drm/amd/display: Skip DPP DTO update if root clock is gated

[Why]
Hardware implements root clock gating by utilizing the DPP DTO registers
with a special case of DTO enabled, phase = 0, modulo = 1. This
conflicts with our policy to always update the DPPDTO for cases where
it's expected to be disabled.

The pipes unexpectedly enter a higher power state than expected because
of this programming flow.

[How]
Guard the upper layers of HWSS against this hardware quirk with
programming the register with an internal state flag in DCCG.

While technically acting as global state for the DCCG, HWSS shouldn't be
expected to understand the hardware quirk for having DTO disabled
causing more power than DTO enabled with this specific setting.

This also prevents sequencing errors from occuring in the future if
we have to program DPP DTO in multiple locations.

Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Jun Lei <jun.lei@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
index 4c2fdfea162f55cb567e2ac702936221d70eec1a..65c1d754e2d6b1fb173f86d2603fb1a17550b809 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
@@ -47,6 +47,14 @@ void dccg31_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk)
 {
        struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
 
+       if (dccg->dpp_clock_gated[dpp_inst]) {
+               /*
+                * Do not update the DPPCLK DTO if the clock is stopped.
+                * It is treated the same as if the pipe itself were in PG.
+                */
+               return;
+       }
+
        if (dccg->ref_dppclk && req_dppclk) {
                int ref_dppclk = dccg->ref_dppclk;
                int modulo, phase;

diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c
index e0e7d32bb1a0e28c5c9bdba68e14c61aca76e6d6..cf23d7bc560a6c92aef84c00f1b081a59b21a6bd 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c
@@ -332,6 +332,9 @@ static void dccg314_dpp_root_clock_control(
 {
        struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
 
+       if (dccg->dpp_clock_gated[dpp_inst] == clock_on)
+               return;
+
        if (clock_on) {
                /* turn off the DTO and leave phase/modulo at max */
                REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_ENABLE[dpp_inst], 0);
@@ -345,6 +348,8 @@ static void dccg314_dpp_root_clock_control(
                          DPPCLK0_DTO_PHASE, 0,
                          DPPCLK0_DTO_MODULO, 1);
        }
+
+       dccg->dpp_clock_gated[dpp_inst] = !clock_on;
 }
 
 static const struct dccg_funcs dccg314_funcs = {

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
index 0b700b3d7d9725145d9920c1f8608290dc1fc27c..8dc804bbe98bd11e89b1cb9578be40935399b317 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
@@ -68,6 +68,7 @@ struct dccg {
        const struct dccg_funcs *funcs;
        int pipe_dppclk_khz[MAX_PIPES];
        int ref_dppclk;
+       bool dpp_clock_gated[MAX_PIPES];
        //int dtbclk_khz[MAX_PIPES];/* TODO needs to be removed */
        //int audio_dtbclk_khz;/* TODO needs to be removed */
        //int ref_dtbclk_khz;/* TODO needs to be removed */