arm64: dts: mediatek: mt8195-cherry: Assign sram supply to MFG1 pd

Add a phandle to the MT8195_POWER_DOMAIN_MFG1 power domain and
assign the GPU SRAM (vsram_others) supply to that in mt8195-cherry:
this allows to keep the sram powered up while the GPU is used.

This means that it's now possible to remove the regulator-always-on
property from the mt6359_vsram_others_ldo_reg vreg, so that it will
be switched on and off during suspend.

Tested-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
index 07b643065a588edfb0cf965a002854bade4a4b82..5cfe104ee13658aa790fbe53d6678518e048dcd5 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
@@ -480,6 +480,10 @@
        domain-supply = <&mt6315_7_vbuck1>;
 };
 
+&mfg1 {
+       domain-supply = <&mt6359_vsram_others_ldo_reg>;
+};
+
 &mmc0 {
        status = "okay";
 
@@ -550,7 +554,6 @@
 
 /* for GPU SRAM */
 &mt6359_vsram_others_ldo_reg {
-       regulator-always-on;
        regulator-min-microvolt = <750000>;
        regulator-max-microvolt = <750000>;
 };

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 54c674c45b49a27c223b4240db452284f01f5f15..0d7735778709c1b4951ed38bd466f744a34500a8 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -538,7 +538,7 @@
                                        #size-cells = <0>;
                                        #power-domain-cells = <1>;
 
-                                       power-domain@MT8195_POWER_DOMAIN_MFG1 {
+                                       mfg1: power-domain@MT8195_POWER_DOMAIN_MFG1 {
                                                reg = <MT8195_POWER_DOMAIN_MFG1>;
                                                clocks = <&apmixedsys CLK_APMIXED_MFGPLL>,
                                                         <&topckgen CLK_TOP_MFG_CORE_TMP>;