arm64: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node

The sdmmc controller's CIU(Card Interface Unit) clock's phase can be
adjusted through the register in the system manager. Add the binding
"altr,sysmgr-syscon" to the SDMMC node for the driver to access the
system manager. Add the "clk-phase-sd-hs" property in the SDMMC node to
designate the smpsel and drvsel properties for the CIU clock.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
index 14c220d87807d5ab28a7f465fa17a497cfb6f069..55c5e1fdddc72ea8e73630ea3bb6a49b2d4cd051 100644 (file)
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
@@ -309,6 +309,7 @@
                                 <&clkmgr STRATIX10_SDMMC_CLK>;
                        clock-names = "biu", "ciu";
                        iommus = <&smmu 5>;
+                       altr,sysmgr-syscon = <&sysmgr 0x28 4>;
                        status = "disabled";
                };
 

diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
index 48424e459f125aa0c82e3bbcd4c8314748eac7c3..19e7284b4cd5fae841f979bc4d253b0ef2ebb3a7 100644 (file)
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
@@ -105,6 +105,7 @@
        cap-mmc-highspeed;
        broken-cd;
        bus-width = <4>;
+       clk-phase-sd-hs = <0>, <135>;
 };
 
 &osc1 {

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
index 7bbec8aafa628d365c7dc7036d42c57015450255..849b46dd80982029085c315dbc11cfba187e6c6c 100644 (file)
--- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
@@ -313,6 +313,7 @@
                                 <&clkmgr AGILEX_SDMMC_CLK>;
                        clock-names = "biu", "ciu";
                        iommus = <&smmu 5>;
+                       altr,sysmgr-syscon = <&sysmgr 0x28 4>;
                        status = "disabled";
                };
 

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
index 26cd3c121757401f0697378248e0e6a89693c975..07c3f887661377808b364b21c128573484a1d2e1 100644 (file)
--- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
@@ -83,6 +83,7 @@
        cap-sd-highspeed;
        broken-cd;
        bus-width = <4>;
+       clk-phase-sd-hs = <0>, <135>;
 };
 
 &osc1 {

diff --git a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
index 62c66e52b65628758e644d9b22038870db18a660..08c08857127067d2242ac3a88089fda9498d3811 100644 (file)
--- a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
@@ -74,6 +74,7 @@
        cap-sd-highspeed;
        broken-cd;
        bus-width = <4>;
+       clk-phase-sd-hs = <0>, <135>;
 };
 
 &osc1 {