void simulate_rdmsr(CPUX86State *env)
{
- X86CPU *x86_cpu = env_archcpu(env);
+ X86CPU *cpu = env_archcpu(env);
CPUState *cs = env_cpu(env);
uint32_t msr = ECX(env);
uint64_t val = 0;
val = rdtscp() + rvmcs(cs->accel->fd, VMCS_TSC_OFFSET);
break;
case MSR_IA32_APICBASE:
- val = cpu_get_apic_base(x86_cpu->apic_state);
+ val = cpu_get_apic_base(cpu->apic_state);
break;
case MSR_IA32_UCODE_REV:
- val = x86_cpu->ucode_rev;
+ val = cpu->ucode_rev;
break;
case MSR_EFER:
val = rvmcs(cs->accel->fd, VMCS_GUEST_IA32_EFER);
void simulate_wrmsr(CPUX86State *env)
{
- X86CPU *x86_cpu = env_archcpu(env);
+ X86CPU *cpu = env_archcpu(env);
CPUState *cs = env_cpu(env);
uint32_t msr = ECX(env);
uint64_t data = ((uint64_t)EDX(env) << 32) | EAX(env);
case MSR_IA32_TSC:
break;
case MSR_IA32_APICBASE:
- cpu_set_apic_base(x86_cpu->apic_state, data);
+ cpu_set_apic_base(cpu->apic_state, data);
break;
case MSR_FSBASE:
wvmcs(cs->accel->fd, VMCS_GUEST_FS_BASE, data);
void load_regs(CPUState *cs)
{
- X86CPU *x86_cpu = X86_CPU(cs);
- CPUX86State *env = &x86_cpu->env;
+ X86CPU *cpu = X86_CPU(cs);
+ CPUX86State *env = &cpu->env;
int i = 0;
RRX(env, R_EAX) = rreg(cs->accel->fd, HV_X86_RAX);
void store_regs(CPUState *cs)
{
- X86CPU *x86_cpu = X86_CPU(cs);
- CPUX86State *env = &x86_cpu->env;
+ X86CPU *cpu = X86_CPU(cs);
+ CPUX86State *env = &cpu->env;
int i = 0;
wreg(cs->accel->fd, HV_X86_RAX, RAX(env));