Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core.
It shares common functions with the PCIe DesignWare core driver and
inherits common properties defined in
-Documentation/devicetree/bindings/pci/designware-pcie.txt.
+Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
Additional properties are described here:
- phy-names: must contain "pcie"
- device_type:
- should be "pci". As specified in designware-pcie.txt
+ should be "pci". As specified in snps,dw-pcie.yaml
Example configuration:
* Axis ARTPEC-6 PCIe interface
This PCIe host controller is based on the Synopsys DesignWare PCIe IP
-and thus inherits all the common properties defined in designware-pcie.txt.
+and thus inherits all the common properties defined in snps,dw-pcie.yaml.
Required properties:
- compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode;
* Freescale i.MX6 PCIe interface
This PCIe host controller is based on the Synopsys DesignWare PCIe IP
-and thus inherits all the common properties defined in designware-pcie.txt.
+and thus inherits all the common properties defined in snps,dw-pcie.yaml.
Required properties:
- compatible:
The HiSilicon STB PCIe host controller is based on the DesignWare PCIe core.
It shares common functions with the DesignWare PCIe core driver and inherits
common properties defined in
-Documentation/devicetree/bindings/pci/designware-pcie.txt.
+Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
Additional properties are described here:
Kirin PCIe host controller is based on the Synopsys DesignWare PCI core.
It shares common functions with the PCIe DesignWare core driver and
inherits common properties defined in
-Documentation/devicetree/bindings/pci/designware-pcie.txt.
+Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
Additional properties are described here:
Freescale Layerscape PCIe controller
This PCIe host controller is based on the Synopsys DesignWare PCIe IP
-and thus inherits all the common properties defined in designware-pcie.txt.
+and thus inherits all the common properties defined in snps,dw-pcie.yaml.
This controller derives its clocks from the Reset Configuration Word (RCW)
which is used to describe the PLL settings at the time of chip-reset.
NVIDIA Tegra PCIe controller (Synopsys DesignWare Core based)
This PCIe controller is based on the Synopsis Designware PCIe IP
-and thus inherits all the common properties defined in designware-pcie.txt.
+and thus inherits all the common properties defined in snps,dw-pcie.yaml and
+snps,dw-pcie-ep.yaml.
Some of the controller instances are dual mode where in they can work either
in root port mode or endpoint mode but one at a time.
property.
- reg-names: Must include the following entries:
"appl": Controller's application logic registers
- "config": As per the definition in designware-pcie.txt
+ "config": As per the definition in snps,dw-pcie.yaml
"atu_dma": iATU and DMA registers. This is where the iATU (internal Address
Translation Unit) registers of the PCIe core are made available
for SW access.
* Marvell Armada 7K/8K PCIe interface
This PCIe host controller is based on the Synopsys DesignWare PCIe IP
-and thus inherits all the common properties defined in designware-pcie.txt.
+and thus inherits all the common properties defined in snps,dw-pcie.yaml.
Required properties:
- compatible: "marvell,armada8k-pcie"
Amazon's Annapurna Labs PCIe Host Controller is based on the Synopsys DesignWare
PCI core. It inherits common properties defined in
-Documentation/devicetree/bindings/pci/designware-pcie.txt.
+Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
Properties of the host controller node that differ from it are:
- device_type:
Usage: required
Value type: <string>
- Definition: Should be "pci". As specified in designware-pcie.txt
+ Definition: Should be "pci". As specified in snps,dw-pcie.yaml
- #address-cells:
Usage: required
Value type: <u32>
- Definition: Should be 3. As specified in designware-pcie.txt
+ Definition: Should be 3. As specified in snps,dw-pcie.yaml
- #size-cells:
Usage: required
Value type: <u32>
- Definition: Should be 2. As specified in designware-pcie.txt
+ Definition: Should be 2. As specified in snps,dw-pcie.yaml
- ranges:
Usage: required
Value type: <prop-encoded-array>
- Definition: As specified in designware-pcie.txt
+ Definition: As specified in snps,dw-pcie.yaml
- interrupts:
Usage: required
- #interrupt-cells:
Usage: required
Value type: <u32>
- Definition: Should be 1. As specified in designware-pcie.txt
+ Definition: Should be 1. As specified in snps,dw-pcie.yaml
- interrupt-map-mask:
Usage: required
Value type: <prop-encoded-array>
- Definition: As specified in designware-pcie.txt
+ Definition: As specified in snps,dw-pcie.yaml
- interrupt-map:
Usage: required
Value type: <prop-encoded-array>
- Definition: As specified in designware-pcie.txt
+ Definition: As specified in snps,dw-pcie.yaml
- clocks:
Usage: required
description: |+
Exynos5433 SoC PCIe host controller is based on the Synopsys DesignWare
PCIe IP and thus inherits all the common properties defined in
- designware-pcie.txt.
+ snps,dw-pcie.yaml.
allOf:
- - $ref: /schemas/pci/pci-bus.yaml#
+ - $ref: /schemas/pci/snps,dw-pcie.yaml#
properties:
compatible:
SiFive FU740 PCIe host controller is based on the Synopsys DesignWare
PCI core. It shares common features with the PCIe DesignWare core and
inherits common properties defined in
- Documentation/devicetree/bindings/pci/designware-pcie.txt.
+ Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
maintainers:
- Paul Walmsley <paul.walmsley@sifive.com>
- Greentime Hu <greentime.hu@sifive.com>
allOf:
- - $ref: /schemas/pci/pci-bus.yaml#
+ - $ref: /schemas/pci/snps,dw-pcie.yaml#
properties:
compatible:
UniPhier PCIe endpoint controller is based on the Synopsys DesignWare
PCI core. It shares common features with the PCIe DesignWare core and
inherits common properties defined in
- Documentation/devicetree/bindings/pci/designware-pcie.txt.
+ Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml.
maintainers:
- Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
allOf:
- - $ref: "pci-ep.yaml#"
+ - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
properties:
compatible:
number of PHYs as specified in *phys* property.
- ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
where <X> is the instance number of the pcie from the HW spec.
- - num-lanes as specified in ../designware-pcie.txt
+ - num-lanes as specified in ../snps,dw-pcie.yaml
- ti,syscon-lane-sel : phandle/offset pair. Phandle to the system control
module and the register offset to specify lane
selection.
device_type,
ranges,
interrupt-map-mask,
- interrupt-map : as specified in ../designware-pcie.txt
+ interrupt-map : as specified in ../snps,dw-pcie.yaml
- ti,syscon-unaligned-access: phandle to the syscon DT node. The 1st argument
should contain the register offset within syscon
and the 2nd argument should contain the bit field
UniPhier PCIe host controller is based on the Synopsys DesignWare PCI core.
It shares common functions with the PCIe DesignWare core driver and inherits
common properties defined in
-Documentation/devicetree/bindings/pci/designware-pcie.txt.
+Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
Required properties:
- compatible: Should be "socionext,uniphier-pcie".
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