[IA64] Add dp bit to cache and bus check structs

Rev 2.2 of Volume 2 of "Intel Itanium Architecture Software Developer's
Manual" (January 2006) adds a dp bit to the cache_check and bus_check
fields (pages 2:401-2:404).  This patch gets the structs back in sync
with the spec.

Signed-off-by: Russ Anderson (rja@sgi.com)
Signed-off-by: Tony Luck <tony.luck@intel.com>

diff --git a/include/asm-ia64/pal.h b/include/asm-ia64/pal.h
index 4283ddcc25fbf69a50cfce33483fbbf203023ff9..b6d4f6f0c3c8218c18c705e1de13677b51002978 100644 (file)
--- a/include/asm-ia64/pal.h
+++ b/include/asm-ia64/pal.h
@@ -487,10 +487,12 @@ typedef struct pal_cache_check_info_s {
                                                 * error occurred
                                                 */
                        wiv             : 1,    /* Way field valid */
-                       reserved2       : 10,
+                       reserved2       : 1,
+                       dp              : 1,    /* Data poisoned on MBE */
+                       reserved3       : 8,
 
                        index           : 20,   /* Cache line index */
-                       reserved3       : 2,
+                       reserved4       : 2,
 
                        is              : 1,    /* instruction set (1 == ia32) */
                        iv              : 1,    /* instruction set field valid */
@@ -557,7 +559,7 @@ typedef struct pal_bus_check_info_s {
                        type            : 8,    /* Bus xaction type*/
                        sev             : 5,    /* Bus error severity*/
                        hier            : 2,    /* Bus hierarchy level */
-                       reserved1       : 1,
+                       dp              : 1,    /* Data poisoned on MBE */
                        bsi             : 8,    /* Bus error status
                                                 * info
                                                 */