clk: renesas: rzg2l: Add support to handle coupled clocks

The AXI and CHI clocks use the same register bit for controlling clock
output. Add a new clock type for coupled clocks, which sets the
CPG_CLKON_ETH.CLK[01]_ON bit when at least one clock is enabled, and
clears the bit only when both clocks are disabled.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210922155145.28156-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 69eba5a66490e9ed025d96086d9a85b688068de1..1501547a11a3ad307b4ff53f834414a4ebb99434 100644 (file)
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -333,13 +333,17 @@ fail:
  * @hw: handle between common and hardware-specific interfaces
  * @off: register offset
  * @bit: ON/MON bit
+ * @enabled: soft state of the clock, if it is coupled with another clock
  * @priv: CPG/MSTP private data
+ * @sibling: pointer to the other coupled clock
  */
 struct mstp_clock {
        struct clk_hw hw;
        u16 off;
        u8 bit;
+       bool enabled;
        struct rzg2l_cpg_priv *priv;
+       struct mstp_clock *sibling;
 };
 
 #define to_mod_clock(_hw) container_of(_hw, struct mstp_clock, hw)
@@ -392,11 +396,41 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable)
 
 static int rzg2l_mod_clock_enable(struct clk_hw *hw)
 {
+       struct mstp_clock *clock = to_mod_clock(hw);
+
+       if (clock->sibling) {
+               struct rzg2l_cpg_priv *priv = clock->priv;
+               unsigned long flags;
+               bool enabled;
+
+               spin_lock_irqsave(&priv->rmw_lock, flags);
+               enabled = clock->sibling->enabled;
+               clock->enabled = true;
+               spin_unlock_irqrestore(&priv->rmw_lock, flags);
+               if (enabled)
+                       return 0;
+       }
+
        return rzg2l_mod_clock_endisable(hw, true);
 }
 
 static void rzg2l_mod_clock_disable(struct clk_hw *hw)
 {
+       struct mstp_clock *clock = to_mod_clock(hw);
+
+       if (clock->sibling) {
+               struct rzg2l_cpg_priv *priv = clock->priv;
+               unsigned long flags;
+               bool enabled;
+
+               spin_lock_irqsave(&priv->rmw_lock, flags);
+               enabled = clock->sibling->enabled;
+               clock->enabled = false;
+               spin_unlock_irqrestore(&priv->rmw_lock, flags);
+               if (enabled)
+                       return;
+       }
+
        rzg2l_mod_clock_endisable(hw, false);
 }
 
@@ -412,6 +446,9 @@ static int rzg2l_mod_clock_is_enabled(struct clk_hw *hw)
                return 1;
        }
 
+       if (clock->sibling)
+               return clock->enabled;
+
        value = readl(priv->base + CLK_MON_R(clock->off));
 
        return value & bitmask;
@@ -423,6 +460,28 @@ static const struct clk_ops rzg2l_mod_clock_ops = {
        .is_enabled = rzg2l_mod_clock_is_enabled,
 };
 
+static struct mstp_clock
+*rzg2l_mod_clock__get_sibling(struct mstp_clock *clock,
+                             struct rzg2l_cpg_priv *priv)
+{
+       struct clk_hw *hw;
+       unsigned int i;
+
+       for (i = 0; i < priv->num_mod_clks; i++) {
+               struct mstp_clock *clk;
+
+               if (priv->clks[priv->num_core_clks + i] == ERR_PTR(-ENOENT))
+                       continue;
+
+               hw = __clk_get_hw(priv->clks[priv->num_core_clks + i]);
+               clk = to_mod_clock(hw);
+               if (clock->off == clk->off && clock->bit == clk->bit)
+                       return clk;
+       }
+
+       return NULL;
+}
+
 static void __init
 rzg2l_cpg_register_mod_clk(const struct rzg2l_mod_clk *mod,
                           const struct rzg2l_cpg_info *info,
@@ -484,6 +543,18 @@ rzg2l_cpg_register_mod_clk(const struct rzg2l_mod_clk *mod,
 
        dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
        priv->clks[id] = clk;
+
+       if (mod->is_coupled) {
+               struct mstp_clock *sibling;
+
+               clock->enabled = rzg2l_mod_clock_is_enabled(&clock->hw);
+               sibling = rzg2l_mod_clock__get_sibling(clock, priv);
+               if (sibling) {
+                       clock->sibling = sibling;
+                       sibling->sibling = clock;
+               }
+       }
+
        return;
 
 fail:

diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h
index 5202c0512483aa63d09da55c3a792eb840251df6..191c403aa52f7ba28d7f4f7108e5ef512d9d0b41 100644 (file)
--- a/drivers/clk/renesas/rzg2l-cpg.h
+++ b/drivers/clk/renesas/rzg2l-cpg.h
@@ -93,6 +93,7 @@ enum clk_types {
  * @parent: id of parent clock
  * @off: register offset
  * @bit: ON/MON bit
+ * @is_coupled: flag to indicate coupled clock
  */
 struct rzg2l_mod_clk {
        const char *name;
@@ -100,17 +101,25 @@ struct rzg2l_mod_clk {
        unsigned int parent;
        u16 off;
        u8 bit;
+       bool is_coupled;
 };
 
-#define DEF_MOD(_name, _id, _parent, _off, _bit)       \
+#define DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _is_coupled)     \
        { \
                .name = _name, \
                .id = MOD_CLK_BASE + (_id), \
                .parent = (_parent), \
                .off = (_off), \
                .bit = (_bit), \
+               .is_coupled = (_is_coupled), \
        }
 
+#define DEF_MOD(_name, _id, _parent, _off, _bit)       \
+       DEF_MOD_BASE(_name, _id, _parent, _off, _bit, false)
+
+#define DEF_COUPLED(_name, _id, _parent, _off, _bit)   \
+       DEF_MOD_BASE(_name, _id, _parent, _off, _bit, true)
+
 /**
  * struct rzg2l_reset - Reset definitions
  *