Add the "timing-adjustment" clock now that we know how it is connected
to the PRG_ETHERNET registers. It is used internally to generate the
RGMII RX delay on the MAC side (if needed).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lore.kernel.org/r/20200620162347.26159-1-martin.blumenstingl@googlemail.com
                        interrupt-names = "macirq";
                        clocks = <&clkc CLKID_ETH>,
                                 <&clkc CLKID_FCLK_DIV2>,
-                                <&clkc CLKID_MPLL2>;
-                       clock-names = "stmmaceth", "clkin0", "clkin1";
+                                <&clkc CLKID_MPLL2>,
+                                <&clkc CLKID_FCLK_DIV2>;
+                       clock-names = "stmmaceth", "clkin0", "clkin1",
+                                     "timing-adjustment";
                        rx-fifo-depth = <4096>;
                        tx-fifo-depth = <2048>;
                        status = "disabled";
 
                        interrupt-names = "macirq";
                        clocks = <&clkc CLKID_ETH>,
                                 <&clkc CLKID_FCLK_DIV2>,
-                                <&clkc CLKID_MPLL2>;
-                       clock-names = "stmmaceth", "clkin0", "clkin1";
+                                <&clkc CLKID_MPLL2>,
+                                <&clkc CLKID_FCLK_DIV2>;
+                       clock-names = "stmmaceth", "clkin0", "clkin1",
+                                     "timing-adjustment";
                        rx-fifo-depth = <4096>;
                        tx-fifo-depth = <2048>;
                        status = "disabled";
 
 ðmac {
        clocks = <&clkc CLKID_ETH>,
                 <&clkc CLKID_FCLK_DIV2>,
-                <&clkc CLKID_MPLL2>;
-       clock-names = "stmmaceth", "clkin0", "clkin1";
+                <&clkc CLKID_MPLL2>,
+                <&clkc CLKID_FCLK_DIV2>;
+       clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
 };
 
 &gpio_intc {
 
 ðmac {
        clocks = <&clkc CLKID_ETH>,
                 <&clkc CLKID_FCLK_DIV2>,
-                <&clkc CLKID_MPLL2>;
-       clock-names = "stmmaceth", "clkin0", "clkin1";
+                <&clkc CLKID_MPLL2>,
+                <&clkc CLKID_FCLK_DIV2>;
+       clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
 
        mdio0: mdio {
                #address-cells = <1>;