arm64: dts: amlogic: Add the Ethernet "timing-adjustment" clock
authorMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Sat, 20 Jun 2020 16:23:47 +0000 (18:23 +0200)
committerKevin Hilman <khilman@baylibre.com>
Mon, 13 Jul 2020 18:57:46 +0000 (11:57 -0700)
Add the "timing-adjustment" clock now that we know how it is connected
to the PRG_ETHERNET registers. It is used internally to generate the
RGMII RX delay on the MAC side (if needed).

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lore.kernel.org/r/20200620162347.26159-1-martin.blumenstingl@googlemail.com
arch/arm64/boot/dts/amlogic/meson-axg.dtsi
arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi

index 8e6281c685fad7017f1da324ea844bdea0fe0564..b9efc8469265d871d244c2cb2a89be88152d0bf2 100644 (file)
                        interrupt-names = "macirq";
                        clocks = <&clkc CLKID_ETH>,
                                 <&clkc CLKID_FCLK_DIV2>,
-                                <&clkc CLKID_MPLL2>;
-                       clock-names = "stmmaceth", "clkin0", "clkin1";
+                                <&clkc CLKID_MPLL2>,
+                                <&clkc CLKID_FCLK_DIV2>;
+                       clock-names = "stmmaceth", "clkin0", "clkin1",
+                                     "timing-adjustment";
                        rx-fifo-depth = <4096>;
                        tx-fifo-depth = <2048>;
                        status = "disabled";
index 593a006f4b7b3944f1a1095c0ad801c7ad68130c..41805f2ed8fc188f053eb8850ef78c4c8b2fbd1d 100644 (file)
                        interrupt-names = "macirq";
                        clocks = <&clkc CLKID_ETH>,
                                 <&clkc CLKID_FCLK_DIV2>,
-                                <&clkc CLKID_MPLL2>;
-                       clock-names = "stmmaceth", "clkin0", "clkin1";
+                                <&clkc CLKID_MPLL2>,
+                                <&clkc CLKID_FCLK_DIV2>;
+                       clock-names = "stmmaceth", "clkin0", "clkin1",
+                                     "timing-adjustment";
                        rx-fifo-depth = <4096>;
                        tx-fifo-depth = <2048>;
                        status = "disabled";
index 8bf6295716e06ea1584f48baf32f289fcdc1ff6f..ea50dd434887eddbc0aa015707d4e6f3517be7f9 100644 (file)
 &ethmac {
        clocks = <&clkc CLKID_ETH>,
                 <&clkc CLKID_FCLK_DIV2>,
-                <&clkc CLKID_MPLL2>;
-       clock-names = "stmmaceth", "clkin0", "clkin1";
+                <&clkc CLKID_MPLL2>,
+                <&clkc CLKID_FCLK_DIV2>;
+       clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
 };
 
 &gpio_intc {
index fe7aaf8873f2cccf6d47888999bf2bb46bd7b883..beb5fc79d18662c18ae33aeb6f568b6316cff5d1 100644 (file)
 &ethmac {
        clocks = <&clkc CLKID_ETH>,
                 <&clkc CLKID_FCLK_DIV2>,
-                <&clkc CLKID_MPLL2>;
-       clock-names = "stmmaceth", "clkin0", "clkin1";
+                <&clkc CLKID_MPLL2>,
+                <&clkc CLKID_FCLK_DIV2>;
+       clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
 
        mdio0: mdio {
                #address-cells = <1>;