clk: qcom: ipq8074: fix missing GPLL0 divider width

GPLL0 uses 4 bits post divider which should be specified
in clock driver structure.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c
index ed2d00f553780865115e0b7a1270bfdb1183a8aa..99906f6a8264aef2a2cc61562994efe5db372953 100644 (file)
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -84,6 +84,7 @@ static struct clk_fixed_factor gpll0_out_main_div2 = {
 static struct clk_alpha_pll_postdiv gpll0 = {
        .offset = 0x21000,
        .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .width = 4,
        .clkr.hw.init = &(struct clk_init_data){
                .name = "gpll0",
                .parent_names = (const char *[]){