ARM: dts: dra7: Use clksel binding for CTRL_CORE_SMA_SW_0

On dra76x, most dpll_gmac output clksel clocks are in registers from
CM_CLKSEL_DPLL_GMAC to CM_DIV_H13_DPLL_GMAC. In addition to that, there
are there more clocks in the CTRL_CORE_SMA_SW_0 register.

Let's group the CTRL_CORE_SMA_SW_0 clocks using the clksel binding to
reduce make W=1 dtbs unique_unit_address warnings, and stop using the
custom the ti,bit-shift property in favor of the standard reg property.

Let's also add a comment for the CTRL_CORE_SMA_SW_0 clock that matches the
documentation.

Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/boot/dts/ti/omap/dra76x.dtsi b/arch/arm/boot/dts/ti/omap/dra76x.dtsi
index 1045eb24aa0dbc2e81e8218371d669ce85a5235a..50a02c393ea27855f86c9d9a153877ea1c5dfc4f 100644 (file)
--- a/arch/arm/boot/dts/ti/omap/dra76x.dtsi
+++ b/arch/arm/boot/dts/ti/omap/dra76x.dtsi
@@ -84,35 +84,44 @@
 };
 
 &scm_conf_clocks {
-       dpll_gmac_h14x2_ctrl_ck: dpll_gmac_h14x2_ctrl_ck@3fc {
-               #clock-cells = <0>;
-               compatible = "ti,divider-clock";
-               clocks = <&dpll_gmac_x2_ck>;
-               ti,max-div = <63>;
-               reg = <0x03fc>;
-               ti,bit-shift = <20>;
-               ti,latch-bit = <26>;
-               assigned-clocks = <&dpll_gmac_h14x2_ctrl_ck>;
-               assigned-clock-rates = <80000000>;
-       };
-
-       dpll_gmac_h14x2_ctrl_mux_ck: dpll_gmac_h14x2_ctrl_mux_ck@3fc {
-               #clock-cells = <0>;
-               compatible = "ti,mux-clock";
-               clocks = <&dpll_gmac_ck>, <&dpll_gmac_h14x2_ctrl_ck>;
+       /* CTRL_CORE_SMA_SW_0 */
+       clock@3fc {
+               compatible = "ti,clksel";
                reg = <0x3fc>;
-               ti,bit-shift = <29>;
-               ti,latch-bit = <26>;
-               assigned-clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>;
-               assigned-clock-parents = <&dpll_gmac_h14x2_ctrl_ck>;
-       };
+               #clock-cells = <2>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               dpll_gmac_h14x2_ctrl_ck: clock@20 {
+                       reg = <20>;
+                       clock-output-names = "dpll_gmac_h14x2_ctrl_ck";
+                       compatible = "ti,divider-clock";
+                       clocks = <&dpll_gmac_x2_ck>;
+                       ti,max-div = <63>;
+                       ti,latch-bit = <26>;
+                       assigned-clocks = <&dpll_gmac_h14x2_ctrl_ck>;
+                       assigned-clock-rates = <80000000>;
+                       #clock-cells = <0>;
+               };
 
-       mcan_clk: mcan_clk@3fc {
-               #clock-cells = <0>;
-               compatible = "ti,gate-clock";
-               clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>;
-               ti,bit-shift = <27>;
-               reg = <0x3fc>;
+               mcan_clk: clock@27 {
+                       reg = <27>;
+                       clock-output-names = "mcan_clk";
+                       compatible = "ti,gate-clock";
+                       clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>;
+                       #clock-cells = <0>;
+               };
+
+               dpll_gmac_h14x2_ctrl_mux_ck: clock@29 {
+                       reg = <29>;
+                       clock-output-names = "dpll_gmac_h14x2_ctrl_mux_ck";
+                       compatible = "ti,mux-clock";
+                       clocks = <&dpll_gmac_ck>, <&dpll_gmac_h14x2_ctrl_ck>;
+                       ti,latch-bit = <26>;
+                       assigned-clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>;
+                       assigned-clock-parents = <&dpll_gmac_h14x2_ctrl_ck>;
+                       #clock-cells = <0>;
+               };
        };
 };