/**
  * stm32h7_spi_prepare_fthlv - Determine FIFO threshold level
  * @spi: pointer to the spi controller data structure
+ * @xfer_len: length of the message to be transferred
  */
-static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi)
+static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi, u32 xfer_len)
 {
-       u32 fthlv, half_fifo;
+       u32 fthlv, half_fifo, packet;
 
        /* data packet should not exceed 1/2 of fifo space */
        half_fifo = (spi->fifo_size / 2);
 
+       /* data_packet should not exceed transfer length */
+       if (half_fifo > xfer_len)
+               packet = xfer_len;
+       else
+               packet = half_fifo;
+
        if (spi->cur_bpw <= 8)
-               fthlv = half_fifo;
+               fthlv = packet;
        else if (spi->cur_bpw <= 16)
-               fthlv = half_fifo / 2;
+               fthlv = packet / 2;
        else
-               fthlv = half_fifo / 4;
+               fthlv = packet / 4;
 
        /* align packet size with data registers access */
        if (spi->cur_bpw > 8)
        else
                fthlv -= (fthlv % 4); /* multiple of 4 */
 
+       if (!fthlv)
+               fthlv = 1;
+
        return fthlv;
 }
 
        cfg1_setb |= (bpw << STM32H7_SPI_CFG1_DSIZE_SHIFT) &
                     STM32H7_SPI_CFG1_DSIZE;
 
-       spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi);
+       spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi, spi->cur_xferlen);
        fthlv = spi->cur_fthlv - 1;
 
        cfg1_clrb |= STM32H7_SPI_CFG1_FTHLV;
 
        spin_lock_irqsave(&spi->lock, flags);
 
+       spi->cur_xferlen = transfer->len;
+
        if (spi->cur_bpw != transfer->bits_per_word) {
                spi->cur_bpw = transfer->bits_per_word;
                spi->cfg->set_bpw(spi);
                        goto out;
        }
 
-       spi->cur_xferlen = transfer->len;
-
        dev_dbg(spi->dev, "transfer communication mode set to %d\n",
                spi->cur_comm);
        dev_dbg(spi->dev,