net: hns3: expand the tc config command

The device HNAE3_DEVICE_VERSION_V3 supports up to 1280 queues
and qsets for one function, so the bitwidth of tc_offset, meaning
the tqps index, needs to expand from 10 bits to 11 bits.

The device HNAE3_DEVICE_VERSION_V3 supports up to 512 queues on
one TC. The tc_size, meaning the exponent with base 2 of queues
supported on TC, which needs to expand from 3 bits to 4 bits.

Signed-off-by: Guojia Liao <liaoguojia@huawei.com>
Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
index 8a37a22a176b2c99b5907209d35493809f5c5e01..c6dc11b32aa7a62a7ab2f364ba924152c79cb377 100644 (file)
--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
@@ -223,11 +223,14 @@ struct hclgevf_rss_indirection_table_cmd {
 };
 
 #define HCLGEVF_RSS_TC_OFFSET_S                0
-#define HCLGEVF_RSS_TC_OFFSET_M                (0x3ff << HCLGEVF_RSS_TC_OFFSET_S)
+#define HCLGEVF_RSS_TC_OFFSET_M                GENMASK(10, 0)
+#define HCLGEVF_RSS_TC_SIZE_MSB_B      11
 #define HCLGEVF_RSS_TC_SIZE_S          12
-#define HCLGEVF_RSS_TC_SIZE_M          (0x7 << HCLGEVF_RSS_TC_SIZE_S)
+#define HCLGEVF_RSS_TC_SIZE_M          GENMASK(14, 12)
 #define HCLGEVF_RSS_TC_VALID_B         15
 #define HCLGEVF_MAX_TC_NUM             8
+#define HCLGEVF_RSS_TC_SIZE_MSB_OFFSET 3
+
 struct hclgevf_rss_tc_mode_cmd {
        __le16 rss_tc_mode[HCLGEVF_MAX_TC_NUM];
        u8 rsv[8];

diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
index ac3afacbc4ce7658e3e3033cb4422706bfbe209a..1682769112d01060f0c78a3d1270d0a4a16983fb 100644 (file)
--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
@@ -706,6 +706,9 @@ static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev,  u16 rss_size)
                              (tc_valid[i] & 0x1));
                hnae3_set_field(mode, HCLGEVF_RSS_TC_SIZE_M,
                                HCLGEVF_RSS_TC_SIZE_S, tc_size[i]);
+               hnae3_set_bit(mode, HCLGEVF_RSS_TC_SIZE_MSB_B,
+                             tc_size[i] >> HCLGEVF_RSS_TC_SIZE_MSB_OFFSET &
+                             0x1);
                hnae3_set_field(mode, HCLGEVF_RSS_TC_OFFSET_M,
                                HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]);