arm64: dts: mediatek: Format mediatek,larbs as an array of phandles

Commit 39bd2b6a3783 ("dt-bindings: Improve phandle-array schemas")
updated the mediatek,larbs property in the mediatek,iommu.yaml
dt-binding to make it clearer that the phandles passed to the property
are independent, rather than subsequent arguments to the first phandle.

Update the mediatek,larbs property in the arm64 Devicetrees to use the
same formatting. This change doesn't impact any behavior: the compiled
dtb is exactly the same. It does however fix the warnings generated by
dtbs_check.

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/r/20220301203147.1143782-2-nfraprado@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index a27b7628c5f7d14c56bc9573176d13b35816d12f..86579330a8bdcc445382596b71d350675e8654ce 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -329,8 +329,8 @@
                interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW>;
                clocks = <&infracfg CLK_INFRA_M4U>;
                clock-names = "bclk";
-               mediatek,larbs = <&larb0 &larb1 &larb2
-                                 &larb3 &larb6>;
+               mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
+                                <&larb3>, <&larb6>;
                #iommu-cells = <1>;
        };
 
@@ -346,7 +346,7 @@
                interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;
                clocks = <&infracfg CLK_INFRA_M4U>;
                clock-names = "bclk";
-               mediatek,larbs = <&larb4 &larb5 &larb7>;
+               mediatek,larbs = <&larb4>, <&larb5>, <&larb7>;
                #iommu-cells = <1>;
        };
 

diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts/mediatek/mt8167.dtsi
index 9029051624a678f1fdcc6064271d57d03587b37f..54655f2feb04d722e111787e9fe701ac6f4b82f1 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi
@@ -174,7 +174,7 @@
                iommu: m4u@10203000 {
                        compatible = "mediatek,mt8167-m4u";
                        reg = <0 0x10203000 0 0x1000>;
-                       mediatek,larbs = <&larb0 &larb1 &larb2>;
+                       mediatek,larbs = <&larb0>, <&larb1>, <&larb2>;
                        interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_LOW>;
                        #iommu-cells = <1>;
                };

diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 2b7d331a458838c5175d08d57d824fe4b31b66cf..042feaedda4a6927ee156723687d489c890c49ef 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -588,8 +588,8 @@
                        interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
                        clocks = <&infracfg CLK_INFRA_M4U>;
                        clock-names = "bclk";
-                       mediatek,larbs = <&larb0 &larb1 &larb2
-                                         &larb3 &larb4 &larb5>;
+                       mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
+                                        <&larb3>, <&larb4>, <&larb5>;
                        #iommu-cells = <1>;
                };
 

diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 4b08691ed39e5ed1997db2f7ef60e2fcf5eb8ee3..5d4a1dd55adc5e7e43fe16bfa948a0139c3fdb61 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -682,8 +682,8 @@
                        compatible = "mediatek,mt8183-m4u";
                        reg = <0 0x10205000 0 0x1000>;
                        interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>;
-                       mediatek,larbs = <&larb0 &larb1 &larb2 &larb3
-                                         &larb4 &larb5 &larb6>;
+                       mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, <&larb3>,
+                                        <&larb4>, <&larb5>, <&larb6>;
                        #iommu-cells = <1>;
                };