drm/amd/display: Correct indentations and spaces

[Why & How]
This fixes indentations and adjust spaces for better readability and
code styles.

Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
index 6450853fea94efbc9d05e45a13ebe40e68551992..645a8991a830089ec52d6e7da551858aaf050374 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
@@ -1731,6 +1731,7 @@ static uint32_t get_ss_entry_number_from_internal_ss_info_tbl_v2_1(
 
        return 0;
 }
+
 /**
  * get_ss_entry_number_from_internal_ss_info_tbl_V3_1
  * Get Number of SpreadSpectrum Entry from the ASIC_InternalSS_Info table of

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
index 9f0f25aee426a4c874c59c4d90e5f865980f851b..c1a5908b97c84cfc5b0c74d9aafbe4fe9c5f8fb5 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
@@ -329,15 +329,14 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p
        }
                break;
        case AMDGPU_FAMILY_GC_11_0_0: {
-           struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);
-
-           if (clk_mgr == NULL) {
-               BREAK_TO_DEBUGGER();
-               return NULL;
-           }
+               struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);
 
-           dcn32_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
-           return &clk_mgr->base;
+               if (clk_mgr == NULL) {
+                       BREAK_TO_DEBUGGER();
+                       return NULL;
+               }
+               dcn32_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
+               return &clk_mgr->base;
        }
 
        case AMDGPU_FAMILY_GC_11_0_1: {

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h
index 047d19ea919c78ff84386c43fbfeeb77dfb82c28..78ca1e5c5e9e67a5d803e8867d5b9daf4ec54980 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h
@@ -37,34 +37,34 @@ typedef enum {
 } WCK_RATIO_e;
 
 typedef struct {
-  uint32_t FClk;
-  uint32_t MemClk;
-  uint32_t Voltage;
-  uint8_t  WckRatio;
-  uint8_t  Spare[3];
+       uint32_t FClk;
+       uint32_t MemClk;
+       uint32_t Voltage;
+       uint8_t  WckRatio;
+       uint8_t  Spare[3];
 } DfPstateTable314_t;
 
 //Freq in MHz
 //Voltage in milli volts with 2 fractional bits
 typedef struct {
-  uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];
-  uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];
-  uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];
-  uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];
-  uint32_t VClocks[NUM_VCN_DPM_LEVELS];
-  uint32_t DClocks[NUM_VCN_DPM_LEVELS];
-  uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];
-  DfPstateTable314_t DfPstateTable[NUM_DF_PSTATE_LEVELS];
+       uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];
+       uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];
+       uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];
+       uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];
+       uint32_t VClocks[NUM_VCN_DPM_LEVELS];
+       uint32_t DClocks[NUM_VCN_DPM_LEVELS];
+       uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];
+       DfPstateTable314_t DfPstateTable[NUM_DF_PSTATE_LEVELS];
 
-  uint8_t  NumDcfClkLevelsEnabled;
-  uint8_t  NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk
-  uint8_t  NumSocClkLevelsEnabled;
-  uint8_t  VcnClkLevelsEnabled;     //Applies to both Vclk and Dclk
-  uint8_t  NumDfPstatesEnabled;
-  uint8_t  spare[3];
+       uint8_t  NumDcfClkLevelsEnabled;
+       uint8_t  NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk
+       uint8_t  NumSocClkLevelsEnabled;
+       uint8_t  VcnClkLevelsEnabled;     //Applies to both Vclk and Dclk
+       uint8_t  NumDfPstatesEnabled;
+       uint8_t  spare[3];
 
-  uint32_t MinGfxClk;
-  uint32_t MaxGfxClk;
+       uint32_t MinGfxClk;
+       uint32_t MaxGfxClk;
 } DpmClocks314_t;
 
 struct dcn314_watermarks {

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index ec4bf9432bdb1894396334e5558a3e126635aaec..96b4f68ec374b63971c28faa37a7a00d67b1aae4 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -340,7 +340,7 @@ struct resource_pool *dc_create_resource_pool(struct dc  *dc,
        return res_pool;
 }
 
-void dc_destroy_resource_pool(struct dc  *dc)
+void dc_destroy_resource_pool(struct dc *dc)
 {
        if (dc) {
                if (dc->res_pool)
@@ -1485,6 +1485,7 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
        struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
        const struct rect odm_slice_rec = calculate_odm_slice_in_timing_active(pipe_ctx);
        bool res = false;
+
        DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
 
        /* Invalid input */

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stat.c b/drivers/gpu/drm/amd/display/dc/core/dc_stat.c
index 5f6392ae31a6605fc1b8dc08d264df629383b5b6..cd6570a1e20ea5bc5837c22d8f6d23de9ba91f30 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stat.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stat.c
@@ -61,7 +61,7 @@ void dc_stat_get_dmub_notification(const struct dc *dc, struct dmub_notification
        /* For HPD/HPD RX, convert dpia port index into link index */
        if (notify->type == DMUB_NOTIFICATION_HPD ||
            notify->type == DMUB_NOTIFICATION_HPD_IRQ ||
-               notify->type == DMUB_NOTIFICATION_DPIA_NOTIFICATION ||
+           notify->type == DMUB_NOTIFICATION_DPIA_NOTIFICATION ||
            notify->type == DMUB_NOTIFICATION_SET_CONFIG_REPLY) {
                notify->link_index =
                        get_link_index_from_dpia_port_index(dc, notify->link_index);