arm64: dts: mt8183: Add complete CPU caches information

This SoC features two clusters composed of:
 - 4x Cortex A53: 32KB I-cache, 2-way set associative,
                  32KB D-cache, 4-way set associative,
                  unified 1MB L2 cache, 16-way set associative;
 - 4x Cortex A73: 64KB I-cache and 64KB D-cache, 4-way set associative,
                  unified 1MB L2 cache, 16-way set associative;

With that in mind, add the appropriate properties needed to specify the
caches information for this SoC, which will now be correctly exported
to sysfs.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221206112330.78431-5-angelogioacchino.delregno@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 268a1f28af8cea1d82b657f33d348db0781b53eb..3d1d7870a5f1bcc1d9255291eef566f7aba9c707 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -336,6 +336,13 @@
                        clock-names = "cpu", "intermediate";
                        operating-points-v2 = <&cluster0_opp>;
                        dynamic-power-coefficient = <84>;
+                       i-cache-size = <32768>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <32768>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <128>;
+                       next-level-cache = <&l2_0>;
                        #cooling-cells = <2>;
                        mediatek,cci = <&cci>;
                };
@@ -352,6 +359,13 @@
                        clock-names = "cpu", "intermediate";
                        operating-points-v2 = <&cluster0_opp>;
                        dynamic-power-coefficient = <84>;
+                       i-cache-size = <32768>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <32768>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <128>;
+                       next-level-cache = <&l2_0>;
                        #cooling-cells = <2>;
                        mediatek,cci = <&cci>;
                };
@@ -368,6 +382,13 @@
                        clock-names = "cpu", "intermediate";
                        operating-points-v2 = <&cluster0_opp>;
                        dynamic-power-coefficient = <84>;
+                       i-cache-size = <32768>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <32768>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <128>;
+                       next-level-cache = <&l2_0>;
                        #cooling-cells = <2>;
                        mediatek,cci = <&cci>;
                };
@@ -384,6 +405,13 @@
                        clock-names = "cpu", "intermediate";
                        operating-points-v2 = <&cluster0_opp>;
                        dynamic-power-coefficient = <84>;
+                       i-cache-size = <32768>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <32768>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <128>;
+                       next-level-cache = <&l2_0>;
                        #cooling-cells = <2>;
                        mediatek,cci = <&cci>;
                };
@@ -400,6 +428,13 @@
                        clock-names = "cpu", "intermediate";
                        operating-points-v2 = <&cluster1_opp>;
                        dynamic-power-coefficient = <211>;
+                       i-cache-size = <65536>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <65536>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <256>;
+                       next-level-cache = <&l2_1>;
                        #cooling-cells = <2>;
                        mediatek,cci = <&cci>;
                };
@@ -416,6 +451,13 @@
                        clock-names = "cpu", "intermediate";
                        operating-points-v2 = <&cluster1_opp>;
                        dynamic-power-coefficient = <211>;
+                       i-cache-size = <65536>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <65536>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <256>;
+                       next-level-cache = <&l2_1>;
                        #cooling-cells = <2>;
                        mediatek,cci = <&cci>;
                };
@@ -432,6 +474,13 @@
                        clock-names = "cpu", "intermediate";
                        operating-points-v2 = <&cluster1_opp>;
                        dynamic-power-coefficient = <211>;
+                       i-cache-size = <65536>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <65536>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <256>;
+                       next-level-cache = <&l2_1>;
                        #cooling-cells = <2>;
                        mediatek,cci = <&cci>;
                };
@@ -448,6 +497,13 @@
                        clock-names = "cpu", "intermediate";
                        operating-points-v2 = <&cluster1_opp>;
                        dynamic-power-coefficient = <211>;
+                       i-cache-size = <65536>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <65536>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <256>;
+                       next-level-cache = <&l2_1>;
                        #cooling-cells = <2>;
                        mediatek,cci = <&cci>;
                };
@@ -481,6 +537,24 @@
                                min-residency-us = <1300>;
                        };
                };
+
+               l2_0: l2-cache0 {
+                       compatible = "cache";
+                       cache-level = <2>;
+                       cache-size = <1048576>;
+                       cache-line-size = <64>;
+                       cache-sets = <1024>;
+                       cache-unified;
+               };
+
+               l2_1: l2-cache1 {
+                       compatible = "cache";
+                       cache-level = <2>;
+                       cache-size = <1048576>;
+                       cache-line-size = <64>;
+                       cache-sets = <1024>;
+                       cache-unified;
+               };
        };
 
        gpu_opp_table: opp-table-0 {