ARM: dts: arm: Fix SP804 users
authorAndre Przywara <andre.przywara@arm.com>
Fri, 28 Aug 2020 14:20:14 +0000 (15:20 +0100)
committerSudeep Holla <sudeep.holla@arm.com>
Mon, 7 Sep 2020 09:49:35 +0000 (10:49 +0100)
The SP804 DT nodes for Realview, MPS2 and VExpress were not complying
with the binding: it requires either one or three clocks, but does not
allow exactly two clocks.

Simply duplicate the first clock to satisfy the binding requirement.
For MPS2, we triple the clock, and add the clock-names property, as this
is required by the Linux primecell driver.
Try to make the clock-names more consistent on the way.

Link: https://lore.kernel.org/r/20200828142018.43298-3-andre.przywara@arm.com
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
arch/arm/boot/dts/arm-realview-pb11mp.dts
arch/arm/boot/dts/mps2.dtsi
arch/arm/boot/dts/vexpress-v2p-ca9.dts

index 9748e0fe800fc96451408e92c1203bdb6b362987..564e2eee2c24c0f123c8eb943e4ed407cb6f8775 100644 (file)
                        clocks = <&sp810_syscon 0>,
                                 <&sp810_syscon 1>,
                                 <&pclk>;
-                       clock-names = "timerclk0",
-                                   "timerclk1",
+                       clock-names = "timer0clk",
+                                   "timer1clk",
                                    "apb_pclk";
                };
 
                        clocks = <&sp810_syscon 2>,
                                 <&sp810_syscon 3>,
                                 <&pclk>;
-                       clock-names = "timerclk2",
-                                   "timerclk3",
+                       clock-names = "timer0clk",
+                                   "timer1clk",
                                    "apb_pclk";
                };
 
                timer45: timer@10018000 {
                        compatible = "arm,sp804", "arm,primecell";
                        reg = <0x10018000 0x1000>;
-                       clocks = <&timclk>, <&pclk>;
-                       clock-names = "timer", "apb_pclk";
+                       clocks = <&timclk>, <&timclk>, <&pclk>;
+                       clock-names = "timer0clk", "timer1clk", "apb_pclk";
                        status = "disabled";
                };
 
                timer67: timer@10019000 {
                        compatible = "arm,sp804", "arm,primecell";
                        reg = <0x10019000 0x1000>;
-                       clocks = <&timclk>, <&pclk>;
-                       clock-names = "timer", "apb_pclk";
+                       clocks = <&timclk>, <&timclk>, <&pclk>;
+                       clock-names = "timer0clk", "timer1clk", "apb_pclk";
                        status = "disabled";
                };
 
index 96fb5a5cf4d32504979d2689d380671d6dc0b9a9..48c34fa282afcad97cee7f9de03972b47ae33f01 100644 (file)
                        };
 
                        timer2: dual-timer@2000 {
-                               compatible = "arm,sp804";
+                               compatible = "arm,sp804", "arm,primecell";
                                reg = <0x2000 0x1000>;
-                               clocks = <&sysclk>;
+                               clocks = <&sysclk>, <&sysclk>, <&sysclk>;
+                               clock-names = "timer0clk", "timer1clk",
+                                              "apb_pclk";
                                interrupts = <10>;
                                status = "disabled";
                        };
index 623246f374485019db2854f4ac0812e5b2f59c5e..6cddea25a292ac990e6f25ec7cd9ad482f0ca298 100644 (file)
                reg = <0x100e4000 0x1000>;
                interrupts = <0 48 4>,
                             <0 49 4>;
-               clocks = <&oscclk2>, <&oscclk2>;
-               clock-names = "timclk", "apb_pclk";
+               clocks = <&oscclk2>, <&oscclk2>, <&oscclk2>;
+               clock-names = "timer0clk", "timer1clk", "apb_pclk";
                status = "disabled";
        };