drm/i915/gt: Temporarily disable CPU caching into DMA for MTL

FIXME: It is suspected that some Address Translation Service (ATS)
issue on IOMMU is causing CAT errors to occur on some MTL workloads.
Applying a write barrier to the ppgtt set entry functions appeared
to have no effect, so we must temporarily use I915_MAP_WC in the
map_pt_dma class of functions on MTL until a proper ATS solution is
found.

Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
CC: Chris Wilson <chris.p.wilson@linux.intel.com>
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Acked-by: Andi Shyti <andi.shyti@linux.intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231102175831.872763-1-jonathan.cavitt@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 4fbed27ef0eccbd192ed8b736cebe2c2de227d3b..21719563a602a49c079b6b161241ee2e7618b42f 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -95,6 +95,16 @@ int map_pt_dma(struct i915_address_space *vm, struct drm_i915_gem_object *obj)
        void *vaddr;
 
        type = intel_gt_coherent_map_type(vm->gt, obj, true);
+       /*
+        * FIXME: It is suspected that some Address Translation Service (ATS)
+        * issue on IOMMU is causing CAT errors to occur on some MTL workloads.
+        * Applying a write barrier to the ppgtt set entry functions appeared
+        * to have no effect, so we must temporarily use I915_MAP_WC here on
+        * MTL until a proper ATS solution is found.
+        */
+       if (IS_METEORLAKE(vm->i915))
+               type = I915_MAP_WC;
+
        vaddr = i915_gem_object_pin_map_unlocked(obj, type);
        if (IS_ERR(vaddr))
                return PTR_ERR(vaddr);
@@ -109,6 +119,16 @@ int map_pt_dma_locked(struct i915_address_space *vm, struct drm_i915_gem_object
        void *vaddr;
 
        type = intel_gt_coherent_map_type(vm->gt, obj, true);
+       /*
+        * FIXME: It is suspected that some Address Translation Service (ATS)
+        * issue on IOMMU is causing CAT errors to occur on some MTL workloads.
+        * Applying a write barrier to the ppgtt set entry functions appeared
+        * to have no effect, so we must temporarily use I915_MAP_WC here on
+        * MTL until a proper ATS solution is found.
+        */
+       if (IS_METEORLAKE(vm->i915))
+               type = I915_MAP_WC;
+
        vaddr = i915_gem_object_pin_map(obj, type);
        if (IS_ERR(vaddr))
                return PTR_ERR(vaddr);