#define SVSB_VOPS_FLD_VOP2_6 GENMASK(23, 16)
#define SVSB_VOPS_FLD_VOP3_7 GENMASK(31, 24)
+/* SVS Thermal Coefficients */
+#define SVSB_TS_COEFF_MT8195 250460
+#define SVSB_TS_COEFF_MT8186 204650
+
/* svs bank related setting */
#define BITS8 8
#define MAX_OPP_ENTRIES 16
* @bank_max: total number of svs banks
* @efuse: svs efuse data received from NVMEM framework
* @tefuse: thermal efuse data received from NVMEM framework
+ * @ts_coeff: thermal sensors coefficient
*/
struct svs_platform {
void __iomem *base;
u32 bank_max;
u32 *efuse;
u32 *tefuse;
+ u32 ts_coeff;
};
struct svs_platform_data {
const struct svs_fusemap *glb_fuse_map;
const u32 *regs;
u32 bank_max;
+ u32 ts_coeff;
};
/**
.probe = svs_mt8192_platform_probe,
.regs = svs_regs_v2,
.bank_max = ARRAY_SIZE(svs_mt8195_banks),
+ .ts_coeff = SVSB_TS_COEFF_MT8195,
.glb_fuse_map = (const struct svs_fusemap[GLB_MAX]) {
{ 0, 0 }, { 19, 4 }
}
.probe = svs_mt8192_platform_probe,
.regs = svs_regs_v2,
.bank_max = ARRAY_SIZE(svs_mt8192_banks),
+ .ts_coeff = SVSB_TS_COEFF_MT8195,
.glb_fuse_map = (const struct svs_fusemap[GLB_MAX]) {
/* FT_PGM not present */
{ -1, 0 }, { 19, 4 }
.probe = svs_mt8192_platform_probe,
.regs = svs_regs_v2,
.bank_max = ARRAY_SIZE(svs_mt8188_banks),
+ .ts_coeff = SVSB_TS_COEFF_MT8195,
.glb_fuse_map = (const struct svs_fusemap[GLB_MAX]) {
/* FT_PGM and VMIN not present */
{ -1, 0 }, { -1, 0 }
.probe = svs_mt8186_platform_probe,
.regs = svs_regs_v2,
.bank_max = ARRAY_SIZE(svs_mt8186_banks),
+ .ts_coeff = SVSB_TS_COEFF_MT8186,
.glb_fuse_map = (const struct svs_fusemap[GLB_MAX]) {
/* FT_PGM and VMIN not present */
{ -1, 0 }, { -1, 0 }
svsp->banks = svsp_data->banks;
svsp->regs = svsp_data->regs;
svsp->bank_max = svsp_data->bank_max;
+ svsp->ts_coeff = svsp_data->ts_coeff;
ret = svsp_data->probe(svsp);
if (ret)