perf jevents: Relocate test events to cpu folder

In future to add support for sys events, relocate the core and uncore
events to a cpu folder.

Signed-off-by: John Garry <john.garry@huawei.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jin Yao <yao.jin@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: linuxarm@huawei.com
Link: https //lore.kernel.org/r/1627566986-30605-3-git-send-email-john.garry@huawei.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>

diff --git a/tools/perf/pmu-events/arch/test/test_cpu/branch.json b/tools/perf/pmu-events/arch/test/test_cpu/branch.json
deleted file mode 100644 (file)
index 93ddfd8..0000000
--- a/tools/perf/pmu-events/arch/test/test_cpu/branch.json
+++ /dev/null
@@ -1,12 +0,0 @@
-[
-  {
-    "EventName": "bp_l1_btb_correct",
-    "EventCode": "0x8a",
-    "BriefDescription": "L1 BTB Correction."
-  },
-  {
-    "EventName": "bp_l2_btb_correct",
-    "EventCode": "0x8b",
-    "BriefDescription": "L2 BTB Correction."
-  }
-]

diff --git a/tools/perf/pmu-events/arch/test/test_cpu/cache.json b/tools/perf/pmu-events/arch/test/test_cpu/cache.json
deleted file mode 100644 (file)
index 036d0ef..0000000
--- a/tools/perf/pmu-events/arch/test/test_cpu/cache.json
+++ /dev/null
@@ -1,5 +0,0 @@
-[
-    {
-        "ArchStdEvent": "L3_CACHE_RD"
-    }
-]
\ No newline at end of file

diff --git a/tools/perf/pmu-events/arch/test/test_cpu/other.json b/tools/perf/pmu-events/arch/test/test_cpu/other.json
deleted file mode 100644 (file)
index 7d53d7e..0000000
--- a/tools/perf/pmu-events/arch/test/test_cpu/other.json
+++ /dev/null
@@ -1,26 +0,0 @@
-[
-    {
-        "EventCode": "0x6",
-        "Counter": "0,1",
-        "UMask": "0x80",
-        "EventName": "SEGMENT_REG_LOADS.ANY",
-        "SampleAfterValue": "200000",
-        "BriefDescription": "Number of segment register loads."
-    },
-    {
-        "EventCode": "0x9",
-        "Counter": "0,1",
-        "UMask": "0x20",
-        "EventName": "DISPATCH_BLOCKED.ANY",
-        "SampleAfterValue": "200000",
-        "BriefDescription": "Memory cluster signals to block micro-op dispatch for any reason"
-    },
-    {
-        "EventCode": "0x3A",
-        "Counter": "0,1",
-        "UMask": "0x0",
-        "EventName": "EIST_TRANS",
-        "SampleAfterValue": "200000",
-        "BriefDescription": "Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions"
-    }
-]
\ No newline at end of file

diff --git a/tools/perf/pmu-events/arch/test/test_cpu/uncore.json b/tools/perf/pmu-events/arch/test/test_cpu/uncore.json
deleted file mode 100644 (file)
index d0a890c..0000000
--- a/tools/perf/pmu-events/arch/test/test_cpu/uncore.json
+++ /dev/null
@@ -1,21 +0,0 @@
-[
- {
-           "EventCode": "0x02",
-           "EventName": "uncore_hisi_ddrc.flux_wcmd",
-           "BriefDescription": "DDRC write commands",
-           "PublicDescription": "DDRC write commands",
-           "Unit": "hisi_sccl,ddrc"
-   },
-   {
-           "Unit": "CBO",
-           "EventCode": "0x22",
-           "UMask": "0x81",
-           "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION",
-           "BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
-           "PublicDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
-           "Counter": "0,1",
-           "CounterMask": "0",
-           "Invert": "0",
-           "EdgeDetect": "0"
-  }
-]

diff --git a/tools/perf/pmu-events/arch/test/test_soc/cpu/branch.json b/tools/perf/pmu-events/arch/test/test_soc/cpu/branch.json
new file mode 100644 (file)
index 0000000..93ddfd8
--- /dev/null
+++ b/tools/perf/pmu-events/arch/test/test_soc/cpu/branch.json
@@ -0,0 +1,12 @@
+[
+  {
+    "EventName": "bp_l1_btb_correct",
+    "EventCode": "0x8a",
+    "BriefDescription": "L1 BTB Correction."
+  },
+  {
+    "EventName": "bp_l2_btb_correct",
+    "EventCode": "0x8b",
+    "BriefDescription": "L2 BTB Correction."
+  }
+]

diff --git a/tools/perf/pmu-events/arch/test/test_soc/cpu/cache.json b/tools/perf/pmu-events/arch/test/test_soc/cpu/cache.json
new file mode 100644 (file)
index 0000000..036d0ef
--- /dev/null
+++ b/tools/perf/pmu-events/arch/test/test_soc/cpu/cache.json
@@ -0,0 +1,5 @@
+[
+    {
+        "ArchStdEvent": "L3_CACHE_RD"
+    }
+]
\ No newline at end of file

diff --git a/tools/perf/pmu-events/arch/test/test_soc/cpu/other.json b/tools/perf/pmu-events/arch/test/test_soc/cpu/other.json
new file mode 100644 (file)
index 0000000..7d53d7e
--- /dev/null
+++ b/tools/perf/pmu-events/arch/test/test_soc/cpu/other.json
@@ -0,0 +1,26 @@
+[
+    {
+        "EventCode": "0x6",
+        "Counter": "0,1",
+        "UMask": "0x80",
+        "EventName": "SEGMENT_REG_LOADS.ANY",
+        "SampleAfterValue": "200000",
+        "BriefDescription": "Number of segment register loads."
+    },
+    {
+        "EventCode": "0x9",
+        "Counter": "0,1",
+        "UMask": "0x20",
+        "EventName": "DISPATCH_BLOCKED.ANY",
+        "SampleAfterValue": "200000",
+        "BriefDescription": "Memory cluster signals to block micro-op dispatch for any reason"
+    },
+    {
+        "EventCode": "0x3A",
+        "Counter": "0,1",
+        "UMask": "0x0",
+        "EventName": "EIST_TRANS",
+        "SampleAfterValue": "200000",
+        "BriefDescription": "Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions"
+    }
+]
\ No newline at end of file

diff --git a/tools/perf/pmu-events/arch/test/test_soc/cpu/uncore.json b/tools/perf/pmu-events/arch/test/test_soc/cpu/uncore.json
new file mode 100644 (file)
index 0000000..d0a890c
--- /dev/null
+++ b/tools/perf/pmu-events/arch/test/test_soc/cpu/uncore.json
@@ -0,0 +1,21 @@
+[
+ {
+           "EventCode": "0x02",
+           "EventName": "uncore_hisi_ddrc.flux_wcmd",
+           "BriefDescription": "DDRC write commands",
+           "PublicDescription": "DDRC write commands",
+           "Unit": "hisi_sccl,ddrc"
+   },
+   {
+           "Unit": "CBO",
+           "EventCode": "0x22",
+           "UMask": "0x81",
+           "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION",
+           "BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
+           "PublicDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
+           "Counter": "0,1",
+           "CounterMask": "0",
+           "Invert": "0",
+           "EdgeDetect": "0"
+  }
+]

diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c
index 9604446f8360be061a5e5c911c9c29fad6e224c6..405bdd36b9b9f42d3198c4226da03b9bccc626f0 100644 (file)
--- a/tools/perf/pmu-events/jevents.c
+++ b/tools/perf/pmu-events/jevents.c
@@ -814,7 +814,7 @@ static void print_mapping_test_table(FILE *outfp)
        fprintf(outfp, "\t.cpuid = \"testcpu\",\n");
        fprintf(outfp, "\t.version = \"v1\",\n");
        fprintf(outfp, "\t.type = \"core\",\n");
-       fprintf(outfp, "\t.table = pme_test_cpu,\n");
+       fprintf(outfp, "\t.table = pme_test_soc_cpu,\n");
        fprintf(outfp, "},\n");
 }