arm64: dts: renesas: rzg2l-smarc-som: Enable Ethernet

Enable Ethernet{0,1} interfaces on RZ/G2L SMARC EVK.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20211013075647.32231-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
index fbf51043d6ccefeeabdc9b6af17cd6a22d6c6859..7e84a29dddfaa6eb9c256daf8b0abece1a9f23fe 100644 (file)
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
@@ -19,6 +19,15 @@
 #define SDHI   (!EMMC)
 
 / {
+       aliases {
+               ethernet0 = &eth0;
+               ethernet1 = &eth1;
+       };
+
+       chosen {
+               bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
+       };
+
        memory@48000000 {
                device_type = "memory";
                /* first 128MB is reserved for secure area. */
@@ -65,6 +74,58 @@
        /delete-node/ channel@7;
 };
 
+&eth0 {
+       pinctrl-0 = <&eth0_pins>;
+       pinctrl-names = "default";
+       phy-handle = <&phy0>;
+       phy-mode = "rgmii-id";
+       status = "okay";
+
+       phy0: ethernet-phy@7 {
+               compatible = "ethernet-phy-id0022.1640",
+                            "ethernet-phy-ieee802.3-c22";
+               reg = <7>;
+               rxc-skew-psec = <2400>;
+               txc-skew-psec = <2400>;
+               rxdv-skew-psec = <0>;
+               txdv-skew-psec = <0>;
+               rxd0-skew-psec = <0>;
+               rxd1-skew-psec = <0>;
+               rxd2-skew-psec = <0>;
+               rxd3-skew-psec = <0>;
+               txd0-skew-psec = <0>;
+               txd1-skew-psec = <0>;
+               txd2-skew-psec = <0>;
+               txd3-skew-psec = <0>;
+       };
+};
+
+&eth1 {
+       pinctrl-0 = <&eth1_pins>;
+       pinctrl-names = "default";
+       phy-handle = <&phy1>;
+       phy-mode = "rgmii-id";
+       status = "okay";
+
+       phy1: ethernet-phy@7 {
+               compatible = "ethernet-phy-id0022.1640",
+                            "ethernet-phy-ieee802.3-c22";
+               reg = <7>;
+               rxc-skew-psec = <2400>;
+               txc-skew-psec = <2400>;
+               rxdv-skew-psec = <0>;
+               txdv-skew-psec = <0>;
+               rxd0-skew-psec = <0>;
+               rxd1-skew-psec = <0>;
+               rxd2-skew-psec = <0>;
+               rxd3-skew-psec = <0>;
+               txd0-skew-psec = <0>;
+               txd1-skew-psec = <0>;
+               txd2-skew-psec = <0>;
+               txd3-skew-psec = <0>;
+       };
+};
+
 &extal_clk {
        clock-frequency = <24000000>;
 };
@@ -74,6 +135,42 @@
                pinmux = <RZG2L_PORT_PINMUX(9, 0, 2)>; /* ADC_TRG */
        };
 
+       eth0_pins: eth0 {
+               pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
+                        <RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
+                        <RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
+                        <RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */
+                        <RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
+                        <RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
+                        <RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
+                        <RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
+                        <RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
+                        <RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
+                        <RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
+                        <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
+                        <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
+                        <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
+                        <RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */
+       };
+
+       eth1_pins: eth1 {
+               pinmux = <RZG2L_PORT_PINMUX(37, 2, 1)>, /* ET1_LINKSTA */
+                        <RZG2L_PORT_PINMUX(37, 0, 1)>, /* ET1_MDC */
+                        <RZG2L_PORT_PINMUX(37, 1, 1)>, /* ET1_MDIO */
+                        <RZG2L_PORT_PINMUX(29, 0, 1)>, /* ET1_TXC */
+                        <RZG2L_PORT_PINMUX(29, 1, 1)>, /* ET1_TX_CTL */
+                        <RZG2L_PORT_PINMUX(30, 0, 1)>, /* ET1_TXD0 */
+                        <RZG2L_PORT_PINMUX(30, 1, 1)>, /* ET1_TXD1 */
+                        <RZG2L_PORT_PINMUX(31, 0, 1)>, /* ET1_TXD2 */
+                        <RZG2L_PORT_PINMUX(31, 1, 1)>, /* ET1_TXD3 */
+                        <RZG2L_PORT_PINMUX(33, 1, 1)>, /* ET1_RXC */
+                        <RZG2L_PORT_PINMUX(34, 0, 1)>, /* ET1_RX_CTL */
+                        <RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */
+                        <RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */
+                        <RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */
+                        <RZG2L_PORT_PINMUX(36, 0, 1)>; /* ET1_RXD3 */
+       };
+
        gpio-sd0-pwr-en-hog {
                gpio-hog;
                gpios = <RZG2L_GPIO(4, 1) GPIO_ACTIVE_HIGH>;

diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
index d8b3d32dc6f516a894238b939dd2568a5812c8e4..2863e487a64023756750ae353942ae93293e7c12 100644 (file)
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
@@ -30,7 +30,6 @@
        };
 
        chosen {
-               bootargs = "ignore_loglevel";
                stdout-path = "serial0:115200n8";
        };