ASoC: Intel: avs: ICCMAX recommendations for ICL+ platforms
authorCezary Rojewski <cezary.rojewski@intel.com>
Tue, 20 Feb 2024 11:50:34 +0000 (12:50 +0100)
committerMark Brown <broonie@kernel.org>
Tue, 20 Feb 2024 13:20:00 +0000 (13:20 +0000)
For ICL+ platforms to avoid DMI/OPIO L1 entry during the base firmware
load procedure, HW recommends to set LTRP_GB to 95us and start an
additional CAPTURE stream in the background.

Once the load completes, original LTRP_GB value is restored and the
additional stream is released.

Reviewed-by: Amadeusz Sławiński <amadeuszx.slawinski@linux.intel.com>
Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Link: https://msgid.link/r/20240220115035.770402-10-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
include/sound/hda_register.h
sound/soc/intel/avs/avs.h
sound/soc/intel/avs/icl.c
sound/soc/intel/avs/tgl.c

index 55958711d6974e87ed08155fef3b47da6d53ba7f..5ff31e6d41c190fac204c5140ba98c501a382e92 100644 (file)
@@ -131,6 +131,8 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 #define AZX_REG_VS_SDXEFIFOS_XBASE     0x1094
 #define AZX_REG_VS_SDXEFIFOS_XINTERVAL 0x20
 
+#define AZX_REG_VS_LTRP_GB_MASK                GENMASK(6, 0)
+
 /* PCI space */
 #define AZX_PCIREG_TCSEL               0x44
 
index 703bb1f145fa457cee68780915e6d54b292f813c..a58c1500f6124769122b3ffa1df8c6e77cb79a99 100644 (file)
@@ -325,6 +325,8 @@ int avs_hda_load_library(struct avs_dev *adev, struct firmware *lib, u32 id);
 int avs_hda_transfer_modules(struct avs_dev *adev, bool load,
                             struct avs_module_entry *mods, u32 num_mods);
 
+int avs_icl_load_basefw(struct avs_dev *adev, struct firmware *fw);
+
 /* Soc component members */
 
 struct avs_soc_component {
index 83ebee6f87ac1dd5e4ec0acdffa4dc2e1a5aeaab..9d9921e1cd4dedcb2ff4f8e9b59a3b4560d7fa4c 100644 (file)
@@ -7,9 +7,13 @@
 //
 
 #include <linux/slab.h>
+#include <sound/hdaudio.h>
+#include <sound/hdaudio_ext.h>
 #include "avs.h"
 #include "messages.h"
 
+#define ICL_VS_LTRP_GB_ICCMAX  95
+
 #ifdef CONFIG_DEBUG_FS
 int avs_icl_enable_logs(struct avs_dev *adev, enum avs_log_enable enable, u32 aging_period,
                        u32 fifo_full_period, unsigned long resource_mask, u32 *priorities)
@@ -118,6 +122,62 @@ int avs_icl_set_d0ix(struct avs_dev *adev, bool enable)
        return AVS_IPC_RET(ret);
 }
 
+int avs_icl_load_basefw(struct avs_dev *adev, struct firmware *fw)
+{
+       struct hdac_bus *bus = &adev->base.core;
+       struct hdac_ext_stream *host_stream;
+       struct snd_pcm_substream substream;
+       struct snd_dma_buffer dmab;
+       unsigned int sd_fmt;
+       u8 ltrp_gb;
+       int ret;
+
+       /*
+        * ICCMAX:
+        *
+        * For ICL+ platforms, as per HW recommendation LTRP_GB is set to 95us
+        * during FW load. Its original value shall be restored once load completes.
+        *
+        * To avoid DMI/OPIO L1 entry during the load procedure, additional CAPTURE
+        * stream is allocated and set to run.
+        */
+
+       memset(&substream, 0, sizeof(substream));
+       substream.stream = SNDRV_PCM_STREAM_CAPTURE;
+
+       host_stream = snd_hdac_ext_stream_assign(bus, &substream, HDAC_EXT_STREAM_TYPE_HOST);
+       if (!host_stream)
+               return -EBUSY;
+
+       ltrp_gb = snd_hdac_chip_readb(bus, VS_LTRP) & AZX_REG_VS_LTRP_GB_MASK;
+       /* Carries no real data, use default format. */
+       sd_fmt = snd_hdac_stream_format(1, 32, 48000);
+
+       ret = snd_hdac_dsp_prepare(hdac_stream(host_stream), sd_fmt, fw->size, &dmab);
+       if (ret < 0)
+               goto release_stream;
+
+       snd_hdac_chip_updateb(bus, VS_LTRP, AZX_REG_VS_LTRP_GB_MASK, ICL_VS_LTRP_GB_ICCMAX);
+
+       spin_lock(&bus->reg_lock);
+       snd_hdac_stream_start(hdac_stream(host_stream));
+       spin_unlock(&bus->reg_lock);
+
+       ret = avs_hda_load_basefw(adev, fw);
+
+       spin_lock(&bus->reg_lock);
+       snd_hdac_stream_stop(hdac_stream(host_stream));
+       spin_unlock(&bus->reg_lock);
+
+       snd_hdac_dsp_cleanup(hdac_stream(host_stream), &dmab);
+
+release_stream:
+       snd_hdac_ext_stream_release(host_stream, HDAC_EXT_STREAM_TYPE_HOST);
+       snd_hdac_chip_updateb(bus, VS_LTRP, AZX_REG_VS_LTRP_GB_MASK, ltrp_gb);
+
+       return ret;
+}
+
 const struct avs_dsp_ops avs_icl_dsp_ops = {
        .power = avs_dsp_core_power,
        .reset = avs_dsp_core_reset,
@@ -125,7 +185,7 @@ const struct avs_dsp_ops avs_icl_dsp_ops = {
        .irq_handler = avs_irq_handler,
        .irq_thread = avs_cnl_irq_thread,
        .int_control = avs_dsp_interrupt_control,
-       .load_basefw = avs_hda_load_basefw,
+       .load_basefw = avs_icl_load_basefw,
        .load_lib = avs_hda_load_library,
        .transfer_mods = avs_hda_transfer_modules,
        .log_buffer_offset = avs_icl_log_buffer_offset,
index 8abdff4fbb870382f9bb07d8bf4d2a0e29822312..0e052e7f6bac46f55ed393af53282eca1e31bd4a 100644 (file)
@@ -42,7 +42,7 @@ const struct avs_dsp_ops avs_tgl_dsp_ops = {
        .irq_handler = avs_irq_handler,
        .irq_thread = avs_cnl_irq_thread,
        .int_control = avs_dsp_interrupt_control,
-       .load_basefw = avs_hda_load_basefw,
+       .load_basefw = avs_icl_load_basefw,
        .load_lib = avs_hda_load_library,
        .transfer_mods = avs_hda_transfer_modules,
        .log_buffer_offset = avs_icl_log_buffer_offset,