drm/i915: pass dev_priv explicitly to PIPE_WGC_C12

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_WGC_C12 register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/62a748b685f253151b17c101dec75351577f30c0.1714399071.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 11b5891a8399aceb15937f3ba1c41f879760f206..a4935289729dc2ebe659873d0d8bae624e59bbde 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -623,7 +623,7 @@ static void vlv_load_wgc_csc(struct intel_crtc *crtc,
 
        intel_de_write_fw(dev_priv, PIPE_WGC_C11_C10(dev_priv, pipe),
                          csc->coeff[4] << 16 | csc->coeff[3]);
-       intel_de_write_fw(dev_priv, PIPE_WGC_C12(pipe),
+       intel_de_write_fw(dev_priv, PIPE_WGC_C12(dev_priv, pipe),
                          csc->coeff[5]);
 
        intel_de_write_fw(dev_priv, PIPE_WGC_C21_C20(pipe),
@@ -650,7 +650,7 @@ static void vlv_read_wgc_csc(struct intel_crtc *crtc,
        csc->coeff[3] = tmp & 0xffff;
        csc->coeff[4] = tmp >> 16;
 
-       tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C12(pipe));
+       tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C12(dev_priv, pipe));
        csc->coeff[5] = tmp & 0xffff;
 
        tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C21_C20(pipe));

diff --git a/drivers/gpu/drm/i915/display/intel_color_regs.h b/drivers/gpu/drm/i915/display/intel_color_regs.h
index 19b0255e08314fa117276a87ebe0522fac7c8c56..2dc876e10eda29d2a791d17191aa1f46e4463718 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_color_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_color_regs.h
@@ -259,7 +259,7 @@
 #define PIPE_WGC_C01_C00(dev_priv, pipe)               _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C01_C00)
 #define PIPE_WGC_C02(dev_priv, pipe)           _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C02)
 #define PIPE_WGC_C11_C10(dev_priv, pipe)               _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C11_C10)
-#define PIPE_WGC_C12(pipe)             _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C12)
+#define PIPE_WGC_C12(dev_priv, pipe)           _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C12)
 #define PIPE_WGC_C21_C20(pipe)         _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C21_C20)
 #define PIPE_WGC_C22(pipe)             _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C22)