arm64: dts: qcom: sc7280: switch USB+DP QMP PHY to new style of bindings

Change the USB QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes).

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230711120916.4165894-8-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 2108c6c0797eae969d18f2d124d2b2b209b4ffe3..640d412f9882edbe377e39f7419cda86c6e8bf38 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -18,6 +18,7 @@
 #include <dt-bindings/interconnect/qcom,sc7280.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/mailbox/qcom-ipcc.h>
+#include <dt-bindings/phy/phy-qcom-qmp.h>
 #include <dt-bindings/power/qcom-rpmpd.h>
 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
@@ -917,7 +918,7 @@
                                 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
                                 <0>, <&pcie1_lane>,
                                 <0>, <0>, <0>,
-                                <&usb_1_ssphy>;
+                                <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
                        clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
                                      "pcie_0_pipe_clk", "pcie_1_pipe_clk",
                                      "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk",
@@ -3394,49 +3395,26 @@
                        resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
                };
 
-               usb_1_qmpphy: phy-wrapper@88e9000 {
-                       compatible = "qcom,sc7280-qmp-usb3-dp-phy",
-                                    "qcom,sm8250-qmp-usb3-dp-phy";
-                       reg = <0 0x088e9000 0 0x200>,
-                             <0 0x088e8000 0 0x40>,
-                             <0 0x088ea000 0 0x200>;
+               usb_1_qmpphy: phy@88e8000 {
+                       compatible = "qcom,sc7280-qmp-usb3-dp-phy";
+                       reg = <0 0x088e8000 0 0x3000>;
                        status = "disabled";
-                       #address-cells = <2>;
-                       #size-cells = <2>;
-                       ranges;
 
                        clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
                                 <&rpmhcc RPMH_CXO_CLK>,
-                                <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
-                       clock-names = "aux", "ref_clk_src", "com_aux";
+                                <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+                                <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+                       clock-names = "aux",
+                                     "ref",
+                                     "com_aux",
+                                     "usb3_pipe";
 
                        resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
                                 <&gcc GCC_USB3_PHY_PRIM_BCR>;
                        reset-names = "phy", "common";
 
-                       usb_1_ssphy: usb3-phy@88e9200 {
-                               reg = <0 0x088e9200 0 0x200>,
-                                     <0 0x088e9400 0 0x200>,
-                                     <0 0x088e9c00 0 0x400>,
-                                     <0 0x088e9600 0 0x200>,
-                                     <0 0x088e9800 0 0x200>,
-                                     <0 0x088e9a00 0 0x100>;
-                               #clock-cells = <0>;
-                               #phy-cells = <0>;
-                               clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
-                               clock-names = "pipe0";
-                               clock-output-names = "usb3_phy_pipe_clk_src";
-                       };
-
-                       dp_phy: dp-phy@88ea200 {
-                               reg = <0 0x088ea200 0 0x200>,
-                                     <0 0x088ea400 0 0x200>,
-                                     <0 0x088eaa00 0 0x200>,
-                                     <0 0x088ea600 0 0x200>,
-                                     <0 0x088ea800 0 0x200>;
-                               #phy-cells = <0>;
-                               #clock-cells = <1>;
-                       };
+                       #clock-cells = <1>;
+                       #phy-cells = <1>;
                };
 
                usb_2: usb@8cf8800 {
@@ -3750,7 +3728,7 @@
                                iommus = <&apps_smmu 0xe0 0x0>;
                                snps,dis_u2_susphy_quirk;
                                snps,dis_enblslpm_quirk;
-                               phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
+                               phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
                                phy-names = "usb2-phy", "usb3-phy";
                                maximum-speed = "super-speed";
                        };
@@ -3855,8 +3833,8 @@
                                 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
                                 <&mdss_dsi_phy 0>,
                                 <&mdss_dsi_phy 1>,
-                                <&dp_phy 0>,
-                                <&dp_phy 1>,
+                                <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+                                <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
                                 <&mdss_edp_phy 0>,
                                 <&mdss_edp_phy 1>;
                        clock-names = "bi_tcxo",
@@ -4192,8 +4170,9 @@
                                                "stream_pixel";
                                assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
                                                  <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
-                               assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
-                               phys = <&dp_phy>;
+                               assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+                                                        <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
+                               phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
                                phy-names = "dp";
 
                                operating-points-v2 = <&dp_opp_table>;