net: ethernet: ti: am65-cpsw: Add support for J7200 CPSW5G

CPSW5G in J7200 supports additional modes like QSGMII and SGMII.
Add new compatible for J7200 and enable QSGMII mode in am65-cpsw driver.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c
index f4a6b590a1e3995a6eb51ba2c8d0c27b9b9af641..033b40649308a46cdf8bcdf94e1c7538aea22c2c 100644 (file)
--- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c
+++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c
@@ -74,6 +74,9 @@
 #define AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG  0x318
 #define AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2       0x31C
 
+#define AM65_CPSW_SGMII_CONTROL_REG            0x010
+#define AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE   BIT(0)
+
 #define AM65_CPSW_CTL_VLAN_AWARE               BIT(1)
 #define AM65_CPSW_CTL_P0_ENABLE                        BIT(2)
 #define AM65_CPSW_CTL_P0_TX_CRC_REMOVE         BIT(13)
@@ -1409,7 +1412,14 @@ static const struct net_device_ops am65_cpsw_nuss_netdev_ops = {
 static void am65_cpsw_nuss_mac_config(struct phylink_config *config, unsigned int mode,
                                      const struct phylink_link_state *state)
 {
-       /* Currently not used */
+       struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data,
+                                                         phylink_config);
+       struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave);
+       struct am65_cpsw_common *common = port->common;
+
+       if (common->pdata.extra_modes & BIT(state->interface))
+               writel(AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE,
+                      port->sgmii_base + AM65_CPSW_SGMII_CONTROL_REG);
 }
 
 static void am65_cpsw_nuss_mac_link_down(struct phylink_config *config, unsigned int mode,
@@ -1847,6 +1857,8 @@ static int am65_cpsw_nuss_init_slave_ports(struct am65_cpsw_common *common)
                port->common = common;
                port->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE +
                                  AM65_CPSW_NU_PORTS_OFFSET * (port_id);
+               if (common->pdata.extra_modes)
+                       port->sgmii_base = common->ss_base + AM65_CPSW_SGMII_BASE * (port_id);
                port->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE +
                                  (AM65_CPSW_NU_STATS_PORT_OFFSET * port_id);
                port->name = of_get_property(port_np, "label", NULL);
@@ -1981,7 +1993,18 @@ am65_cpsw_nuss_init_port_ndev(struct am65_cpsw_common *common, u32 port_idx)
        port->slave.phylink_config.type = PHYLINK_NETDEV;
        port->slave.phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000FD;
 
-       phy_interface_set_rgmii(port->slave.phylink_config.supported_interfaces);
+       if (phy_interface_mode_is_rgmii(port->slave.phy_if)) {
+               phy_interface_set_rgmii(port->slave.phylink_config.supported_interfaces);
+       } else if (port->slave.phy_if == PHY_INTERFACE_MODE_RMII) {
+               __set_bit(PHY_INTERFACE_MODE_RMII,
+                         port->slave.phylink_config.supported_interfaces);
+       } else if (common->pdata.extra_modes & BIT(port->slave.phy_if)) {
+               __set_bit(PHY_INTERFACE_MODE_QSGMII,
+                         port->slave.phylink_config.supported_interfaces);
+       } else {
+               dev_err(dev, "selected phy-mode is not supported\n");
+               return -EOPNOTSUPP;
+       }
 
        phylink = phylink_create(&port->slave.phylink_config,
                                 of_node_to_fwnode(port->slave.phy_node),
@@ -2611,10 +2634,18 @@ static const struct am65_cpsw_pdata am64x_cpswxg_pdata = {
        .fdqring_mode = K3_RINGACC_RING_MODE_RING,
 };
 
+static const struct am65_cpsw_pdata j7200_cpswxg_pdata = {
+       .quirks = 0,
+       .ale_dev_id = "am64-cpswxg",
+       .fdqring_mode = K3_RINGACC_RING_MODE_RING,
+       .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII),
+};
+
 static const struct of_device_id am65_cpsw_nuss_of_mtable[] = {
        { .compatible = "ti,am654-cpsw-nuss", .data = &am65x_sr1_0},
        { .compatible = "ti,j721e-cpsw-nuss", .data = &j721e_pdata},
        { .compatible = "ti,am642-cpsw-nuss", .data = &am64x_cpswxg_pdata},
+       { .compatible = "ti,j7200-cpswxg-nuss", .data = &j7200_cpswxg_pdata},
        { /* sentinel */ },
 };
 MODULE_DEVICE_TABLE(of, am65_cpsw_nuss_of_mtable);

diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.h b/drivers/net/ethernet/ti/am65-cpsw-nuss.h
index ac945631bf2fdc8b43256df7e0b1ebe556279f90..2c9850fdfcb6dc7489fb072038b9574bf66ce417 100644 (file)
--- a/drivers/net/ethernet/ti/am65-cpsw-nuss.h
+++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.h
@@ -46,6 +46,7 @@ struct am65_cpsw_port {
        const char                      *name;
        u32                             port_id;
        void __iomem                    *port_base;
+       void __iomem                    *sgmii_base;
        void __iomem                    *stat_base;
        void __iomem                    *fetch_ram_base;
        bool                            disabled;
@@ -88,6 +89,7 @@ struct am65_cpsw_rx_chn {
 
 struct am65_cpsw_pdata {
        u32     quirks;
+       u64     extra_modes;
        enum k3_ring_mode fdqring_mode;
        const char      *ale_dev_id;
 };