drm/amdgpu: use ring structure to access rptr/wptr v2

Use ring structure to access the cpu/gpu address of rptr/wptr.

v2: merge gfx10/sdma5/sdma5.2 patches

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index 6c01199e911283f2e1d7958fc384e383deb72454..5647f13b98d49c814bdd34f3a67a8b00e118394c 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -164,7 +164,7 @@ static uint64_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring)
 {
        u32 rptr;
 
-       rptr = ring->adev->wb.wb[ring->rptr_offs];
+       rptr = *ring->rptr_cpu_addr;
 
        return (rptr & 0x3fffc) >> 2;
 }
@@ -436,12 +436,10 @@ static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
        struct amdgpu_ring *ring;
        u32 rb_cntl, ib_cntl;
        u32 rb_bufsz;
-       u32 wb_offset;
        int i, j, r;
 
        for (i = 0; i < adev->sdma.num_instances; i++) {
                ring = &adev->sdma.instance[i].ring;
-               wb_offset = (ring->rptr_offs * 4);
 
                mutex_lock(&adev->srbm_mutex);
                for (j = 0; j < 16; j++) {
@@ -477,9 +475,9 @@ static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
 
                /* set the wb address whether it's enabled or not */
                WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
-                      upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
+                      upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
                WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
-                      ((adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC));
+                      ((ring->rptr_gpu_addr) & 0xFFFFFFFC));
 
                rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK;
 

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 407074f958f477daa55610367d48694aa35822b5..f2dd53f2af6148ec386594a7052fd36a4199285a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3519,9 +3519,8 @@ static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue
 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
                                 struct amdgpu_ring *ring)
 {
-       struct amdgpu_device *adev = kiq_ring->adev;
        uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
-       uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
+       uint64_t wptr_addr = ring->wptr_gpu_addr;
        uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
 
        amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
@@ -6344,12 +6343,12 @@ static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
        WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
 
        /* set the wb address wether it's enabled or not */
-       rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
+       rptr_addr = ring->rptr_gpu_addr;
        WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
        WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
                     CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
 
-       wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
+       wptr_gpu_addr = ring->wptr_gpu_addr;
        WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
                     lower_32_bits(wptr_gpu_addr));
        WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
@@ -6382,11 +6381,11 @@ static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
                WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
                WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
                /* Set the wb address wether it's enabled or not */
-               rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
+               rptr_addr = ring->rptr_gpu_addr;
                WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
                WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
                             CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
-               wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
+               wptr_gpu_addr = ring->wptr_gpu_addr;
                WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
                             lower_32_bits(wptr_gpu_addr));
                WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
@@ -6610,13 +6609,13 @@ static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring)
        mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
 
        /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
-       wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
+       wb_gpu_addr = ring->rptr_gpu_addr;
        mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
        mqd->cp_gfx_hqd_rptr_addr_hi =
                upper_32_bits(wb_gpu_addr) & 0xffff;
 
        /* set up rb_wptr_poll addr */
-       wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
+       wb_gpu_addr = ring->wptr_gpu_addr;
        mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
        mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
 
@@ -6730,7 +6729,7 @@ static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
                        memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
                /* reset the ring */
                ring->wptr = 0;
-               adev->wb.wb[ring->wptr_offs] = 0;
+               *ring->wptr_cpu_addr = 0;
                amdgpu_ring_clear_ring(ring);
 #ifdef BRING_UP_DEBUG
                mutex_lock(&adev->srbm_mutex);
@@ -6904,13 +6903,13 @@ static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
        mqd->cp_hqd_pq_control = tmp;
 
        /* set the wb address whether it's enabled or not */
-       wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
+       wb_gpu_addr = ring->rptr_gpu_addr;
        mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
        mqd->cp_hqd_pq_rptr_report_addr_hi =
                upper_32_bits(wb_gpu_addr) & 0xffff;
 
        /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
-       wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
+       wb_gpu_addr = ring->wptr_gpu_addr;
        mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
        mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
 
@@ -7130,7 +7129,7 @@ static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
 
                /* reset ring buffer */
                ring->wptr = 0;
-               atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0);
+               atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
                amdgpu_ring_clear_ring(ring);
        } else {
                amdgpu_ring_clear_ring(ring);
@@ -8496,7 +8495,8 @@ static void gfx_v10_0_get_clockgating_state(void *handle, u64 *flags)
 
 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
 {
-       return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/
+       /* gfx10 is 32bit rptr*/
+       return *(uint32_t *)ring->rptr_cpu_addr;
 }
 
 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
@@ -8506,7 +8506,7 @@ static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
 
        /* XXX check if swapping is necessary on BE */
        if (ring->use_doorbell) {
-               wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
+               wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
        } else {
                wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
                wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
@@ -8521,7 +8521,7 @@ static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
 
        if (ring->use_doorbell) {
                /* XXX check if swapping is necessary on BE */
-               atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
+               atomic64_set((atomic64_t *)ring->wptr_cpu_addr, ring->wptr);
                WDOORBELL64(ring->doorbell_index, ring->wptr);
        } else {
                WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
@@ -8531,7 +8531,8 @@ static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
 
 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
 {
-       return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */
+       /* gfx10 hardware is 32bit rptr */
+       return *(uint32_t *)ring->rptr_cpu_addr;
 }
 
 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
@@ -8540,7 +8541,7 @@ static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
 
        /* XXX check if swapping is necessary on BE */
        if (ring->use_doorbell)
-               wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
+               wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
        else
                BUG();
        return wptr;
@@ -8552,7 +8553,7 @@ static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
 
        /* XXX check if swapping is necessary on BE */
        if (ring->use_doorbell) {
-               atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
+               atomic64_set((atomic64_t *)ring->wptr_cpu_addr, ring->wptr);
                WDOORBELL64(ring->doorbell_index, ring->wptr);
        } else {
                BUG(); /* only DOORBELL method supported on gfx10 now */

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index 6a8dadea40f92c43dddca4b3aa2f1f28e37feec5..29a91b320d4fe3a482a31e56add686aceb2aa475 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -2117,7 +2117,7 @@ static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev)
        WREG32(mmCP_RB0_WPTR, ring->wptr);
 
        /* set the wb address whether it's enabled or not */
-       rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
+       rptr_addr = ring->rptr_gpu_addr;
        WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
        WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
 
@@ -2139,7 +2139,7 @@ static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev)
 
 static u64 gfx_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
 {
-       return ring->adev->wb.wb[ring->rptr_offs];
+       return *ring->rptr_cpu_addr;
 }
 
 static u64 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
@@ -2203,7 +2203,7 @@ static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev)
        ring->wptr = 0;
        WREG32(mmCP_RB1_WPTR, ring->wptr);
 
-       rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
+       rptr_addr = ring->rptr_gpu_addr;
        WREG32(mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
        WREG32(mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
 
@@ -2222,7 +2222,7 @@ static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev)
        WREG32(mmCP_RB2_CNTL, tmp | CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK);
        ring->wptr = 0;
        WREG32(mmCP_RB2_WPTR, ring->wptr);
-       rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
+       rptr_addr = ring->rptr_gpu_addr;
        WREG32(mmCP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr));
        WREG32(mmCP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
 

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index d17a6f39934703f5060f38286578837a30930048..ac3f2dbba7260f90cc98a3132e3c4770a62a5190 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -2630,8 +2630,8 @@ static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev)
        ring->wptr = 0;
        WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
 
-       /* set the wb address whether it's enabled or not */
-       rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
+       /* set the wb address wether it's enabled or not */
+       rptr_addr = ring->rptr_gpu_addr;
        WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
        WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
 
@@ -2656,7 +2656,7 @@ static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev)
 
 static u64 gfx_v7_0_ring_get_rptr(struct amdgpu_ring *ring)
 {
-       return ring->adev->wb.wb[ring->rptr_offs];
+       return *ring->rptr_cpu_addr;
 }
 
 static u64 gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
@@ -2677,7 +2677,7 @@ static void gfx_v7_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
 static u64 gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
 {
        /* XXX check if swapping is necessary on BE */
-       return ring->adev->wb.wb[ring->wptr_offs];
+       return *ring->wptr_cpu_addr;
 }
 
 static void gfx_v7_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
@@ -2685,7 +2685,7 @@ static void gfx_v7_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
        struct amdgpu_device *adev = ring->adev;
 
        /* XXX check if swapping is necessary on BE */
-       adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
+       *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
        WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
 }
 
@@ -2981,12 +2981,12 @@ static void gfx_v7_0_mqd_init(struct amdgpu_device *adev,
                CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK; /* assuming kernel queue control */
 
        /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
-       wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
+       wb_gpu_addr = ring->wptr_gpu_addr;
        mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
        mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
 
-       /* set the wb address whether it's enabled or not */
-       wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
+       /* set the wb address wether it's enabled or not */
+       wb_gpu_addr = ring->rptr_gpu_addr;
        mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
        mqd->cp_hqd_pq_rptr_report_addr_hi =
                upper_32_bits(wb_gpu_addr) & 0xffff;

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 25dc729d0ec2dc5009ca3f44b0c50d7b11dca22c..e4e779a19c2035af8490c8ca57e863ec67531bc8 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4306,11 +4306,11 @@ static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
        WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
 
        /* set the wb address wether it's enabled or not */
-       rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
+       rptr_addr = ring->rptr_gpu_addr;
        WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
        WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
 
-       wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
+       wptr_gpu_addr = ring->wptr_gpu_addr;
        WREG32(mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));
        WREG32(mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));
        mdelay(1);
@@ -4393,7 +4393,7 @@ static int gfx_v8_0_kiq_kcq_enable(struct amdgpu_device *adev)
        for (i = 0; i < adev->gfx.num_compute_rings; i++) {
                struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
                uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
-               uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
+               uint64_t wptr_addr = ring->wptr_gpu_addr;
 
                /* map queues */
                amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
@@ -4517,13 +4517,13 @@ static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring)
        mqd->cp_hqd_pq_control = tmp;
 
        /* set the wb address whether it's enabled or not */
-       wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
+       wb_gpu_addr = ring->rptr_gpu_addr;
        mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
        mqd->cp_hqd_pq_rptr_report_addr_hi =
                upper_32_bits(wb_gpu_addr) & 0xffff;
 
        /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
-       wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
+       wb_gpu_addr = ring->wptr_gpu_addr;
        mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
        mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
 
@@ -6051,7 +6051,7 @@ static int gfx_v8_0_set_clockgating_state(void *handle,
 
 static u64 gfx_v8_0_ring_get_rptr(struct amdgpu_ring *ring)
 {
-       return ring->adev->wb.wb[ring->rptr_offs];
+       return *ring->rptr_cpu_addr;
 }
 
 static u64 gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
@@ -6060,7 +6060,7 @@ static u64 gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
 
        if (ring->use_doorbell)
                /* XXX check if swapping is necessary on BE */
-               return ring->adev->wb.wb[ring->wptr_offs];
+               return *ring->wptr_cpu_addr;
        else
                return RREG32(mmCP_RB0_WPTR);
 }
@@ -6071,7 +6071,7 @@ static void gfx_v8_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
 
        if (ring->use_doorbell) {
                /* XXX check if swapping is necessary on BE */
-               adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
+               *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
                WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
        } else {
                WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
@@ -6271,7 +6271,7 @@ static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
 
 static u64 gfx_v8_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
 {
-       return ring->adev->wb.wb[ring->wptr_offs];
+       return *ring->wptr_cpu_addr;
 }
 
 static void gfx_v8_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
@@ -6279,7 +6279,7 @@ static void gfx_v8_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
        struct amdgpu_device *adev = ring->adev;
 
        /* XXX check if swapping is necessary on BE */
-       adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
+       *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
        WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
 }
 

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index d58fd83524ac70d1c481fa26f9d3e80242a3f4ef..06182b7e43510f958364bf96ab25e75442435811 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -780,9 +780,8 @@ static void gfx_v9_0_kiq_set_resources(struct amdgpu_ring *kiq_ring,
 static void gfx_v9_0_kiq_map_queues(struct amdgpu_ring *kiq_ring,
                                 struct amdgpu_ring *ring)
 {
-       struct amdgpu_device *adev = kiq_ring->adev;
        uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
-       uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
+       uint64_t wptr_addr = ring->wptr_gpu_addr;
        uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
 
        amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
@@ -3326,11 +3325,11 @@ static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
        WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
 
        /* set the wb address wether it's enabled or not */
-       rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
+       rptr_addr = ring->rptr_gpu_addr;
        WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
        WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
 
-       wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
+       wptr_gpu_addr = ring->wptr_gpu_addr;
        WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));
        WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));
 
@@ -3542,13 +3541,13 @@ static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
        mqd->cp_hqd_pq_control = tmp;
 
        /* set the wb address whether it's enabled or not */
-       wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
+       wb_gpu_addr = ring->rptr_gpu_addr;
        mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
        mqd->cp_hqd_pq_rptr_report_addr_hi =
                upper_32_bits(wb_gpu_addr) & 0xffff;
 
        /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
-       wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
+       wb_gpu_addr = ring->wptr_gpu_addr;
        mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
        mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
 
@@ -3830,7 +3829,7 @@ static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)
 
                /* reset ring buffer */
                ring->wptr = 0;
-               atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0);
+               atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
                amdgpu_ring_clear_ring(ring);
        } else {
                amdgpu_ring_clear_ring(ring);
@@ -5279,7 +5278,7 @@ static void gfx_v9_0_get_clockgating_state(void *handle, u64 *flags)
 
 static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
 {
-       return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 is 32bit rptr*/
+       return *ring->rptr_cpu_addr; /* gfx9 is 32bit rptr*/
 }
 
 static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
@@ -5289,7 +5288,7 @@ static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
 
        /* XXX check if swapping is necessary on BE */
        if (ring->use_doorbell) {
-               wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
+               wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
        } else {
                wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
                wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
@@ -5304,7 +5303,7 @@ static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
 
        if (ring->use_doorbell) {
                /* XXX check if swapping is necessary on BE */
-               atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
+               atomic64_set((atomic64_t *)ring->wptr_cpu_addr, ring->wptr);
                WDOORBELL64(ring->doorbell_index, ring->wptr);
        } else {
                WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
@@ -5469,7 +5468,7 @@ static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
 
 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
 {
-       return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */
+       return *ring->rptr_cpu_addr; /* gfx9 hardware is 32bit rptr */
 }
 
 static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
@@ -5478,7 +5477,7 @@ static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
 
        /* XXX check if swapping is necessary on BE */
        if (ring->use_doorbell)
-               wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
+               wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
        else
                BUG();
        return wptr;
@@ -5490,7 +5489,7 @@ static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
 
        /* XXX check if swapping is necessary on BE */
        if (ring->use_doorbell) {
-               atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
+               atomic64_set((atomic64_t *)ring->wptr_cpu_addr, ring->wptr);
                WDOORBELL64(ring->doorbell_index, ring->wptr);
        } else{
                BUG(); /* only DOORBELL method supported on gfx9 now */

diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
index 299de1d131d824bd92e92a846655a70f0b4b121d..d2722adabd1baa4076f8877236cf036db178ba25 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
@@ -407,7 +407,7 @@ static uint64_t jpeg_v2_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
        struct amdgpu_device *adev = ring->adev;
 
        if (ring->use_doorbell)
-               return adev->wb.wb[ring->wptr_offs];
+               return *ring->wptr_cpu_addr;
        else
                return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);
 }
@@ -424,7 +424,7 @@ static void jpeg_v2_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
        struct amdgpu_device *adev = ring->adev;
 
        if (ring->use_doorbell) {
-               adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
+               *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
                WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
        } else {
                WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));

diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
index 8c3227d0b8b44dd39ec5bff62d8ce841c4d092b3..c2bf036a7330a82333a62f03931bbe0f1249041f 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
@@ -402,7 +402,7 @@ static uint64_t jpeg_v2_5_dec_ring_get_wptr(struct amdgpu_ring *ring)
        struct amdgpu_device *adev = ring->adev;
 
        if (ring->use_doorbell)
-               return adev->wb.wb[ring->wptr_offs];
+               return *ring->wptr_cpu_addr;
        else
                return RREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_WPTR);
 }
@@ -419,7 +419,7 @@ static void jpeg_v2_5_dec_ring_set_wptr(struct amdgpu_ring *ring)
        struct amdgpu_device *adev = ring->adev;
 
        if (ring->use_doorbell) {
-               adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
+               *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
                WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
        } else {
                WREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));

diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
index 41a00851b6c50fb74ad5da3ef1d3934dc7c50efc..a1b751d9ac06467c1043f271516d0fa409990aac 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
@@ -427,7 +427,7 @@ static uint64_t jpeg_v3_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
        struct amdgpu_device *adev = ring->adev;
 
        if (ring->use_doorbell)
-               return adev->wb.wb[ring->wptr_offs];
+               return *ring->wptr_cpu_addr;
        else
                return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);
 }
@@ -444,7 +444,7 @@ static void jpeg_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
        struct amdgpu_device *adev = ring->adev;
 
        if (ring->use_doorbell) {
-               adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
+               *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
                WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
        } else {
                WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));

diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
index a7ec4ac89da5c7cba0815b633c5b364884588cdb..0819ffe8e7591e671f8afdcf6e558b296e3784e3 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
@@ -46,7 +46,7 @@ static void mes_v10_1_ring_set_wptr(struct amdgpu_ring *ring)
        struct amdgpu_device *adev = ring->adev;
 
        if (ring->use_doorbell) {
-               atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs],
+               atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
                             ring->wptr);
                WDOORBELL64(ring->doorbell_index, ring->wptr);
        } else {
@@ -56,7 +56,7 @@ static void mes_v10_1_ring_set_wptr(struct amdgpu_ring *ring)
 
 static u64 mes_v10_1_ring_get_rptr(struct amdgpu_ring *ring)
 {
-       return ring->adev->wb.wb[ring->rptr_offs];
+       return *ring->rptr_cpu_addr;
 }
 
 static u64 mes_v10_1_ring_get_wptr(struct amdgpu_ring *ring)
@@ -64,8 +64,7 @@ static u64 mes_v10_1_ring_get_wptr(struct amdgpu_ring *ring)
        u64 wptr;
 
        if (ring->use_doorbell)
-               wptr = atomic64_read((atomic64_t *)
-                                    &ring->adev->wb.wb[ring->wptr_offs]);
+               wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
        else
                BUG();
        return wptr;
@@ -673,13 +672,13 @@ static int mes_v10_1_mqd_init(struct amdgpu_ring *ring)
        mqd->cp_hqd_pq_control = tmp;
 
        /* set the wb address whether it's enabled or not */
-       wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
+       wb_gpu_addr = ring->rptr_gpu_addr;
        mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
        mqd->cp_hqd_pq_rptr_report_addr_hi =
                upper_32_bits(wb_gpu_addr) & 0xffff;
 
        /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
-       wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
+       wb_gpu_addr = ring->wptr_gpu_addr;
        mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8;
        mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
 

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index 84b57b06b20ccba8cb6f598950ea418d7b80cf3d..6bdffdc1c0b92593d26f9529c29b662393fc374d 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -194,7 +194,7 @@ out:
 static uint64_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring)
 {
        /* XXX check if swapping is necessary on BE */
-       return ring->adev->wb.wb[ring->rptr_offs] >> 2;
+       return *ring->rptr_cpu_addr >> 2;
 }
 
 /**
@@ -414,12 +414,10 @@ static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev)
        struct amdgpu_ring *ring;
        u32 rb_cntl, ib_cntl;
        u32 rb_bufsz;
-       u32 wb_offset;
        int i, j, r;
 
        for (i = 0; i < adev->sdma.num_instances; i++) {
                ring = &adev->sdma.instance[i].ring;
-               wb_offset = (ring->rptr_offs * 4);
 
                mutex_lock(&adev->srbm_mutex);
                for (j = 0; j < 16; j++) {
@@ -455,9 +453,9 @@ static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev)
 
                /* set the wb address whether it's enabled or not */
                WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
-                      upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
+                      upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
                WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
-                      lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
+                      lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
 
                rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 8af5c94d526a9c000903462583a7c8007137ce78..2584fa3cb13e7ad5f9aefae8f670026a9bcc5613 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -350,7 +350,7 @@ out:
 static uint64_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
 {
        /* XXX check if swapping is necessary on BE */
-       return ring->adev->wb.wb[ring->rptr_offs] >> 2;
+       return *ring->rptr_cpu_addr >> 2;
 }
 
 /**
@@ -367,7 +367,7 @@ static uint64_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
 
        if (ring->use_doorbell || ring->use_pollmem) {
                /* XXX check if swapping is necessary on BE */
-               wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2;
+               wptr = *ring->wptr_cpu_addr >> 2;
        } else {
                wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;
        }
@@ -387,12 +387,12 @@ static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
        struct amdgpu_device *adev = ring->adev;
 
        if (ring->use_doorbell) {
-               u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs];
+               u32 *wb = (u32 *)ring->wptr_cpu_addr;
                /* XXX check if swapping is necessary on BE */
                WRITE_ONCE(*wb, ring->wptr << 2);
                WDOORBELL32(ring->doorbell_index, ring->wptr << 2);
        } else if (ring->use_pollmem) {
-               u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs];
+               u32 *wb = (u32 *)ring->wptr_cpu_addr;
 
                WRITE_ONCE(*wb, ring->wptr << 2);
        } else {
@@ -649,7 +649,6 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
        struct amdgpu_ring *ring;
        u32 rb_cntl, ib_cntl, wptr_poll_cntl;
        u32 rb_bufsz;
-       u32 wb_offset;
        u32 doorbell;
        u64 wptr_gpu_addr;
        int i, j, r;
@@ -657,7 +656,6 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
        for (i = 0; i < adev->sdma.num_instances; i++) {
                ring = &adev->sdma.instance[i].ring;
                amdgpu_ring_clear_ring(ring);
-               wb_offset = (ring->rptr_offs * 4);
 
                mutex_lock(&adev->srbm_mutex);
                for (j = 0; j < 16; j++) {
@@ -694,9 +692,9 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
 
                /* set the wb address whether it's enabled or not */
                WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
-                      upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
+                      upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
                WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
-                      lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
+                      lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
 
                rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 
@@ -715,7 +713,7 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
                WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell);
 
                /* setup the wptr shadow polling */
-               wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
+               wptr_gpu_addr = ring->wptr_gpu_addr;
 
                WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO + sdma_offsets[i],
                       lower_32_bits(wptr_gpu_addr));

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 80de85847712a567463df222ce323596368095e6..65181efba50ec73c68e44001692259f590983373 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -722,7 +722,7 @@ static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring)
        u64 *rptr;
 
        /* XXX check if swapping is necessary on BE */
-       rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
+       rptr = ((u64 *)ring->rptr_cpu_addr);
 
        DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
        return ((*rptr) >> 2);
@@ -742,7 +742,7 @@ static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring)
 
        if (ring->use_doorbell) {
                /* XXX check if swapping is necessary on BE */
-               wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
+               wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));
                DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
        } else {
                wptr = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI);
@@ -768,7 +768,7 @@ static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
 
        DRM_DEBUG("Setting write pointer\n");
        if (ring->use_doorbell) {
-               u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
+               u64 *wb = (u64 *)ring->wptr_cpu_addr;
 
                DRM_DEBUG("Using doorbell -- "
                                "wptr_offs == 0x%08x "
@@ -811,7 +811,7 @@ static uint64_t sdma_v4_0_page_ring_get_wptr(struct amdgpu_ring *ring)
 
        if (ring->use_doorbell) {
                /* XXX check if swapping is necessary on BE */
-               wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
+               wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));
        } else {
                wptr = RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI);
                wptr = wptr << 32;
@@ -833,7 +833,7 @@ static void sdma_v4_0_page_ring_set_wptr(struct amdgpu_ring *ring)
        struct amdgpu_device *adev = ring->adev;
 
        if (ring->use_doorbell) {
-               u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
+               u64 *wb = (u64 *)ring->wptr_cpu_addr;
 
                /* XXX check if swapping is necessary on BE */
                WRITE_ONCE(*wb, (ring->wptr << 2));
@@ -1174,13 +1174,10 @@ static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i)
 {
        struct amdgpu_ring *ring = &adev->sdma.instance[i].ring;
        u32 rb_cntl, ib_cntl, wptr_poll_cntl;
-       u32 wb_offset;
        u32 doorbell;
        u32 doorbell_offset;
        u64 wptr_gpu_addr;
 
-       wb_offset = (ring->rptr_offs * 4);
-
        rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL);
        rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl);
        WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
@@ -1193,9 +1190,9 @@ static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i)
 
        /* set the wb address whether it's enabled or not */
        WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_HI,
-              upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
+              upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
        WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_LO,
-              lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
+              lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
 
        rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
                                RPTR_WRITEBACK_ENABLE, 1);
@@ -1225,7 +1222,7 @@ static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i)
        WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 0);
 
        /* setup the wptr shadow polling */
-       wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
+       wptr_gpu_addr = ring->wptr_gpu_addr;
        WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO,
                    lower_32_bits(wptr_gpu_addr));
        WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI,
@@ -1264,13 +1261,10 @@ static void sdma_v4_0_page_resume(struct amdgpu_device *adev, unsigned int i)
 {
        struct amdgpu_ring *ring = &adev->sdma.instance[i].page;
        u32 rb_cntl, ib_cntl, wptr_poll_cntl;
-       u32 wb_offset;
        u32 doorbell;
        u32 doorbell_offset;
        u64 wptr_gpu_addr;
 
-       wb_offset = (ring->rptr_offs * 4);
-
        rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL);
        rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl);
        WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
@@ -1283,9 +1277,9 @@ static void sdma_v4_0_page_resume(struct amdgpu_device *adev, unsigned int i)
 
        /* set the wb address whether it's enabled or not */
        WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_HI,
-              upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
+              upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
        WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_LO,
-              lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
+              lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
 
        rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL,
                                RPTR_WRITEBACK_ENABLE, 1);
@@ -1316,7 +1310,7 @@ static void sdma_v4_0_page_resume(struct amdgpu_device *adev, unsigned int i)
        WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 0);
 
        /* setup the wptr shadow polling */
-       wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
+       wptr_gpu_addr = ring->wptr_gpu_addr;
        WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO,
                    lower_32_bits(wptr_gpu_addr));
        WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI,

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index d3939c5f531d3cebc99720607e44758772cc5642..ff359e7f1eb842c66374387afedd4f96dbd99d0b 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
@@ -347,7 +347,7 @@ static uint64_t sdma_v5_0_ring_get_rptr(struct amdgpu_ring *ring)
        u64 *rptr;
 
        /* XXX check if swapping is necessary on BE */
-       rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
+       rptr = (u64 *)ring->rptr_cpu_addr;
 
        DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
        return ((*rptr) >> 2);
@@ -367,7 +367,7 @@ static uint64_t sdma_v5_0_ring_get_wptr(struct amdgpu_ring *ring)
 
        if (ring->use_doorbell) {
                /* XXX check if swapping is necessary on BE */
-               wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
+               wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));
                DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
        } else {
                wptr = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
@@ -400,8 +400,8 @@ static void sdma_v5_0_ring_set_wptr(struct amdgpu_ring *ring)
                                lower_32_bits(ring->wptr << 2),
                                upper_32_bits(ring->wptr << 2));
                /* XXX check if swapping is necessary on BE */
-               adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2);
-               adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2);
+               atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
+                            ring->wptr << 2);
                DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
                                ring->doorbell_index, ring->wptr << 2);
                WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
@@ -708,7 +708,6 @@ static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev)
        struct amdgpu_ring *ring;
        u32 rb_cntl, ib_cntl;
        u32 rb_bufsz;
-       u32 wb_offset;
        u32 doorbell;
        u32 doorbell_offset;
        u32 temp;
@@ -718,7 +717,6 @@ static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev)
 
        for (i = 0; i < adev->sdma.num_instances; i++) {
                ring = &adev->sdma.instance[i].ring;
-               wb_offset = (ring->rptr_offs * 4);
 
                if (!amdgpu_sriov_vf(adev))
                        WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
@@ -741,7 +739,7 @@ static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev)
                WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
 
                /* setup the wptr shadow polling */
-               wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
+               wptr_gpu_addr = ring->wptr_gpu_addr;
                WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
                       lower_32_bits(wptr_gpu_addr));
                WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
@@ -756,9 +754,9 @@ static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev)
 
                /* set the wb address whether it's enabled or not */
                WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
-                      upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
+                      upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
                WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
-                      lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
+                      lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
 
                rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index 8298926f8502a0212dbf07f81681effeded1c3a4..bf2cf95cbf8fbc7dac2b9a3259cd853a1cfee027 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -248,7 +248,7 @@ static uint64_t sdma_v5_2_ring_get_rptr(struct amdgpu_ring *ring)
        u64 *rptr;
 
        /* XXX check if swapping is necessary on BE */
-       rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
+       rptr = (u64 *)ring->rptr_cpu_addr;
 
        DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
        return ((*rptr) >> 2);
@@ -268,7 +268,7 @@ static uint64_t sdma_v5_2_ring_get_wptr(struct amdgpu_ring *ring)
 
        if (ring->use_doorbell) {
                /* XXX check if swapping is necessary on BE */
-               wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
+               wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));
                DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
        } else {
                wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
@@ -301,8 +301,8 @@ static void sdma_v5_2_ring_set_wptr(struct amdgpu_ring *ring)
                                lower_32_bits(ring->wptr << 2),
                                upper_32_bits(ring->wptr << 2));
                /* XXX check if swapping is necessary on BE */
-               adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2);
-               adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2);
+               atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
+                            ring->wptr << 2);
                DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
                                ring->doorbell_index, ring->wptr << 2);
                WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
@@ -609,7 +609,6 @@ static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
        struct amdgpu_ring *ring;
        u32 rb_cntl, ib_cntl;
        u32 rb_bufsz;
-       u32 wb_offset;
        u32 doorbell;
        u32 doorbell_offset;
        u32 temp;
@@ -619,7 +618,6 @@ static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
 
        for (i = 0; i < adev->sdma.num_instances; i++) {
                ring = &adev->sdma.instance[i].ring;
-               wb_offset = (ring->rptr_offs * 4);
 
                if (!amdgpu_sriov_vf(adev))
                        WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
@@ -642,7 +640,7 @@ static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
                WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
 
                /* setup the wptr shadow polling */
-               wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
+               wptr_gpu_addr = ring->wptr_gpu_addr;
                WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
                       lower_32_bits(wptr_gpu_addr));
                WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
@@ -657,9 +655,9 @@ static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
 
                /* set the wb address whether it's enabled or not */
                WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
-                      upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
+                      upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
                WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
-                      lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
+                      lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
 
                rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 

diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
index 2f95235bbfb30bdd31c4469fd2e074b7e9249b56..f675111ace20c2c858180511247f4b05d57b44af 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
@@ -40,7 +40,7 @@ static void si_dma_set_irq_funcs(struct amdgpu_device *adev);
 
 static uint64_t si_dma_ring_get_rptr(struct amdgpu_ring *ring)
 {
-       return ring->adev->wb.wb[ring->rptr_offs>>2];
+       return *ring->rptr_cpu_addr;
 }
 
 static uint64_t si_dma_ring_get_wptr(struct amdgpu_ring *ring)
@@ -153,7 +153,7 @@ static int si_dma_start(struct amdgpu_device *adev)
                WREG32(DMA_RB_RPTR + sdma_offsets[i], 0);
                WREG32(DMA_RB_WPTR + sdma_offsets[i], 0);
 
-               rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
+               rptr_addr = ring->rptr_gpu_addr;
 
                WREG32(DMA_RB_RPTR_ADDR_LO + sdma_offsets[i], lower_32_bits(rptr_addr));
                WREG32(DMA_RB_RPTR_ADDR_HI + sdma_offsets[i], upper_32_bits(rptr_addr) & 0xFF);

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index 2f15b8e0f7d7d2671f31b62811bfb499434ab508..e668b3baa8c60984e087b89a6125324fcc6fef5a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -118,7 +118,7 @@ static uint64_t uvd_v7_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
        struct amdgpu_device *adev = ring->adev;
 
        if (ring->use_doorbell)
-               return adev->wb.wb[ring->wptr_offs];
+               return *ring->wptr_cpu_addr;
 
        if (ring == &adev->uvd.inst[ring->me].ring_enc[0])
                return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR);
@@ -153,7 +153,7 @@ static void uvd_v7_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
 
        if (ring->use_doorbell) {
                /* XXX check if swapping is necessary on BE */
-               adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
+               *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
                WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
                return;
        }
@@ -754,7 +754,7 @@ static int uvd_v7_0_mmsch_start(struct amdgpu_device *adev,
                if (adev->uvd.harvest_config & (1 << i))
                        continue;
                WDOORBELL32(adev->uvd.inst[i].ring_enc[0].doorbell_index, 0);
-               adev->wb.wb[adev->uvd.inst[i].ring_enc[0].wptr_offs] = 0;
+               *adev->uvd.inst[i].ring_enc[0].wptr_cpu_addr = 0;
                adev->uvd.inst[i].ring_enc[0].wptr = 0;
                adev->uvd.inst[i].ring_enc[0].wptr_old = 0;
        }

diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
index d1fc4e0b8265d01d7ae91ba106dca5b06a88ae45..66cd3d11aa4b8fecea7d1ebd5f677feb594929ae 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -83,7 +83,7 @@ static uint64_t vce_v4_0_ring_get_wptr(struct amdgpu_ring *ring)
        struct amdgpu_device *adev = ring->adev;
 
        if (ring->use_doorbell)
-               return adev->wb.wb[ring->wptr_offs];
+               return *ring->wptr_cpu_addr;
 
        if (ring->me == 0)
                return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR));
@@ -106,7 +106,7 @@ static void vce_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
 
        if (ring->use_doorbell) {
                /* XXX check if swapping is necessary on BE */
-               adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
+               *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
                WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
                return;
        }
@@ -177,7 +177,7 @@ static int vce_v4_0_mmsch_start(struct amdgpu_device *adev,
        WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP), 0);
 
        WDOORBELL32(adev->vce.ring[0].doorbell_index, 0);
-       adev->wb.wb[adev->vce.ring[0].wptr_offs] = 0;
+       *adev->vce.ring[0].wptr_cpu_addr = 0;
        adev->vce.ring[0].wptr = 0;
        adev->vce.ring[0].wptr_old = 0;
 

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index 7a7f35e83dd5c62eb4b5026b9a6feeee78274432..8421044d562947b1b56fc6d5db2f80beab37b19e 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -1336,7 +1336,7 @@ static uint64_t vcn_v2_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
        struct amdgpu_device *adev = ring->adev;
 
        if (ring->use_doorbell)
-               return adev->wb.wb[ring->wptr_offs];
+               return *ring->wptr_cpu_addr;
        else
                return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);
 }
@@ -1357,7 +1357,7 @@ static void vcn_v2_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
                        lower_32_bits(ring->wptr) | 0x80000000);
 
        if (ring->use_doorbell) {
-               adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
+               *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
                WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
        } else {
                WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
@@ -1565,12 +1565,12 @@ static uint64_t vcn_v2_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
 
        if (ring == &adev->vcn.inst->ring_enc[0]) {
                if (ring->use_doorbell)
-                       return adev->wb.wb[ring->wptr_offs];
+                       return *ring->wptr_cpu_addr;
                else
                        return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
        } else {
                if (ring->use_doorbell)
-                       return adev->wb.wb[ring->wptr_offs];
+                       return *ring->wptr_cpu_addr;
                else
                        return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
        }
@@ -1589,14 +1589,14 @@ static void vcn_v2_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
 
        if (ring == &adev->vcn.inst->ring_enc[0]) {
                if (ring->use_doorbell) {
-                       adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
+                       *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
                        WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
                } else {
                        WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
                }
        } else {
                if (ring->use_doorbell) {
-                       adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
+                       *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
                        WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
                } else {
                        WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index 17d44be5887756bc5d8fb1dfa3c1a00b338730a8..9352d07539b931a163880dc105a14d4dbabb8f53 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -1491,7 +1491,7 @@ static uint64_t vcn_v2_5_dec_ring_get_wptr(struct amdgpu_ring *ring)
        struct amdgpu_device *adev = ring->adev;
 
        if (ring->use_doorbell)
-               return adev->wb.wb[ring->wptr_offs];
+               return *ring->wptr_cpu_addr;
        else
                return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR);
 }
@@ -1508,7 +1508,7 @@ static void vcn_v2_5_dec_ring_set_wptr(struct amdgpu_ring *ring)
        struct amdgpu_device *adev = ring->adev;
 
        if (ring->use_doorbell) {
-               adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
+               *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
                WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
        } else {
                WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
@@ -1607,12 +1607,12 @@ static uint64_t vcn_v2_5_enc_ring_get_wptr(struct amdgpu_ring *ring)
 
        if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {
                if (ring->use_doorbell)
-                       return adev->wb.wb[ring->wptr_offs];
+                       return *ring->wptr_cpu_addr;
                else
                        return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR);
        } else {
                if (ring->use_doorbell)
-                       return adev->wb.wb[ring->wptr_offs];
+                       return *ring->wptr_cpu_addr;
                else
                        return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2);
        }
@@ -1631,14 +1631,14 @@ static void vcn_v2_5_enc_ring_set_wptr(struct amdgpu_ring *ring)
 
        if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {
                if (ring->use_doorbell) {
-                       adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
+                       *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
                        WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
                } else {
                        WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
                }
        } else {
                if (ring->use_doorbell) {
-                       adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
+                       *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
                        WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
                } else {
                        WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index cb5f0a12333f308d2ec358014ec5cf206f305d11..19cdad38d1348e0f2340e37b900625b4177602ae 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -1695,7 +1695,7 @@ static uint64_t vcn_v3_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
        struct amdgpu_device *adev = ring->adev;
 
        if (ring->use_doorbell)
-               return adev->wb.wb[ring->wptr_offs];
+               return *ring->wptr_cpu_addr;
        else
                return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR);
 }
@@ -1721,7 +1721,7 @@ static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
        }
 
        if (ring->use_doorbell) {
-               adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
+               *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
                WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
        } else {
                WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
@@ -2012,12 +2012,12 @@ static uint64_t vcn_v3_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
 
        if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {
                if (ring->use_doorbell)
-                       return adev->wb.wb[ring->wptr_offs];
+                       return *ring->wptr_cpu_addr;
                else
                        return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR);
        } else {
                if (ring->use_doorbell)
-                       return adev->wb.wb[ring->wptr_offs];
+                       return *ring->wptr_cpu_addr;
                else
                        return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2);
        }
@@ -2036,14 +2036,14 @@ static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
 
        if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {
                if (ring->use_doorbell) {
-                       adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
+                       *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
                        WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
                } else {
                        WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
                }
        } else {
                if (ring->use_doorbell) {
-                       adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
+                       *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
                        WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
                } else {
                        WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));