crypto: hisilicon - modify the value of engine type rate
authorKai Ye <yekai13@huawei.com>
Sat, 20 Nov 2021 04:47:36 +0000 (12:47 +0800)
committerHerbert Xu <herbert@gondor.apana.org.au>
Fri, 26 Nov 2021 05:25:17 +0000 (16:25 +1100)
Modify the value of type rate from new QM spec.

Signed-off-by: Kai Ye <yekai13@huawei.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
drivers/crypto/hisilicon/hpre/hpre_main.c
drivers/crypto/hisilicon/sec2/sec_main.c
drivers/crypto/hisilicon/zip/zip_main.c

index 65a641396c07fe88043c707a49066f1584084842..ebfab3e14499ac5e3242ef6a4f06f63590046826 100644 (file)
 #define HPRE_QM_PM_FLR                 BIT(11)
 #define HPRE_QM_SRIOV_FLR              BIT(12)
 
-#define HPRE_SHAPER_TYPE_RATE          128
+#define HPRE_SHAPER_TYPE_RATE          640
 #define HPRE_VIA_MSI_DSM               1
 #define HPRE_SQE_MASK_OFFSET           8
 #define HPRE_SQE_MASK_LEN              24
index 90551bf38b523a3e3f67974c93a4a855e73de7d5..26d3ab1d308ba64eaf0aa2b46d37adb25ce2ad66 100644 (file)
 
 #define SEC_SQE_MASK_OFFSET            64
 #define SEC_SQE_MASK_LEN               48
-#define SEC_SHAPER_TYPE_RATE           128
+#define SEC_SHAPER_TYPE_RATE           400
 
 struct sec_hw_error {
        u32 int_msk;
index 873971ef9aeedc8e3ae39f690b5d37f9c6b571ae..1a237d95d482f062f46c787f5b570daefffc6b5f 100644 (file)
 #define HZIP_PREFETCH_ENABLE           (~(BIT(26) | BIT(17) | BIT(0)))
 #define HZIP_SVA_PREFETCH_DISABLE      BIT(26)
 #define HZIP_SVA_DISABLE_READY         (BIT(26) | BIT(30))
-#define HZIP_SHAPER_RATE_COMPRESS      252
-#define HZIP_SHAPER_RATE_DECOMPRESS    229
+#define HZIP_SHAPER_RATE_COMPRESS      750
+#define HZIP_SHAPER_RATE_DECOMPRESS    140
 #define HZIP_DELAY_1_US                1
 #define HZIP_POLL_TIMEOUT_US   1000