arm64: zynqmp: Add mali-400 gpu node for zynqmp
authorParth Gajjar <parth.gajjar@amd.com>
Tue, 21 Mar 2023 07:06:19 +0000 (00:06 -0700)
committerMichal Simek <michal.simek@amd.com>
Fri, 12 May 2023 11:23:07 +0000 (13:23 +0200)
Add mali-400 gpu node for zynqmp.
Enabled gpu node for xilinx boards.

Signed-off-by: Parth Gajjar <parth.gajjar@amd.com>
Signed-off-by: Vishal Sagar <vishal.sagar@amd.com>
Link: https://lore.kernel.org/r/20230321070619.29440-3-parth.gajjar@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts
arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
arch/arm64/boot/dts/xilinx/zynqmp.dtsi

index 3e9979ab60bbcdf1b0e9381738988ca7b1362177..5e7e1bf5b811530d37f85aaf53279b99408805af 100644 (file)
        clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
 };
 
+&gpu {
+       clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>;
+};
+
 &lpd_dma_chan1 {
        clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
 };
index 20e83ca47b5dba9e6ef9ddd761e396d8987a5a06..34412304d09fa384c4ace7989c95e6336896a2dd 100644 (file)
                          "", "", "", "", "", /* 165 - 169 */
                          "", "", "", ""; /* 170 - 173 */
 };
+
+&gpu {
+       status = "okay";
+};
index b05be2552826574b787782689b63c3bf5723f275..f89ef2afcd9e570d5f61e5ce9e22d1636f68c653 100644 (file)
        pinctrl-0 = <&pinctrl_gpio_default>;
 };
 
+&gpu {
+       status = "okay";
+};
 
 &i2c1 {
        status = "okay";
index 05a2b79738afb41dd8b3ff3d6935d0877d288093..6e0106bf12942c89e97784baf71254dfaf237906 100644 (file)
        status = "okay";
 };
 
+&gpu {
+       status = "okay";
+};
+
 &i2c0 {
        clock-frequency = <400000>;
        status = "okay";
index 6948fd40554b3f344566db63f47cde03a0561d78..c74bc3ff703b857e058ea8b9f60da2357636cd0e 100644 (file)
                          "", "", "", "";
 };
 
+&gpu {
+       status = "okay";
+};
+
 &i2c1 {
        status = "okay";
        pinctrl-names = "default", "gpio";
index 5fd6b70a154a9af74da89c584c1b40686c0b9aa2..13c43324f1d247393e278ccd39e3da883ae4e5f5 100644 (file)
        pinctrl-0 = <&pinctrl_gpio_default>;
 };
 
+&gpu {
+       status = "okay";
+};
+
 &i2c0 {
        status = "okay";
        clock-frequency = <400000>;
index bd8f20f3223d7e5d127e0116739f0b041e799eb3..485585c491f4241de63e625607d4022880da34ef 100644 (file)
        status = "okay";
 };
 
+&gpu {
+       status = "okay";
+};
+
 &i2c1 {
        status = "okay";
        clock-frequency = <400000>;
index 96feaad30166345b2269595adb3665360c121318..44ec9edd24527bd1fb2175f32816df867e3dd2af 100644 (file)
        status = "okay";
 };
 
+&gpu {
+       status = "okay";
+};
+
 &i2c1 {
        status = "okay";
        clock-frequency = <400000>;
index 24a252317150f0e9fbe617977229b7407f46e7e4..09773b7200f836d464c7b303971b3e689f0ff2f1 100644 (file)
        pinctrl-0 = <&pinctrl_gpio_default>;
 };
 
+&gpu {
+       status = "okay";
+};
+
 &i2c0 {
        status = "okay";
        clock-frequency = <400000>;
index d685d8fbc36a1a853d18b9ccb714fc0581d14f1c..e0305dcbb010d901c6a662f766db5d8b8507b832 100644 (file)
        pinctrl-0 = <&pinctrl_gpio_default>;
 };
 
+&gpu {
+       status = "okay";
+};
+
 &i2c0 {
        status = "okay";
        clock-frequency = <400000>;
index 153db59dc4b3e4051dc17f4088581caf77d35c76..bb0d0be30aa0e62a3c8a6c86ad88fab371b0f880 100644 (file)
                        interrupts = <1 9 0xf04>;
                };
 
+               gpu: gpu@fd4b0000 {
+                       status = "disabled";
+                       compatible = "xlnx,zynqmp-mali", "arm,mali-400";
+                       reg = <0x0 0xfd4b0000 0x0 0x10000>;
+                       interrupt-parent = <&gic>;
+                       interrupts = <0 132 4>, <0 132 4>, <0 132 4>,
+                                    <0 132 4>, <0 132 4>, <0 132 4>;
+                       interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1";
+                       clock-names = "bus", "core";
+                       power-domains = <&zynqmp_firmware PD_GPU>;
+               };
+
                /* LPDDMA default allows only secured access. inorder to enable
                 * These dma channels, Users should ensure that these dma
                 * Channels are allowed for non secure access.