drm/amdgpu: retire rlc callbacks sriov_rreg/wreg

Not needed anymore.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Zhou, Peng Ju <PengJu.Zhou@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
index 286b2347d063f5418dbfc4ba0f4adfe6d35368ff..3f671a62b0098e38efc37817ca2755be0007d417 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
@@ -127,8 +127,6 @@ struct amdgpu_rlc_funcs {
        void (*reset)(struct amdgpu_device *adev);
        void (*start)(struct amdgpu_device *adev);
        void (*update_spm_vmid)(struct amdgpu_device *adev, unsigned vmid);
-       void (*sriov_wreg)(struct amdgpu_device *adev, u32 offset, u32 v, u32 acc_flags, u32 hwip);
-       u32 (*sriov_rreg)(struct amdgpu_device *adev, u32 offset, u32 acc_flags, u32 hwip);
        bool (*is_rlcg_access_range)(struct amdgpu_device *adev, uint32_t reg);
 };
 

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index 8c27d31f3e53422ce8f32f8becb66f11fce35a8d..80c25176c993230734548e5a72395f777e1b9e10 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -821,8 +821,9 @@ void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev,
        }
 }
 
-bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev, u32 acc_flags,
-                                         u32 hwip, bool write, u32 *rlcg_flag)
+static bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev,
+                                                u32 acc_flags, u32 hwip,
+                                                bool write, u32 *rlcg_flag)
 {
        bool ret = false;
 

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
index dbfa3ba445c37c845a863e113f92321a4b1abbec..c5edd84c1c125e226f544f86999649d38fe5f66e 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
@@ -334,8 +334,6 @@ enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *ad
 void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev,
                        struct amdgpu_video_codec_info *encode, uint32_t encode_array_size,
                        struct amdgpu_video_codec_info *decode, uint32_t decode_array_size);
-bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev, u32 acc_flags,
-                                         u32 hwip, bool write, u32 *rlcg_flag);
 void amdgpu_sriov_wreg(struct amdgpu_device *adev,
                       u32 offset, u32 value,
                       u32 acc_flags, u32 hwip);

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 3fb484214d3a223ef2fd199c424f408f8082c934..f54e106e2b86f63f5431edd870cdfbb6f0b01f98 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -56,10 +56,6 @@
 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid     1
 #define GFX10_MEC_HPD_SIZE     2048
 
-#define RLCG_VFGATE_DISABLED   0x4000000
-#define RLCG_WRONG_OPERATION_TYPE      0x2000000
-#define RLCG_NOT_IN_RANGE      0x1000000
-
 #define F32_CE_PROGRAM_RAM_SIZE                65536
 #define RLCG_UCODE_LOADING_START_ADDRESS       0x00002000L
 
@@ -180,9 +176,6 @@
 #define mmRLC_SPARE_INT_0_Sienna_Cichlid               0x4ca5
 #define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX      1
 
-#define RLCG_ERROR_REPORT_ENABLED(adev) \
-       (amdgpu_sriov_reg_indirect_mmhub(adev) || amdgpu_sriov_reg_indirect_gc(adev))
-
 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
@@ -1458,111 +1451,6 @@ static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
        SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000)
 };
 
-static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32_t flag)
-{
-       static void *scratch_reg0;
-       static void *scratch_reg1;
-       static void *scratch_reg2;
-       static void *scratch_reg3;
-       static void *spare_int;
-       static uint32_t grbm_cntl;
-       static uint32_t grbm_idx;
-       uint32_t i = 0;
-       uint32_t retries = 50000;
-       u32 ret = 0;
-       u32 tmp;
-
-       scratch_reg0 = adev->rmmio +
-                      (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0) * 4;
-       scratch_reg1 = adev->rmmio +
-                      (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1) * 4;
-       scratch_reg2 = adev->rmmio +
-                      (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG2) * 4;
-       scratch_reg3 = adev->rmmio +
-                      (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3) * 4;
-
-       if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) {
-               spare_int = adev->rmmio +
-                           (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX]
-                            + mmRLC_SPARE_INT_0_Sienna_Cichlid) * 4;
-       } else {
-               spare_int = adev->rmmio +
-                           (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT) * 4;
-       }
-
-       grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL;
-       grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX;
-
-       if (offset == grbm_cntl || offset == grbm_idx) {
-               if (offset  == grbm_cntl)
-                       writel(v, scratch_reg2);
-               else if (offset == grbm_idx)
-                       writel(v, scratch_reg3);
-
-               writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));
-       } else {
-               writel(v, scratch_reg0);
-               writel(offset | flag, scratch_reg1);
-               writel(1, spare_int);
-
-               for (i = 0; i < retries; i++) {
-                       tmp = readl(scratch_reg1);
-                       if (!(tmp & flag))
-                               break;
-
-                       udelay(10);
-               }
-
-               if (i >= retries) {
-                       if (RLCG_ERROR_REPORT_ENABLED(adev)) {
-                               if (tmp & RLCG_VFGATE_DISABLED)
-                                       pr_err("The vfgate is disabled, program reg:0x%05x failed!\n", offset);
-                               else if (tmp & RLCG_WRONG_OPERATION_TYPE)
-                                       pr_err("Wrong operation type, program reg:0x%05x failed!\n", offset);
-                               else if (tmp & RLCG_NOT_IN_RANGE)
-                                       pr_err("The register is not in range, program reg:0x%05x failed!\n", offset);
-                               else
-                                       pr_err("Unknown error type, program reg:0x%05x failed!\n", offset);
-                       } else
-                               pr_err("timeout: rlcg program reg:0x%05x failed!\n", offset);
-               }
-       }
-
-       ret = readl(scratch_reg0);
-
-       return ret;
-}
-
-static void gfx_v10_sriov_wreg(struct amdgpu_device *adev, u32 offset, u32 value, u32 acc_flags, u32 hwip)
-{
-       u32 rlcg_flag;
-
-       if (!amdgpu_sriov_runtime(adev) &&
-           amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, true, &rlcg_flag)) {
-               gfx_v10_rlcg_rw(adev, offset, value, rlcg_flag);
-               return;
-       }
-
-       if (acc_flags & AMDGPU_REGS_NO_KIQ)
-               WREG32_NO_KIQ(offset, value);
-       else
-               WREG32(offset, value);
-}
-
-static u32 gfx_v10_sriov_rreg(struct amdgpu_device *adev, u32 offset, u32 acc_flags, u32 hwip)
-{
-       u32 rlcg_flag;
-
-       if (!amdgpu_sriov_runtime(adev) &&
-           amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, false, &rlcg_flag))
-               return gfx_v10_rlcg_rw(adev, offset, 0, rlcg_flag);
-
-       if (acc_flags & AMDGPU_REGS_NO_KIQ)
-               return RREG32_NO_KIQ(offset);
-       else
-               return RREG32(offset);
-}
-
 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
 {
        /* Pending on emulation bring up */
@@ -8370,8 +8258,6 @@ static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
        .reset = gfx_v10_0_rlc_reset,
        .start = gfx_v10_0_rlc_start,
        .update_spm_vmid = gfx_v10_0_update_spm_vmid,
-       .sriov_wreg = gfx_v10_sriov_wreg,
-       .sriov_rreg = gfx_v10_sriov_rreg,
        .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
 };
 

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index c7bccf1a28b427d6ea7feba2645d64f948881272..ca7b886c6ce6bb114fc495c73ffe1fe6878dd587 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -63,10 +63,6 @@
 #define mmGCEA_PROBE_MAP                        0x070c
 #define mmGCEA_PROBE_MAP_BASE_IDX               0
 
-#define GFX9_RLCG_VFGATE_DISABLED              0x4000000
-#define GFX9_RLCG_WRONG_OPERATION_TYPE         0x2000000
-#define GFX9_RLCG_NOT_IN_RANGE                 0x1000000
-
 MODULE_FIRMWARE("amdgpu/vega10_ce.bin");
 MODULE_FIRMWARE("amdgpu/vega10_pfp.bin");
 MODULE_FIRMWARE("amdgpu/vega10_me.bin");
@@ -743,106 +739,6 @@ static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] =
        mmRLC_SRM_INDEX_CNTL_DATA_7 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 };
 
-static u32 gfx_v9_0_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32_t flag)
-{
-       static void *scratch_reg0;
-       static void *scratch_reg1;
-       static void *scratch_reg2;
-       static void *scratch_reg3;
-       static void *spare_int;
-       static uint32_t grbm_cntl;
-       static uint32_t grbm_idx;
-       uint32_t i = 0;
-       uint32_t retries = 50000;
-       u32 ret = 0;
-       u32 tmp;
-
-       scratch_reg0 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0)*4;
-       scratch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4;
-       scratch_reg2 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG2_BASE_IDX] + mmSCRATCH_REG2)*4;
-       scratch_reg3 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG3_BASE_IDX] + mmSCRATCH_REG3)*4;
-       spare_int = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT)*4;
-
-       grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL;
-       grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX;
-
-       if (offset == grbm_cntl || offset == grbm_idx) {
-               if (offset  == grbm_cntl)
-                       writel(v, scratch_reg2);
-               else if (offset == grbm_idx)
-                       writel(v, scratch_reg3);
-
-               writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));
-       } else {
-               /*
-                * SCRATCH_REG0         = read/write value
-                * SCRATCH_REG1[30:28]  = command
-                * SCRATCH_REG1[19:0]   = address in dword
-                * SCRATCH_REG1[26:24]  = Error reporting
-                */
-               writel(v, scratch_reg0);
-               writel(offset | flag, scratch_reg1);
-               writel(1, spare_int);
-
-               for (i = 0; i < retries; i++) {
-                       tmp = readl(scratch_reg1);
-                       if (!(tmp & flag))
-                               break;
-
-                       udelay(10);
-               }
-
-               if (i >= retries) {
-                       if (amdgpu_sriov_reg_indirect_gc(adev)) {
-                               if (tmp & GFX9_RLCG_VFGATE_DISABLED)
-                                       pr_err("The vfgate is disabled, program reg:0x%05x failed!\n", offset);
-                               else if (tmp & GFX9_RLCG_WRONG_OPERATION_TYPE)
-                                       pr_err("Wrong operation type, program reg:0x%05x failed!\n", offset);
-                               else if (tmp & GFX9_RLCG_NOT_IN_RANGE)
-                                       pr_err("The register is not in range, program reg:0x%05x failed!\n", offset);
-                               else
-                                       pr_err("Unknown error type, program reg:0x%05x failed!\n", offset);
-                       } else
-                               pr_err("timeout: rlcg program reg:0x%05x failed!\n", offset);
-               }
-       }
-
-       ret = readl(scratch_reg0);
-
-       return ret;
-}
-
-static u32 gfx_v9_0_sriov_rreg(struct amdgpu_device *adev, u32 offset, u32 acc_flags, u32 hwip)
-{
-       u32 rlcg_flag;
-
-       if (!amdgpu_sriov_runtime(adev) &&
-           amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, false, &rlcg_flag))
-               return gfx_v9_0_rlcg_rw(adev, offset, 0, rlcg_flag);
-
-       if (acc_flags & AMDGPU_REGS_NO_KIQ)
-               return RREG32_NO_KIQ(offset);
-       else
-               return RREG32(offset);
-}
-
-static void gfx_v9_0_sriov_wreg(struct amdgpu_device *adev, u32 offset,
-                              u32 value, u32 acc_flags, u32 hwip)
-{
-       u32 rlcg_flag;
-
-       if (!amdgpu_sriov_runtime(adev) &&
-           amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, true, &rlcg_flag)) {
-               gfx_v9_0_rlcg_rw(adev, offset, value, rlcg_flag);
-               return;
-       }
-
-       if (acc_flags & AMDGPU_REGS_NO_KIQ)
-               WREG32_NO_KIQ(offset, value);
-       else
-               WREG32(offset, value);
-}
-
 #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
 #define VEGA12_GB_ADDR_CONFIG_GOLDEN 0x24104041
 #define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042
@@ -5268,8 +5164,6 @@ static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
        .reset = gfx_v9_0_rlc_reset,
        .start = gfx_v9_0_rlc_start,
        .update_spm_vmid = gfx_v9_0_update_spm_vmid,
-       .sriov_wreg = gfx_v9_0_sriov_wreg,
-       .sriov_rreg = gfx_v9_0_sriov_rreg,
        .is_rlcg_access_range = gfx_v9_0_is_rlcg_access_range,
 };