gen_update_fprs_dirty(dc, dst);
}
-static TCGv_i32 gen_dest_fpr_F(DisasContext *dc)
-{
- return tcg_temp_new_i32();
-}
-
static TCGv_i64 gen_load_fpr_D(DisasContext *dc, unsigned int src)
{
src = DFPREG(src);
memop |= MO_ALIGN_4;
switch (size) {
case MO_32:
- d32 = gen_dest_fpr_F(dc);
+ d32 = tcg_temp_new_i32();
tcg_gen_qemu_ld_i32(d32, addr, da->mem_idx, memop);
gen_store_fpr_F(dc, rd, d32);
break;
case MO_32:
d64 = tcg_temp_new_i64();
gen_helper_ld_asi(d64, tcg_env, addr, r_asi, r_mop);
- d32 = gen_dest_fpr_F(dc);
+ d32 = tcg_temp_new_i32();
tcg_gen_extrl_i64_i32(d32, d64);
gen_store_fpr_F(dc, rd, d32);
break;
s1 = gen_load_fpr_F(dc, rs);
s2 = gen_load_fpr_F(dc, rd);
- dst = gen_dest_fpr_F(dc);
+ dst = tcg_temp_new_i32();
zero = tcg_constant_i32(0);
tcg_gen_movcond_i32(TCG_COND_NE, dst, c32, zero, s1, s2);
return true;
}
- dst = gen_dest_fpr_F(dc);
+ dst = tcg_temp_new_i32();
src = gen_load_fpr_D(dc, a->rs);
func(dst, src);
gen_store_fpr_F(dc, a->rd, dst);
}
gen_op_clear_ieee_excp_and_FTT();
- dst = gen_dest_fpr_F(dc);
+ dst = tcg_temp_new_i32();
src = gen_load_fpr_D(dc, a->rs);
func(dst, tcg_env, src);
gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
gen_op_clear_ieee_excp_and_FTT();
gen_op_load_fpr_QT1(QFPREG(a->rs));
- dst = gen_dest_fpr_F(dc);
+ dst = tcg_temp_new_i32();
func(dst, tcg_env);
gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
gen_store_fpr_F(dc, a->rd, dst);