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ARM: dts: wpcm450: Add FIU SPI controller node
author
Jonathan Neuschäfer
<j.neuschaefer@gmx.net>
Sat, 5 Nov 2022 18:59:08 +0000
(19:59 +0100)
committer
Joel Stanley
<joel@jms.id.au>
Tue, 22 Nov 2022 01:37:20 +0000
(12:07 +1030)
Add the SPI controller (FIU, Flash Interface Unit) to the WPCM450
devicetree, according to the newly defined binding, as well as the SHM
(shared memory interface) syscon.
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Link:
https://lore.kernel.org/r/20221105185911.1547847-6-j.neuschaefer@gmx.net
Signed-off-by: Joel Stanley <joel@jms.id.au>
arch/arm/boot/dts/nuvoton-wpcm450.dtsi
patch
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diff --git
a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi
b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi
index 93595850a4c3c5fffeb0d494e975544d54524438..0adf0a7a6a7f24d8072bdbb7d007a047188e4d02 100644
(file)
--- a/
arch/arm/boot/dts/nuvoton-wpcm450.dtsi
+++ b/
arch/arm/boot/dts/nuvoton-wpcm450.dtsi
@@
-456,5
+456,21
@@
function = "hg7";
};
};
+
+ fiu: spi-controller@c8000000 {
+ compatible = "nuvoton,wpcm450-fiu";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xc8000000 0x1000>, <0xc0000000 0x4000000>;
+ reg-names = "control", "memory";
+ clocks = <&clk 0>;
+ status = "disabled";
+ };
+
+ shm: syscon@c8001000 {
+ compatible = "nuvoton,wpcm450-shm", "syscon";
+ reg = <0xc8001000 0x1000>;
+ reg-io-width = <1>;
+ };
};
};