buf, buf_bytes);
for (uint32_t i = 0; i < buf_bytes; i++) {
- sdbus_write_data(&s->sdbus, buf[i]);
+ sdbus_write_byte(&s->sdbus, buf[i]);
}
/* Read from SD bus */
s->startbit_detect = value;
break;
case REG_SD_FIFO: /* Read/Write FIFO */
- sdbus_write_data(&s->sdbus, value & 0xff);
- sdbus_write_data(&s->sdbus, (value >> 8) & 0xff);
- sdbus_write_data(&s->sdbus, (value >> 16) & 0xff);
- sdbus_write_data(&s->sdbus, (value >> 24) & 0xff);
+ sdbus_write_byte(&s->sdbus, value & 0xff);
+ sdbus_write_byte(&s->sdbus, (value >> 8) & 0xff);
+ sdbus_write_byte(&s->sdbus, (value >> 16) & 0xff);
+ sdbus_write_byte(&s->sdbus, (value >> 24) & 0xff);
allwinner_sdhost_update_transfer_cnt(s, sizeof(uint32_t));
allwinner_sdhost_auto_stop(s);
allwinner_sdhost_update_irq(s);
}
n--;
s->datacnt--;
- sdbus_write_data(&s->sdbus, value & 0xff);
+ sdbus_write_byte(&s->sdbus, value & 0xff);
value >>= 8;
}
}
return 0;
}
-void sdbus_write_data(SDBus *sdbus, uint8_t value)
+void sdbus_write_byte(SDBus *sdbus, uint8_t value)
{
SDState *card = get_card(sdbus);
if (!s->enabled) {
break;
}
- sdbus_write_data(&s->sdbus, (value >> 24) & 0xff);
- sdbus_write_data(&s->sdbus, (value >> 16) & 0xff);
- sdbus_write_data(&s->sdbus, (value >> 8) & 0xff);
- sdbus_write_data(&s->sdbus, value & 0xff);
+ sdbus_write_byte(&s->sdbus, (value >> 24) & 0xff);
+ sdbus_write_byte(&s->sdbus, (value >> 16) & 0xff);
+ sdbus_write_byte(&s->sdbus, (value >> 8) & 0xff);
+ sdbus_write_byte(&s->sdbus, value & 0xff);
break;
case R_ENABLE:
s->regs[addr] = value;
}
n--;
s->datacnt--;
- sdbus_write_data(&s->sdbus, value & 0xff);
+ sdbus_write_byte(&s->sdbus, value & 0xff);
value >>= 8;
}
}
if (s->cmdat & CMDAT_WR_RD) {
while (s->bytesleft && s->tx_len) {
- sdbus_write_data(&s->sdbus, s->tx_fifo[s->tx_start++]);
+ sdbus_write_byte(&s->sdbus, s->tx_fifo[s->tx_start++]);
s->tx_start &= 0x1f;
s->tx_len --;
s->bytesleft --;
}
for (index = 0; index < (s->blksize & BLOCK_SIZE_MASK); index++) {
- sdbus_write_data(&s->sdbus, s->fifo_buffer[index]);
+ sdbus_write_byte(&s->sdbus, s->fifo_buffer[index]);
}
/* Next data can be written through BUFFER DATORT register */
s->sdmasysad += s->data_count - begin;
if (s->data_count == block_size) {
for (n = 0; n < block_size; n++) {
- sdbus_write_data(&s->sdbus, s->fifo_buffer[n]);
+ sdbus_write_byte(&s->sdbus, s->fifo_buffer[n]);
}
s->data_count = 0;
if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
} else {
dma_memory_read(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt);
for (n = 0; n < datacnt; n++) {
- sdbus_write_data(&s->sdbus, s->fifo_buffer[n]);
+ sdbus_write_byte(&s->sdbus, s->fifo_buffer[n]);
}
}
s->blkcnt--;
dscr.addr += s->data_count - begin;
if (s->data_count == block_size) {
for (n = 0; n < block_size; n++) {
- sdbus_write_data(&s->sdbus, s->fifo_buffer[n]);
+ sdbus_write_byte(&s->sdbus, s->fifo_buffer[n]);
}
s->data_count = 0;
if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
uint8_t sdbus_get_dat_lines(SDBus *sdbus);
bool sdbus_get_cmd_line(SDBus *sdbus);
int sdbus_do_command(SDBus *sd, SDRequest *req, uint8_t *response);
-void sdbus_write_data(SDBus *sd, uint8_t value);
+/**
+ * Write a byte to a SD bus.
+ * @sd: bus
+ * @value: byte to write
+ *
+ * Write a byte on the data lines of a SD bus.
+ */
+void sdbus_write_byte(SDBus *sd, uint8_t value);
uint8_t sdbus_read_data(SDBus *sd);
bool sdbus_data_ready(SDBus *sd);
bool sdbus_get_inserted(SDBus *sd);