r8169: add support for RTL8126A

This adds support for the RTL8126A found on Asus z790 Maximus Formula.
It was successfully tested w/o the firmware at 1000Mbps. Firmware file
has been provided by Realtek and submitted to linux-firmware.
2.5G and 5G modes are untested.

Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/realtek/r8169.h b/drivers/net/ethernet/realtek/r8169.h
index 81567fcf395799701ce3ba597374daa8342b94e9..c921456edeb9a43074eea6b06d51768da6a7d106 100644 (file)
--- a/drivers/net/ethernet/realtek/r8169.h
+++ b/drivers/net/ethernet/realtek/r8169.h
@@ -68,6 +68,7 @@ enum mac_version {
        /* support for RTL_GIGA_MAC_VER_60 has been removed */
        RTL_GIGA_MAC_VER_61,
        RTL_GIGA_MAC_VER_63,
+       RTL_GIGA_MAC_VER_65,
        RTL_GIGA_MAC_NONE
 };
 

diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethernet/realtek/r8169_main.c
index e0abdbcfadeea7f1e2af4b9a14df98135a10c482..c7086953974ee8d72b6cc775ddb671d5f60b008a 100644 (file)
--- a/drivers/net/ethernet/realtek/r8169_main.c
+++ b/drivers/net/ethernet/realtek/r8169_main.c
@@ -55,6 +55,7 @@
 #define FIRMWARE_8107E_2       "rtl_nic/rtl8107e-2.fw"
 #define FIRMWARE_8125A_3       "rtl_nic/rtl8125a-3.fw"
 #define FIRMWARE_8125B_2       "rtl_nic/rtl8125b-2.fw"
+#define FIRMWARE_8126A_2       "rtl_nic/rtl8126a-2.fw"
 
 #define TX_DMA_BURST   7       /* Maximum PCI burst, '7' is unlimited */
 #define InterFrameGap  0x03    /* 3 means InterFrameGap = the shortest one */
@@ -136,6 +137,7 @@ static const struct {
        [RTL_GIGA_MAC_VER_61] = {"RTL8125A",            FIRMWARE_8125A_3},
        /* reserve 62 for CFG_METHOD_4 in the vendor driver */
        [RTL_GIGA_MAC_VER_63] = {"RTL8125B",            FIRMWARE_8125B_2},
+       [RTL_GIGA_MAC_VER_65] = {"RTL8126A",            FIRMWARE_8126A_2},
 };
 
 static const struct pci_device_id rtl8169_pci_tbl[] = {
@@ -158,6 +160,7 @@ static const struct pci_device_id rtl8169_pci_tbl[] = {
        { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
        { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
        { PCI_VDEVICE(REALTEK,  0x8125) },
+       { PCI_VDEVICE(REALTEK,  0x8126) },
        { PCI_VDEVICE(REALTEK,  0x3000) },
        {}
 };
@@ -327,8 +330,12 @@ enum rtl8168_registers {
 };
 
 enum rtl8125_registers {
+       INT_CFG0_8125           = 0x34,
+#define INT_CFG0_ENABLE_8125           BIT(0)
+#define INT_CFG0_CLKREQEN              BIT(3)
        IntrMask_8125           = 0x38,
        IntrStatus_8125         = 0x3c,
+       INT_CFG1_8125           = 0x7a,
        TxPoll_8125             = 0x90,
        MAC0_BKP                = 0x19e0,
        EEE_TXIDLE_TIMER_8125   = 0x6048,
@@ -1139,7 +1146,7 @@ static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
        case RTL_GIGA_MAC_VER_31:
                r8168dp_2_mdio_write(tp, location, val);
                break;
-       case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
+       case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65:
                r8168g_mdio_write(tp, location, val);
                break;
        default:
@@ -1154,7 +1161,7 @@ static int rtl_readphy(struct rtl8169_private *tp, int location)
        case RTL_GIGA_MAC_VER_28:
        case RTL_GIGA_MAC_VER_31:
                return r8168dp_2_mdio_read(tp, location);
-       case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
+       case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65:
                return r8168g_mdio_read(tp, location);
        default:
                return r8169_mdio_read(tp, location);
@@ -1340,7 +1347,7 @@ static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable)
        case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26:
        case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30:
        case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37:
-       case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63:
+       case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_65:
                if (enable)
                        RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN);
                else
@@ -1507,7 +1514,7 @@ static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
                break;
        case RTL_GIGA_MAC_VER_34:
        case RTL_GIGA_MAC_VER_37:
-       case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63:
+       case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_65:
                if (wolopts)
                        rtl_mod_config2(tp, 0, PME_SIGNAL);
                else
@@ -2073,6 +2080,9 @@ static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii)
                u16 val;
                enum mac_version ver;
        } mac_info[] = {
+               /* 8126A family. */
+               { 0x7cf, 0x649, RTL_GIGA_MAC_VER_65 },
+
                /* 8125B family. */
                { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 },
 
@@ -2343,6 +2353,7 @@ static void rtl_init_rxcfg(struct rtl8169_private *tp)
                RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST);
                break;
        case RTL_GIGA_MAC_VER_63:
+       case RTL_GIGA_MAC_VER_65:
                RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST |
                        RX_PAUSE_SLOT_ON);
                break;
@@ -2529,7 +2540,7 @@ static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp)
        case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61:
                rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
                break;
-       case RTL_GIGA_MAC_VER_63:
+       case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_65:
                RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
                rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
                rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42);
@@ -2772,7 +2783,7 @@ static void rtl_enable_exit_l1(struct rtl8169_private *tp)
        case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38:
                rtl_eri_set_bits(tp, 0xd4, 0x0c00);
                break;
-       case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
+       case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65:
                r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80);
                break;
        default:
@@ -2786,7 +2797,7 @@ static void rtl_disable_exit_l1(struct rtl8169_private *tp)
        case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
                rtl_eri_clear_bits(tp, 0xd4, 0x1f00);
                break;
-       case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
+       case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65:
                r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0);
                break;
        default:
@@ -2796,6 +2807,8 @@ static void rtl_disable_exit_l1(struct rtl8169_private *tp)
 
 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
 {
+       u8 val8;
+
        if (tp->mac_version < RTL_GIGA_MAC_VER_32)
                return;
 
@@ -2809,11 +2822,19 @@ static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
                        return;
 
                rtl_mod_config5(tp, 0, ASPM_en);
-               rtl_mod_config2(tp, 0, ClkReqEn);
+               switch (tp->mac_version) {
+               case RTL_GIGA_MAC_VER_65:
+                       val8 = RTL_R8(tp, INT_CFG0_8125) | INT_CFG0_CLKREQEN;
+                       RTL_W8(tp, INT_CFG0_8125, val8);
+                       break;
+               default:
+                       rtl_mod_config2(tp, 0, ClkReqEn);
+                       break;
+               }
 
                switch (tp->mac_version) {
                case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48:
-               case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63:
+               case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_65:
                        /* reset ephy tx/rx disable timer */
                        r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0);
                        /* chip can trigger L1.2 */
@@ -2825,14 +2846,22 @@ static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
        } else {
                switch (tp->mac_version) {
                case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48:
-               case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63:
+               case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_65:
                        r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0);
                        break;
                default:
                        break;
                }
 
-               rtl_mod_config2(tp, ClkReqEn, 0);
+               switch (tp->mac_version) {
+               case RTL_GIGA_MAC_VER_65:
+                       val8 = RTL_R8(tp, INT_CFG0_8125) & ~INT_CFG0_CLKREQEN;
+                       RTL_W8(tp, INT_CFG0_8125, val8);
+                       break;
+               default:
+                       rtl_mod_config2(tp, ClkReqEn, 0);
+                       break;
+               }
                rtl_mod_config5(tp, ASPM_en, 0);
        }
 }
@@ -3545,10 +3574,15 @@ static void rtl_hw_start_8125_common(struct rtl8169_private *tp)
        /* disable new tx descriptor format */
        r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);
 
-       if (tp->mac_version == RTL_GIGA_MAC_VER_63)
+       if (tp->mac_version == RTL_GIGA_MAC_VER_65)
+               RTL_W8(tp, 0xD8, RTL_R8(tp, 0xD8) & ~0x02);
+
+       if (tp->mac_version == RTL_GIGA_MAC_VER_65)
+               r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);
+       else if (tp->mac_version == RTL_GIGA_MAC_VER_63)
                r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200);
        else
-               r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);
+               r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0300);
 
        if (tp->mac_version == RTL_GIGA_MAC_VER_63)
                r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000);
@@ -3561,6 +3595,10 @@ static void rtl_hw_start_8125_common(struct rtl8169_private *tp)
        r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);
        r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);
        r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001);
+       if (tp->mac_version == RTL_GIGA_MAC_VER_65)
+               r8168_mac_ocp_modify(tp, 0xea1c, 0x0300, 0x0000);
+       else
+               r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
        r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403);
        r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068);
        r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f);
@@ -3575,10 +3613,10 @@ static void rtl_hw_start_8125_common(struct rtl8169_private *tp)
 
        rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10);
 
-       if (tp->mac_version == RTL_GIGA_MAC_VER_63)
-               rtl8125b_config_eee_mac(tp);
-       else
+       if (tp->mac_version == RTL_GIGA_MAC_VER_61)
                rtl8125a_config_eee_mac(tp);
+       else
+               rtl8125b_config_eee_mac(tp);
 
        rtl_disable_rxdvgate(tp);
 }
@@ -3622,6 +3660,12 @@ static void rtl_hw_start_8125b(struct rtl8169_private *tp)
        rtl_hw_start_8125_common(tp);
 }
 
+static void rtl_hw_start_8126a(struct rtl8169_private *tp)
+{
+       rtl_set_def_aspm_entry_latency(tp);
+       rtl_hw_start_8125_common(tp);
+}
+
 static void rtl_hw_config(struct rtl8169_private *tp)
 {
        static const rtl_generic_fct hw_configs[] = {
@@ -3664,6 +3708,7 @@ static void rtl_hw_config(struct rtl8169_private *tp)
                [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117,
                [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2,
                [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b,
+               [RTL_GIGA_MAC_VER_65] = rtl_hw_start_8126a,
        };
 
        if (hw_configs[tp->mac_version])
@@ -3674,9 +3719,23 @@ static void rtl_hw_start_8125(struct rtl8169_private *tp)
 {
        int i;
 
+       RTL_W8(tp, INT_CFG0_8125, 0x00);
+
        /* disable interrupt coalescing */
-       for (i = 0xa00; i < 0xb00; i += 4)
-               RTL_W32(tp, i, 0);
+       switch (tp->mac_version) {
+       case RTL_GIGA_MAC_VER_61:
+               for (i = 0xa00; i < 0xb00; i += 4)
+                       RTL_W32(tp, i, 0);
+               break;
+       case RTL_GIGA_MAC_VER_63:
+       case RTL_GIGA_MAC_VER_65:
+               for (i = 0xa00; i < 0xa80; i += 4)
+                       RTL_W32(tp, i, 0);
+               RTL_W16(tp, INT_CFG1_8125, 0x0000);
+               break;
+       default:
+               break;
+       }
 
        rtl_hw_config(tp);
 }
@@ -3754,8 +3813,7 @@ static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
        rtl_jumbo_config(tp);
 
        switch (tp->mac_version) {
-       case RTL_GIGA_MAC_VER_61:
-       case RTL_GIGA_MAC_VER_63:
+       case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_65:
                rtl8125_set_eee_txidle_timer(tp);
                break;
        default:
@@ -3904,7 +3962,7 @@ static void rtl8169_cleanup(struct rtl8169_private *tp)
                RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
                rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
                break;
-       case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
+       case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65:
                rtl_enable_rxdvgate(tp);
                fsleep(2000);
                break;
@@ -4055,8 +4113,7 @@ static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp,
 
        switch (tp->mac_version) {
        case RTL_GIGA_MAC_VER_34:
-       case RTL_GIGA_MAC_VER_61:
-       case RTL_GIGA_MAC_VER_63:
+       case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_65:
                padto = max_t(unsigned int, padto, ETH_ZLEN);
                break;
        default:
@@ -5085,7 +5142,7 @@ static void rtl_hw_initialize(struct rtl8169_private *tp)
        case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
                rtl_hw_init_8168g(tp);
                break;
-       case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63:
+       case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_65:
                rtl_hw_init_8125(tp);
                break;
        default:

diff --git a/drivers/net/ethernet/realtek/r8169_phy_config.c b/drivers/net/ethernet/realtek/r8169_phy_config.c
index b50f16786c246abbe25553103ae699f7e5f10592..1f74317beb88788f4fcf7a598befea12b8da3be3 100644 (file)
--- a/drivers/net/ethernet/realtek/r8169_phy_config.c
+++ b/drivers/net/ethernet/realtek/r8169_phy_config.c
@@ -1102,6 +1102,12 @@ static void rtl8125b_hw_phy_config(struct rtl8169_private *tp,
        rtl8125b_config_eee_phy(phydev);
 }
 
+static void rtl8126a_hw_phy_config(struct rtl8169_private *tp,
+                                  struct phy_device *phydev)
+{
+       r8169_apply_firmware(tp);
+}
+
 void r8169_hw_phy_config(struct rtl8169_private *tp, struct phy_device *phydev,
                         enum mac_version ver)
 {
@@ -1152,6 +1158,7 @@ void r8169_hw_phy_config(struct rtl8169_private *tp, struct phy_device *phydev,
                [RTL_GIGA_MAC_VER_53] = rtl8117_hw_phy_config,
                [RTL_GIGA_MAC_VER_61] = rtl8125a_2_hw_phy_config,
                [RTL_GIGA_MAC_VER_63] = rtl8125b_hw_phy_config,
+               [RTL_GIGA_MAC_VER_65] = rtl8126a_hw_phy_config,
        };
 
        if (phy_configs[ver])