arm64: dts: ti: k3-j721e-evm: Add overlay for PCIE0 Endpoint Mode

Add overlay to enable the PCIE0 instance of PCIe on J721E-EVM in
Endpoint mode of operation.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20231211115535.1264353-2-s-vadapalli@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index 1ac47876bc99e1bcf7c1bdc27dea4ea93629043b..c6606b7678a34abad85670168ca070fa16079729 100644 (file)
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -67,6 +67,7 @@ k3-j721e-evm-dtbs := k3-j721e-common-proc-board.dtb k3-j721e-evm-quad-port-eth-e
 dtb-$(CONFIG_ARCH_K3) += k3-j721e-beagleboneai64.dtb
 dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm.dtb
 dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-gesi-exp-board.dtbo
+dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-pcie0-ep.dtbo
 dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk.dtb
 
 # Boards with J721s2 SoC
@@ -103,6 +104,8 @@ k3-am642-tqma64xxl-mbax4xxl-sdcard-dtbs := \
        k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo
 k3-am642-tqma64xxl-mbax4xxl-wlan-dtbs := \
        k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-wlan.dtbo
+k3-j721e-evm-pcie0-ep-dtbs := k3-j721e-common-proc-board.dtb \
+       k3-j721e-evm-pcie0-ep.dtbo
 dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
        k3-am625-beagleplay-csi2-tevi-ov5640.dtb \
        k3-am625-sk-csi2-imx219.dtb \
@@ -113,7 +116,8 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
        k3-am62a7-sk-csi2-imx219.dtb \
        k3-am62a7-sk-csi2-ov5640.dtb \
        k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb \
-       k3-am642-tqma64xxl-mbax4xxl-wlan.dtb
+       k3-am642-tqma64xxl-mbax4xxl-wlan.dtb \
+       k3-j721e-evm-pcie0-ep.dtb
 
 # Enable support for device-tree overlays
 DTC_FLAGS_k3-am625-beagleplay += -@

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso b/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso
new file mode 100644 (file)
index 0000000..0c82a13
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0
+/**
+ * DT Overlay for enabling PCIE0 instance in Endpoint Configuration with the
+ * J7 common processor board.
+ *
+ * J7 Common Processor Board Product Link: https://www.ti.com/tool/J721EXCPXEVM
+ *
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+#include "k3-pinctrl.h"
+
+/*
+ * Since Root Complex and Endpoint modes are mutually exclusive
+ * disable Root Complex mode.
+ */
+&pcie0_rc {
+       status = "disabled";
+};
+
+&cbass_main {
+       #address-cells = <2>;
+       #size-cells = <2>;
+       interrupt-parent = <&gic500>;
+
+       pcie0_ep: pcie-ep@2900000 {
+               compatible = "ti,j721e-pcie-ep";
+               reg = <0x00 0x02900000 0x00 0x1000>,
+                     <0x00 0x02907000 0x00 0x400>,
+                     <0x00 0x0d000000 0x00 0x00800000>,
+                     <0x00 0x10000000 0x00 0x08000000>;
+               reg-names = "intd_cfg", "user_cfg", "reg", "mem";
+               interrupt-names = "link_state";
+               interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
+               ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
+               max-link-speed = <3>;
+               num-lanes = <1>;
+               power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 239 1>;
+               clock-names = "fck";
+               max-functions = /bits/ 8 <6>;
+               max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
+               dma-coherent;
+               phys = <&serdes0_pcie_link>;
+               phy-names = "pcie-phy";
+       };
+};