clk: renesas: r8a779g0: Add TPU clock

Add the module clock used by the 16-Bit Timer Pulse Unit (TPU) on the
Renesas R-Car V4H (R8A779G0) SoC.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/f2c1e2c5411b7bd6af726e6baf6e1efc354a7cdf.1665147497.git.geert+renesas@glider.be

diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
index 1215b6f516ea40c9500c596301457461bea0720d..5cc5ee1295d9fe68f87af100fd931e95dee9121d 100644 (file)
--- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
@@ -182,6 +182,7 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
        DEF_MOD("scif4",        705,    R8A779G0_CLK_SASYNCPERD4),
        DEF_MOD("sydm0",        709,    R8A779G0_CLK_S0D6_PER),
        DEF_MOD("sydm1",        710,    R8A779G0_CLK_S0D6_PER),
+       DEF_MOD("tpu0",         718,    R8A779G0_CLK_SASYNCPERD4),
        DEF_MOD("wdt1:wdt0",    907,    R8A779G0_CLK_R),
        DEF_MOD("pfc0",         915,    R8A779G0_CLK_CL16M),
        DEF_MOD("pfc1",         916,    R8A779G0_CLK_CL16M),