drm/amd/display: Initialize necessary uninitialized variables

This commit initializes uninitialized variables.
For some compilers uninitialized variable warnings are treated as Error.

Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Acked-by: Alan Liu <haoping.liu@amd.com>
Signed-off-by: Meera Patel <meera.patel@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index cb992aca760dc4690da4b6c348a045be6cd0733e..0701d03b88a9cee10612c751d2e6c235e67f4cc6 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -297,7 +297,7 @@ void dcn32_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
 
        clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;
        for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
-               int dpp_inst, dppclk_khz, prev_dppclk_khz;
+               int dpp_inst = 0, dppclk_khz, prev_dppclk_khz;
 
                dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
 

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 2d8a8c8ff47d4e300fe0aa3703047ef5f1abd0a9..4284a3609e9852b90bceeb2d806f24f8fbc8f5f0 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -4090,9 +4090,9 @@ static bool commit_minimal_transition_state(struct dc *dc,
                struct dc_state *transition_base_context)
 {
        struct dc_state *transition_context = dc_create_state(dc);
-       enum pipe_split_policy tmp_mpc_policy;
-       bool temp_dynamic_odm_policy;
-       bool temp_subvp_policy;
+       enum pipe_split_policy tmp_mpc_policy = 0;
+       bool temp_dynamic_odm_policy = 0;
+       bool temp_subvp_policy = 0;
        enum dc_status ret = DC_ERROR_UNEXPECTED;
        unsigned int i, j;
        unsigned int pipe_in_use = 0;
@@ -4372,8 +4372,8 @@ bool dc_update_planes_and_stream(struct dc *dc,
         * cause underflow. Apply stream configuration with minimal pipe
         * split first to avoid unsupported transitions for active pipes.
         */
-       bool force_minimal_pipe_splitting;
-       bool is_plane_addition;
+       bool force_minimal_pipe_splitting = 0;
+       bool is_plane_addition = 0;
 
        populate_fast_updates(fast_update, srf_updates, surface_count, stream_update);
        force_minimal_pipe_splitting = could_mpcc_tree_change_for_active_pipes(

diff --git a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
index df3a438abda82c9f433696d930fa58e76e00a012..2e3fa0fb8bd490a25d3c187175bf441038eb720f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
@@ -1659,7 +1659,7 @@ static int dcn315_populate_dml_pipes_from_context(
 {
        int i, pipe_cnt, crb_idx, crb_pipes;
        struct resource_context *res_ctx = &context->res_ctx;
-       struct pipe_ctx *pipe;
+       struct pipe_ctx *pipe = NULL;
        const int max_usable_det = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - DCN3_15_MIN_COMPBUF_SIZE_KB;
        int remaining_det_segs = max_usable_det / DCN3_15_CRB_SEGMENT_SIZE_KB;
        bool pixel_rate_crb = allow_pixel_rate_crb(dc, context);

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index 1cc09799f92d386ca338fa5a1cd77d63dfc28c7a..0d1f18f8348e5934527ac655997e00f647b7e4c1 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -1892,7 +1892,7 @@ int dcn32_populate_dml_pipes_from_context(
 {
        int i, pipe_cnt;
        struct resource_context *res_ctx = &context->res_ctx;
-       struct pipe_ctx *pipe;
+       struct pipe_ctx *pipe = NULL;
        bool subvp_in_use = false;
        struct dc_crtc_timing *timing;
        bool vsr_odm_support = false;

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
index f294f2f8c75bcf6dd102ab6ac199b96e5a9a0c10..57cf0358cc438516eb81d0dfc6bbbbf9ff8e9009 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
@@ -3194,7 +3194,7 @@ static void CalculateFlipSchedule(
        unsigned int HostVMDynamicLevels;
        double TimeForFetchingMetaPTEImmediateFlip;
        double TimeForFetchingRowInVBlankImmediateFlip;
-       double ImmediateFlipBW;
+       double ImmediateFlipBW = 1.0;
        double HostVMInefficiencyFactor;
        double VRatioClamped;
 

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
index 43016c462251f48a9d85d4a6a2f3134263c61cb7..eba51144fee75f6e53bbb8d9ab5c454c619e60cb 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
@@ -3505,7 +3505,7 @@ static void CalculateFlipSchedule(
        unsigned int HostVMDynamicLevelsTrips;
        double TimeForFetchingMetaPTEImmediateFlip;
        double TimeForFetchingRowInVBlankImmediateFlip;
-       double ImmediateFlipBW;
+       double ImmediateFlipBW = 1.0;
        double LineTime = v->HTotal[k] / v->PixelClock[k];
 
        if (v->GPUVMEnable == true && v->HostVMEnable == true) {

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
index 9010c47476e923e6f8d1f95aca7de12fe9e47165..32251af76935d1d41a204b0906530a060d444bb7 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
@@ -3613,7 +3613,7 @@ static void CalculateFlipSchedule(
        unsigned int HostVMDynamicLevelsTrips;
        double TimeForFetchingMetaPTEImmediateFlip;
        double TimeForFetchingRowInVBlankImmediateFlip;
-       double ImmediateFlipBW;
+       double ImmediateFlipBW = 1.0;
        double LineTime = v->HTotal[k] / v->PixelClock[k];
 
        if (v->GPUVMEnable == true && v->HostVMEnable == true) {

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
index a50e7f4dce4215f1b5f537186f9185dbd7f146b6..890797ecf0f9118394cf3eb0198147164aee8516 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
@@ -4124,7 +4124,7 @@ void dml32_CalculateFlipSchedule(
        unsigned int HostVMDynamicLevelsTrips;
        double TimeForFetchingMetaPTEImmediateFlip;
        double TimeForFetchingRowInVBlankImmediateFlip;
-       double ImmediateFlipBW;
+       double ImmediateFlipBW = 1.0;
 
        if (GPUVMEnable == true && HostVMEnable == true)
                HostVMDynamicLevelsTrips = HostVMMaxNonCachedPageTableLevels;