crypto: qat - store the ring-to-service mapping

This driver relies on either the FW (on the PF) or the PF (on the VF) to
know how crypto services and rings map to one another. Store this
information so that it can be referenced in the future at runtime for
checks or extensions.

Signed-off-by: Marco Chiappero <marco.chiappero@intel.com>
Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Reviewed-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

diff --git a/drivers/crypto/qat/qat_4xxx/adf_4xxx_hw_data.c b/drivers/crypto/qat/qat_4xxx/adf_4xxx_hw_data.c
index 0d1603894af440b87bd452f8ce9aabb253ecbc70..67cd20f443ab4b5b26033de7af869629e97b5563 100644 (file)
--- a/drivers/crypto/qat/qat_4xxx/adf_4xxx_hw_data.c
+++ b/drivers/crypto/qat/qat_4xxx/adf_4xxx_hw_data.c
@@ -246,6 +246,7 @@ void adf_init_hw_data_4xxx(struct adf_hw_device_data *hw_data)
        hw_data->num_logical_accel = 1;
        hw_data->tx_rx_gap = ADF_4XXX_RX_RINGS_OFFSET;
        hw_data->tx_rings_mask = ADF_4XXX_TX_RINGS_MASK;
+       hw_data->ring_to_svc_map = ADF_GEN4_DEFAULT_RING_TO_SRV_MAP;
        hw_data->alloc_irq = adf_isr_resource_alloc;
        hw_data->free_irq = adf_isr_resource_free;
        hw_data->enable_error_correction = adf_enable_error_correction;

diff --git a/drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c b/drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c
index 3987a44fa164b6789246fb5ec988074bfcd1ea44..b941fe3713ff15a963f864a772e9ff28d7d23e32 100644 (file)
--- a/drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c
+++ b/drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c
@@ -109,6 +109,7 @@ void adf_init_hw_data_c3xxx(struct adf_hw_device_data *hw_data)
        hw_data->num_engines = ADF_C3XXX_MAX_ACCELENGINES;
        hw_data->tx_rx_gap = ADF_GEN2_RX_RINGS_OFFSET;
        hw_data->tx_rings_mask = ADF_GEN2_TX_RINGS_MASK;
+       hw_data->ring_to_svc_map = ADF_GEN2_DEFAULT_RING_TO_SRV_MAP;
        hw_data->alloc_irq = adf_isr_resource_alloc;
        hw_data->free_irq = adf_isr_resource_free;
        hw_data->enable_error_correction = adf_gen2_enable_error_correction;

diff --git a/drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c b/drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c
index 85122013534de1a1e64b6f7df79ffd21d919ebf2..a9fbe57b32ae35631a205604d3796604388a9ace 100644 (file)
--- a/drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c
+++ b/drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c
@@ -67,6 +67,7 @@ void adf_init_hw_data_c3xxxiov(struct adf_hw_device_data *hw_data)
        hw_data->num_engines = ADF_C3XXXIOV_MAX_ACCELENGINES;
        hw_data->tx_rx_gap = ADF_C3XXXIOV_RX_RINGS_OFFSET;
        hw_data->tx_rings_mask = ADF_C3XXXIOV_TX_RINGS_MASK;
+       hw_data->ring_to_svc_map = ADF_GEN2_DEFAULT_RING_TO_SRV_MAP;
        hw_data->alloc_irq = adf_vf_isr_resource_alloc;
        hw_data->free_irq = adf_vf_isr_resource_free;
        hw_data->enable_error_correction = adf_vf_void_noop;

diff --git a/drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c b/drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c
index a76e33d7a215ac344a1326a59992ad836e0a6293..b1eac2f81faa7be522b4c2a39911ba41702fc07c 100644 (file)
--- a/drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c
+++ b/drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c
@@ -111,6 +111,7 @@ void adf_init_hw_data_c62x(struct adf_hw_device_data *hw_data)
        hw_data->num_engines = ADF_C62X_MAX_ACCELENGINES;
        hw_data->tx_rx_gap = ADF_GEN2_RX_RINGS_OFFSET;
        hw_data->tx_rings_mask = ADF_GEN2_TX_RINGS_MASK;
+       hw_data->ring_to_svc_map = ADF_GEN2_DEFAULT_RING_TO_SRV_MAP;
        hw_data->alloc_irq = adf_isr_resource_alloc;
        hw_data->free_irq = adf_isr_resource_free;
        hw_data->enable_error_correction = adf_gen2_enable_error_correction;

diff --git a/drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c b/drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c
index 99c56405f88fb51368c0dc79452fee21aaf63250..0282038fca54893c93387007a0d24f83a63de912 100644 (file)
--- a/drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c
+++ b/drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c
@@ -67,6 +67,7 @@ void adf_init_hw_data_c62xiov(struct adf_hw_device_data *hw_data)
        hw_data->num_engines = ADF_C62XIOV_MAX_ACCELENGINES;
        hw_data->tx_rx_gap = ADF_C62XIOV_RX_RINGS_OFFSET;
        hw_data->tx_rings_mask = ADF_C62XIOV_TX_RINGS_MASK;
+       hw_data->ring_to_svc_map = ADF_GEN2_DEFAULT_RING_TO_SRV_MAP;
        hw_data->alloc_irq = adf_vf_isr_resource_alloc;
        hw_data->free_irq = adf_vf_isr_resource_free;
        hw_data->enable_error_correction = adf_vf_void_noop;

diff --git a/drivers/crypto/qat/qat_common/adf_accel_devices.h b/drivers/crypto/qat/qat_common/adf_accel_devices.h
index 1fb32f3e78df61fc718864907f8790a8ea13c21e..59f06e53d316bb2bf847b60f6be1f09ed42e7a21 100644 (file)
--- a/drivers/crypto/qat/qat_common/adf_accel_devices.h
+++ b/drivers/crypto/qat/qat_common/adf_accel_devices.h
@@ -208,6 +208,7 @@ struct adf_hw_device_data {
        u32 ae_mask;
        u32 admin_ae_mask;
        u16 tx_rings_mask;
+       u16 ring_to_svc_map;
        u8 tx_rx_gap;
        u8 num_banks;
        u16 num_banks_per_vf;
@@ -224,12 +225,19 @@ struct adf_hw_device_data {
 /* CSR read macro */
 #define ADF_CSR_RD(csr_base, csr_offset) __raw_readl(csr_base + csr_offset)
 
+#define ADF_CFG_NUM_SERVICES   4
+#define ADF_SRV_TYPE_BIT_LEN   3
+#define ADF_SRV_TYPE_MASK      0x7
+
 #define GET_DEV(accel_dev) ((accel_dev)->accel_pci_dev.pci_dev->dev)
 #define GET_BARS(accel_dev) ((accel_dev)->accel_pci_dev.pci_bars)
 #define GET_HW_DATA(accel_dev) (accel_dev->hw_device)
 #define GET_MAX_BANKS(accel_dev) (GET_HW_DATA(accel_dev)->num_banks)
 #define GET_NUM_RINGS_PER_BANK(accel_dev) \
        GET_HW_DATA(accel_dev)->num_rings_per_bank
+#define GET_SRV_TYPE(accel_dev, idx) \
+       (((GET_HW_DATA(accel_dev)->ring_to_svc_map) >> (ADF_SRV_TYPE_BIT_LEN * (idx))) \
+       & ADF_SRV_TYPE_MASK)
 #define GET_MAX_ACCELENGINES(accel_dev) (GET_HW_DATA(accel_dev)->num_engines)
 #define GET_CSR_OPS(accel_dev) (&(accel_dev)->hw_device->csr_ops)
 #define GET_PFVF_OPS(accel_dev) (&(accel_dev)->hw_device->pfvf_ops)

diff --git a/drivers/crypto/qat/qat_common/adf_cfg_common.h b/drivers/crypto/qat/qat_common/adf_cfg_common.h
index 4fabb70b1f180c61c5aea19484f2f08899dfb254..6e5de1dab97b4f3402fee40d62dbfc1ba9f1443f 100644 (file)
--- a/drivers/crypto/qat/qat_common/adf_cfg_common.h
+++ b/drivers/crypto/qat/qat_common/adf_cfg_common.h
@@ -19,6 +19,19 @@
 #define ADF_MAX_DEVICES (32 * 32)
 #define ADF_DEVS_ARRAY_SIZE BITS_TO_LONGS(ADF_MAX_DEVICES)
 
+#define ADF_CFG_SERV_RING_PAIR_0_SHIFT 0
+#define ADF_CFG_SERV_RING_PAIR_1_SHIFT 3
+#define ADF_CFG_SERV_RING_PAIR_2_SHIFT 6
+#define ADF_CFG_SERV_RING_PAIR_3_SHIFT 9
+enum adf_cfg_service_type {
+       UNUSED = 0,
+       CRYPTO,
+       COMP,
+       SYM,
+       ASYM,
+       USED
+};
+
 enum adf_cfg_val_type {
        ADF_DEC,
        ADF_HEX,

diff --git a/drivers/crypto/qat/qat_common/adf_gen2_hw_data.h b/drivers/crypto/qat/qat_common/adf_gen2_hw_data.h
index 7c2c1736646096d6bcbb62a32924baa15396dd2c..f2e0451b11c087678b59d1fba7c7eb150210bacf 100644 (file)
--- a/drivers/crypto/qat/qat_common/adf_gen2_hw_data.h
+++ b/drivers/crypto/qat/qat_common/adf_gen2_hw_data.h
@@ -4,6 +4,7 @@
 #define ADF_GEN2_HW_DATA_H_
 
 #include "adf_accel_devices.h"
+#include "adf_cfg_common.h"
 
 /* Transport access */
 #define ADF_BANK_INT_SRC_SEL_MASK_0    0x4444444CUL
@@ -116,6 +117,13 @@ do { \
 #define ADF_POWERGATE_DC               BIT(23)
 #define ADF_POWERGATE_PKE              BIT(24)
 
+/* Default ring mapping */
+#define ADF_GEN2_DEFAULT_RING_TO_SRV_MAP \
+       (CRYPTO << ADF_CFG_SERV_RING_PAIR_0_SHIFT | \
+        CRYPTO << ADF_CFG_SERV_RING_PAIR_1_SHIFT | \
+        UNUSED << ADF_CFG_SERV_RING_PAIR_2_SHIFT | \
+          COMP << ADF_CFG_SERV_RING_PAIR_3_SHIFT)
+
 /* WDT timers
  *
  * Timeout is in cycles. Clock speed may vary across products but this

diff --git a/drivers/crypto/qat/qat_common/adf_gen4_hw_data.h b/drivers/crypto/qat/qat_common/adf_gen4_hw_data.h
index 449d6a5976a9d55478c045f515ddceaaeb04db64..f0f71ca44ca364e38ba48935b50f5ce7511619b4 100644 (file)
--- a/drivers/crypto/qat/qat_common/adf_gen4_hw_data.h
+++ b/drivers/crypto/qat/qat_common/adf_gen4_hw_data.h
@@ -4,6 +4,7 @@
 #define ADF_GEN4_HW_CSR_DATA_H_
 
 #include "adf_accel_devices.h"
+#include "adf_cfg_common.h"
 
 /* Transport access */
 #define ADF_BANK_INT_SRC_SEL_MASK      0x44UL
@@ -94,6 +95,13 @@ do { \
                   ADF_RING_BUNDLE_SIZE * (bank) + \
                   ADF_RING_CSR_RING_SRV_ARB_EN, (value))
 
+/* Default ring mapping */
+#define ADF_GEN4_DEFAULT_RING_TO_SRV_MAP \
+       (ASYM << ADF_CFG_SERV_RING_PAIR_0_SHIFT | \
+         SYM << ADF_CFG_SERV_RING_PAIR_1_SHIFT | \
+        ASYM << ADF_CFG_SERV_RING_PAIR_2_SHIFT | \
+         SYM << ADF_CFG_SERV_RING_PAIR_3_SHIFT)
+
 /* WDT timers
  *
  * Timeout is in cycles. Clock speed may vary across products but this

diff --git a/drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c b/drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c
index 2d18279191d7ef80059335ce0674e7635e12faa9..09599fe4d2f3f04b533cfa4029a60c0363961d16 100644 (file)
--- a/drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c
+++ b/drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c
@@ -191,6 +191,7 @@ void adf_init_hw_data_dh895xcc(struct adf_hw_device_data *hw_data)
        hw_data->num_engines = ADF_DH895XCC_MAX_ACCELENGINES;
        hw_data->tx_rx_gap = ADF_GEN2_RX_RINGS_OFFSET;
        hw_data->tx_rings_mask = ADF_GEN2_TX_RINGS_MASK;
+       hw_data->ring_to_svc_map = ADF_GEN2_DEFAULT_RING_TO_SRV_MAP;
        hw_data->alloc_irq = adf_isr_resource_alloc;
        hw_data->free_irq = adf_isr_resource_free;
        hw_data->enable_error_correction = adf_gen2_enable_error_correction;

diff --git a/drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c b/drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c
index 5489d6c0225619699719176f97836b912ec3768e..31c14d7e1c115d00414388df60ab6a8605ba1e09 100644 (file)
--- a/drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c
+++ b/drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c
@@ -67,6 +67,7 @@ void adf_init_hw_data_dh895xcciov(struct adf_hw_device_data *hw_data)
        hw_data->num_engines = ADF_DH895XCCIOV_MAX_ACCELENGINES;
        hw_data->tx_rx_gap = ADF_DH895XCCIOV_RX_RINGS_OFFSET;
        hw_data->tx_rings_mask = ADF_DH895XCCIOV_TX_RINGS_MASK;
+       hw_data->ring_to_svc_map = ADF_GEN2_DEFAULT_RING_TO_SRV_MAP;
        hw_data->alloc_irq = adf_vf_isr_resource_alloc;
        hw_data->free_irq = adf_vf_isr_resource_free;
        hw_data->enable_error_correction = adf_vf_void_noop;