drm/amd/display: update GSP1 generic info packet for PSRSU
authorDavid Zhang <dingchen.zhang@amd.com>
Fri, 29 Apr 2022 21:32:56 +0000 (17:32 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 6 Jun 2022 18:40:51 +0000 (14:40 -0400)
[why & how]
Based on PSRSU specification, every selective update frame need to use
two SDP to indicate the frame active range. So we occupy another GSP1
for PSRSU execution.

Signed-off-by: David Zhang <dingchen.zhang@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c

index b683ad8171067adb5f8d465fbca080fc6c37b44f..1a26ce87c16e3cadfcdb9997cb951a351e49954c 100644 (file)
@@ -419,6 +419,21 @@ void enc3_stream_encoder_update_dp_info_packets(
                                &info_frame->vsc,
                                true);
        }
+       /* TODO: VSC SDP at packetIndex 1 should be restricted only if PSR-SU on.
+        * There should have another Infopacket type (e.g. vsc_psrsu) for PSR_SU.
+        * In addition, currently the driver check the valid bit then update and
+        * send the corresponding Infopacket. For PSR-SU, the SDP only be sent
+        * while entering PSR-SU mode. So we need another parameter(e.g. send)
+        * in dc_info_packet to indicate which infopacket should be enabled by
+        * default here.
+        */
+       if (info_frame->vsc.valid) {
+               enc->vpg->funcs->update_generic_info_packet(
+                               enc->vpg,
+                               1,  /* packetIndex */
+                               &info_frame->vsc,
+                               true);
+       }
        if (info_frame->spd.valid) {
                enc->vpg->funcs->update_generic_info_packet(
                                enc->vpg,