}
 
        if (intel_phy_is_snps(dev_priv, phy) &&
-           dev_priv->snps_phy_failed_calibration & BIT(phy)) {
+           dev_priv->display.snps.phy_failed_calibration & BIT(phy)) {
                drm_dbg_kms(&dev_priv->drm,
                            "SNPS PHY %c failed to calibrate, proceeding anyway\n",
                            phy_name(phy));
 
                u32 block_time_us;
        } sagv;
 
+       struct {
+               /*
+                * DG2: Mask of PHYs that were not calibrated by the firmware
+                * and should not be used.
+                */
+               u8 phy_failed_calibration;
+       } snps;
+
        struct {
                /* ordered wq for modesets */
                struct workqueue_struct *modeset;
 
                 */
                if (intel_de_wait_for_clear(i915, DG2_PHY_MISC(phy),
                                            DG2_PHY_DP_TX_ACK_MASK, 25))
-                       i915->snps_phy_failed_calibration |= BIT(phy);
+                       i915->display.snps.phy_failed_calibration |= BIT(phy);
        }
 }
 
 
 
        bool irq_enabled;
 
-       /*
-        * DG2: Mask of PHYs that were not calibrated by the firmware
-        * and should not be used.
-        */
-       u8 snps_phy_failed_calibration;
-
        struct i915_pmu pmu;
 
        struct i915_drm_clients clients;