drm/i915/gt: skip WA verification for GEN7_MISCCPCTL on DG2

Some DG2 firmware locks this register for modification. Using wa_add
with read_mask 0 allows to skip checks of such registers.

Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8945
Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230912073521.2106162-1-andrzej.hajda@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index e950efc75983ef36559e4510a2aaf7f22a2113d0..fcde2e1562ab8c70eab764322f92b6d43f0985f9 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1596,8 +1596,12 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
        /* Wa_14014830051:dg2 */
        wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
 
-       /* Wa_14015795083 */
-       wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
+       /*
+        * Wa_14015795083
+        * Skip verification for possibly locked register.
+        */
+       wa_add(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE,
+              0, 0, false);
 
        /* Wa_18018781329 */
        wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);