#undef DEBUG_PUV3
#include "hw/unicore32/puv3.h"
#include "qemu/module.h"
+#include "qemu/log.h"
#define PUV3_DMA_CH_NR (6)
#define PUV3_DMA_CH_MASK (0xff)
ret = s->reg_CFG[PUV3_DMA_CH(offset)];
break;
default:
- DPRINTF("Bad offset 0x%x\n", offset);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
+ __func__, offset);
}
DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
s->reg_CFG[PUV3_DMA_CH(offset)] = value;
break;
default:
- DPRINTF("Bad offset 0x%x\n", offset);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
+ __func__, offset);
}
DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
}
#undef DEBUG_PUV3
#include "hw/unicore32/puv3.h"
#include "qemu/module.h"
+#include "qemu/log.h"
#define TYPE_PUV3_GPIO "puv3_gpio"
#define PUV3_GPIO(obj) OBJECT_CHECK(PUV3GPIOState, (obj), TYPE_PUV3_GPIO)
ret = s->reg_GPIR;
break;
default:
- DPRINTF("Bad offset 0x%x\n", offset);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
+ __func__, offset);
}
DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
if (s->reg_GPDR & value) {
s->reg_GPLR |= value;
} else {
- DPRINTF("Write gpio input port error!");
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Write gpio input port\n",
+ __func__);
}
break;
case 0x0c:
if (s->reg_GPDR & value) {
s->reg_GPLR &= ~value;
} else {
- DPRINTF("Write gpio input port error!");
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Write gpio input port\n",
+ __func__);
}
break;
case 0x10: /* GRER */
s->reg_GPIR = value;
break;
default:
- DPRINTF("Bad offset 0x%x\n", offset);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
+ __func__, offset);
}
}
#undef DEBUG_PUV3
#include "hw/unicore32/puv3.h"
#include "qemu/module.h"
+#include "qemu/log.h"
#define TYPE_PUV3_INTC "puv3_intc"
#define PUV3_INTC(obj) OBJECT_CHECK(PUV3INTCState, (obj), TYPE_PUV3_INTC)
ret = s->reg_ICPR; /* the same value with ICPR */
break;
default:
- DPRINTF("Bad offset %x\n", (int)offset);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
+ __func__, offset);
}
DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
return ret;
s->reg_ICMR = value;
break;
default:
- DPRINTF("Bad offset 0x%x\n", (int)offset);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
+ __func__, offset);
return;
}
puv3_intc_update(s);
#undef DEBUG_PUV3
#include "hw/unicore32/puv3.h"
#include "qemu/module.h"
+#include "qemu/log.h"
#define TYPE_PUV3_PM "puv3_pm"
#define PUV3_PM(obj) OBJECT_CHECK(PUV3PMState, (obj), TYPE_PUV3_PM)
ret = 0x7;
break;
default:
- DPRINTF("Bad offset 0x%x\n", offset);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
+ __func__, offset);
}
DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
case 0x38:
break;
default:
- DPRINTF("Bad offset 0x%x\n", offset);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
+ __func__, offset);
}
DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
}
#include "hw/irq.h"
#include "hw/ptimer.h"
#include "qemu/module.h"
+#include "qemu/log.h"
#undef DEBUG_PUV3
#include "hw/unicore32/puv3.h"
ret = s->reg_OIER;
break;
default:
- DPRINTF("Bad offset %x\n", (int)offset);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
+ __func__, offset);
}
DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
return ret;
s->reg_OIER = value;
break;
default:
- DPRINTF("Bad offset %x\n", (int)offset);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
+ __func__, offset);
}
}
#include "hw/boards.h"
#include "hw/loader.h"
#include "sysemu/qtest.h"
-
-#undef DEBUG_PUV3
#include "hw/unicore32/puv3.h"
#include "hw/input/i8042.h"
#include "hw/irq.h"