arm64: dts: Update cache properties for freescale

The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).

Update the Device Trees accordingly.

Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Chester Lin <clin@suse.com>
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index ac1c3a7e5f7a57114979865d0aa428d181e13842..1b33cabb4e1457dc1f9789d964108679e2905b60 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -46,6 +46,7 @@
 
                l2: l2-cache {
                        compatible = "cache";
+                       cache-level = <2>;
                };
        };
 

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 704f72caddd3bbb93d271052d9f4a4c61b60a0db..b9fd24cdc919beff2e75b0fe0e8d194465a563fb 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -84,6 +84,7 @@
 
                l2: l2-cache {
                        compatible = "cache";
+                       cache-level = <2>;
                };
        };
 

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 3d9e29824bb2113ac1b0db8f95ac124b97ae89b9..a01e3cfec77fb9794d7fd8a61557cac963ad3881 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -79,6 +79,7 @@
 
                l2: l2-cache {
                        compatible = "cache";
+                       cache-level = <2>;
                };
        };
 

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
index a2cadf7571482967f1d0940f7c117be3252eae0b..1e5d76c4d83db04e127d7528b2fddb05de53849a 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -95,18 +95,22 @@
 
        cluster0_l2: l2-cache0 {
                compatible = "cache";
+               cache-level = <2>;
        };
 
        cluster1_l2: l2-cache1 {
                compatible = "cache";
+               cache-level = <2>;
        };
 
        cluster2_l2: l2-cache2 {
                compatible = "cache";
+               cache-level = <2>;
        };
 
        cluster3_l2: l2-cache3 {
                compatible = "cache";
+               cache-level = <2>;
        };
 
        CPU_PW20: cpu-pw20 {

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
index c3dc38188c17ca1aaceb6e349d838842c0a3f7d0..c12c86915ec87df70563100c4ad2011a800cf1fb 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
@@ -95,18 +95,22 @@
 
        cluster0_l2: l2-cache0 {
                compatible = "cache";
+               cache-level = <2>;
        };
 
        cluster1_l2: l2-cache1 {
                compatible = "cache";
+               cache-level = <2>;
        };
 
        cluster2_l2: l2-cache2 {
                compatible = "cache";
+               cache-level = <2>;
        };
 
        cluster3_l2: l2-cache3 {
                compatible = "cache";
+               cache-level = <2>;
        };
 
        CPU_PW20: cpu-pw20 {

diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index 6680fb2a6dc92332eb1340e8073aa79adbbf8e54..e5215ed0975e1a84049a757b4de9e195ae084419 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -300,6 +300,7 @@
 
                cluster0_l2: l2-cache0 {
                        compatible = "cache";
+                       cache-unified;
                        cache-size = <0x100000>;
                        cache-line-size = <64>;
                        cache-sets = <1024>;
@@ -308,6 +309,7 @@
 
                cluster1_l2: l2-cache1 {
                        compatible = "cache";
+                       cache-unified;
                        cache-size = <0x100000>;
                        cache-line-size = <64>;
                        cache-sets = <1024>;
@@ -316,6 +318,7 @@
 
                cluster2_l2: l2-cache2 {
                        compatible = "cache";
+                       cache-unified;
                        cache-size = <0x100000>;
                        cache-line-size = <64>;
                        cache-sets = <1024>;
@@ -324,6 +327,7 @@
 
                cluster3_l2: l2-cache3 {
                        compatible = "cache";
+                       cache-unified;
                        cache-size = <0x100000>;
                        cache-line-size = <64>;
                        cache-sets = <1024>;
@@ -332,6 +336,7 @@
 
                cluster4_l2: l2-cache4 {
                        compatible = "cache";
+                       cache-unified;
                        cache-size = <0x100000>;
                        cache-line-size = <64>;
                        cache-sets = <1024>;
@@ -340,6 +345,7 @@
 
                cluster5_l2: l2-cache5 {
                        compatible = "cache";
+                       cache-unified;
                        cache-size = <0x100000>;
                        cache-line-size = <64>;
                        cache-sets = <1024>;
@@ -348,6 +354,7 @@
 
                cluster6_l2: l2-cache6 {
                        compatible = "cache";
+                       cache-unified;
                        cache-size = <0x100000>;
                        cache-line-size = <64>;
                        cache-sets = <1024>;
@@ -356,6 +363,7 @@
 
                cluster7_l2: l2-cache7 {
                        compatible = "cache";
+                       cache-unified;
                        cache-size = <0x100000>;
                        cache-line-size = <64>;
                        cache-sets = <1024>;

diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
index 9f79504f9d6a6c5b12fdf6e545312a27a752668a..0c64b919462125c65cf81ba1d323f1e996c55436 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
@@ -59,6 +59,7 @@
 
                A35_L2: l2-cache0 {
                        compatible = "cache";
+                       cache-level = <2>;
                };
        };
 

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index ea5feb04a0b7e2e921b9128cd8a79c8dbf95c083..fae0e1a31147b46f3ef5b1b5557386b39f28fd49 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -139,6 +139,7 @@
                A53_L2: l2-cache0 {
                        compatible = "cache";
                        cache-level = <2>;
+                       cache-unified;
                        cache-size = <0x80000>;
                        cache-line-size = <64>;
                        cache-sets = <512>;

diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index fc86e73373135d0ecff80188bd21bc0347779ae2..3c8ff12ab14d9dd01d06e44ae14bd36fa326b47d 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -139,6 +139,7 @@
                A53_L2: l2-cache0 {
                        compatible = "cache";
                        cache-level = <2>;
+                       cache-unified;
                        cache-size = <0x80000>;
                        cache-line-size = <64>;
                        cache-sets = <512>;

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index d7039d9fe61adfe3f9d09cdba701bedcf6ce9ad4..4fc90477b41994484b900b1d0b8a7fe6d0183818 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -123,6 +123,7 @@
 
                A53_L2: l2-cache0 {
                        compatible = "cache";
+                       cache-unified;
                        cache-level = <2>;
                        cache-size = <0x80000>;
                        cache-line-size = <64>;

diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index c6530e5c7fef5b72af226f7b52307434a11a315a..3d25535b43e5f5450244b545d4d5d282cf44c19a 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -179,6 +179,7 @@
                A53_L2: l2-cache0 {
                        compatible = "cache";
                        cache-level = <2>;
+                       cache-unified;
                        cache-size = <0x100000>;
                        cache-line-size = <64>;
                        cache-sets = <1024>;

diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
index c9c2b6536233b1755e8c3c9bf9dd67cef62f8e30..41ce8336f29e413ad69fe1a17638da4dcda60e02 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
@@ -136,6 +136,7 @@
                A53_L2: l2-cache0 {
                        compatible = "cache";
                        cache-level = <2>;
+                       cache-unified;
                        cache-size = <0x100000>;
                        cache-line-size = <64>;
                        cache-sets = <1024>;
@@ -144,6 +145,7 @@
                A72_L2: l2-cache1 {
                        compatible = "cache";
                        cache-level = <2>;
+                       cache-unified;
                        cache-size = <0x100000>;
                        cache-line-size = <64>;
                        cache-sets = <1024>;

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index f4ea18bb95abfe3cbfb336095e221990fd895811..85c0b1d2bac5f3312a41a9cac90a8a13f098be50 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -127,6 +127,7 @@
                A35_L2: l2-cache0 {
                        compatible = "cache";
                        cache-level = <2>;
+                       cache-unified;
                        cache-size = <0x80000>;
                        cache-line-size = <64>;
                        cache-sets = <1024>;

diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
index 06ce5f19aa8aacbbcc3d8562d0f2a73fcde49e1d..32193a43ff49da7e76ed6ac329070a74613d966b 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
@@ -51,6 +51,7 @@
 
                A35_L2: l2-cache0 {
                        compatible = "cache";
+                       cache-level = <2>;
                };
        };
 

diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index 824d401e7a2c5325299c8ce3b90303f4162382ac..d8c82da88ca070f5e389b7f74ffc06a000870d86 100644 (file)
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -52,10 +52,12 @@
 
                cluster0_l2: l2-cache0 {
                        compatible = "cache";
+                       cache-level = <2>;
                };
 
                cluster1_l2: l2-cache1 {
                        compatible = "cache";
+                       cache-level = <2>;
                };
        };
 

diff --git a/arch/arm64/boot/dts/freescale/s32v234.dtsi b/arch/arm64/boot/dts/freescale/s32v234.dtsi
index ba0b5305d4812c0c572a75994bff59166ce72caf..3e306218d5331a841209d924b6ee926315e7955d 100644 (file)
--- a/arch/arm64/boot/dts/freescale/s32v234.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32v234.dtsi
@@ -61,10 +61,12 @@
 
                cluster0_l2_cache: l2-cache0 {
                        compatible = "cache";
+                       cache-level = <2>;
                };
 
                cluster1_l2_cache: l2-cache1 {
                        compatible = "cache";
+                       cache-level = <2>;
                };
        };