drm/amd/display: reset lane settings after each PHY repeater LT
authorSung Joon Kim <sungkim@amd.com>
Tue, 1 Feb 2022 18:59:02 +0000 (13:59 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 14 Feb 2022 20:08:41 +0000 (15:08 -0500)
[why]
In LTTPR non-transparent mode, we need
to reset the cached lane settings before performing
link training on the next PHY repeater. Otherwise,
the cached lane settings will be used for the next
clock recovery e.g. VS = MAX (3) which should not be
the case according to the DP specs. We expect to use
minimum lane settings on each clock recovery sequence.

[how]
Reset DPCD and HW lane settings on each repeater LT.
Set training pattern to 0 for the repeater that failed LT
at the proper place.

Reviewed-by: Meenakshikumar Somasundaram <Meenakshikumar.Somasundaram@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Sung Joon Kim <sungkim@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

index cd9c31b5e55d395f0d4536edd1d8fefcb4bc0790..d62b59d52ba85a409fdd9eb4924ce78cc9fbbe52 100644 (file)
@@ -2230,22 +2230,27 @@ static enum link_training_result dp_perform_8b_10b_link_training(
                                repeater_id--) {
                        status = perform_clock_recovery_sequence(link, link_res, lt_settings, repeater_id);
 
-                       if (status != LINK_TRAINING_SUCCESS)
+                       if (status != LINK_TRAINING_SUCCESS) {
+                               repeater_training_done(link, repeater_id);
                                break;
+                       }
 
                        status = perform_channel_equalization_sequence(link,
                                        link_res,
                                        lt_settings,
                                        repeater_id);
 
+                       repeater_training_done(link, repeater_id);
+
                        if (status != LINK_TRAINING_SUCCESS)
                                break;
 
-                       repeater_training_done(link, repeater_id);
+                       for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
+                               lt_settings->dpcd_lane_settings[lane].raw = 0;
+                               lt_settings->hw_lane_settings[lane].VOLTAGE_SWING = 0;
+                               lt_settings->hw_lane_settings[lane].PRE_EMPHASIS = 0;
+                       }
                }
-
-               for (lane = 0; lane < (uint8_t)lt_settings->link_settings.lane_count; lane++)
-                       lt_settings->dpcd_lane_settings[lane].raw = 0;
        }
 
        if (status == LINK_TRAINING_SUCCESS) {