crypto: hisilicon/qm - adjust order of device error configuration

In order to avoid reporting an exception but the error type is not
configured, the driver needs to configure the error type first, and then
enable the error interrupt. Before executing the task, hardware error
initialization is needed so that the hardware can detect the error in time.

Signed-off-by: Weili Qian <qianweili@huawei.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

diff --git a/drivers/crypto/hisilicon/hpre/hpre_main.c b/drivers/crypto/hisilicon/hpre/hpre_main.c
index 31515ae054f8ab8ddf9013bc6362228fb4e82bfc..1f47bb5e39902767a6fbbf2cd1130224c18c4eec 100644 (file)
--- a/drivers/crypto/hisilicon/hpre/hpre_main.c
+++ b/drivers/crypto/hisilicon/hpre/hpre_main.c
@@ -466,8 +466,7 @@ static void hpre_hw_error_enable(struct hisi_qm *qm)
        /* clear HPRE hw error source if having */
        writel(HPRE_CORE_INT_DISABLE, qm->io_base + HPRE_HAC_SOURCE_INT);
 
-       /* enable hpre hw error interrupts */
-       writel(HPRE_CORE_INT_ENABLE, qm->io_base + HPRE_INT_MASK);
+       /* configure error type */
        writel(HPRE_HAC_RAS_CE_ENABLE, qm->io_base + HPRE_RAS_CE_ENB);
        writel(HPRE_HAC_RAS_NFE_ENABLE, qm->io_base + HPRE_RAS_NFE_ENB);
        writel(HPRE_HAC_RAS_FE_ENABLE, qm->io_base + HPRE_RAS_FE_ENB);
@@ -476,6 +475,9 @@ static void hpre_hw_error_enable(struct hisi_qm *qm)
        val = readl(qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB);
        val |= HPRE_AM_OOO_SHUTDOWN_ENABLE;
        writel(val, qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB);
+
+       /* enable hpre hw error interrupts */
+       writel(HPRE_CORE_INT_ENABLE, qm->io_base + HPRE_INT_MASK);
 }
 
 static inline struct hisi_qm *hpre_file_to_qm(struct hpre_debugfs_file *file)

diff --git a/drivers/crypto/hisilicon/qm.c b/drivers/crypto/hisilicon/qm.c
index 09f0370881ab8b4a11f26abbb107fb4a5009e8b3..04c09053ea11c82e8320d9b90d6463d341bde140 100644 (file)
--- a/drivers/crypto/hisilicon/qm.c
+++ b/drivers/crypto/hisilicon/qm.c
@@ -3917,6 +3917,7 @@ static int qm_controller_reset_done(struct hisi_qm *qm)
        }
 
        qm_restart_prepare(qm);
+       hisi_qm_dev_err_init(qm);
 
        ret = qm_restart(qm);
        if (ret) {
@@ -3938,7 +3939,6 @@ static int qm_controller_reset_done(struct hisi_qm *qm)
                return -EPERM;
        }
 
-       hisi_qm_dev_err_init(qm);
        qm_restart_done(qm);
 
        clear_bit(QM_RESETTING, &qm->misc_ctl);

diff --git a/drivers/crypto/hisilicon/sec2/sec_main.c b/drivers/crypto/hisilicon/sec2/sec_main.c
index 6f0062d4408c35dcfd0a362f6ba63a9867379be0..e57167da6be0fd97313192f27f6144a08bce4ab8 100644 (file)
--- a/drivers/crypto/hisilicon/sec2/sec_main.c
+++ b/drivers/crypto/hisilicon/sec2/sec_main.c
@@ -440,43 +440,39 @@ static void sec_hw_error_enable(struct hisi_qm *qm)
                return;
        }
 
-       val = readl(qm->io_base + SEC_CONTROL_REG);
-
        /* clear SEC hw error source if having */
        writel(SEC_CORE_INT_CLEAR, qm->io_base + SEC_CORE_INT_SOURCE);
 
-       /* enable SEC hw error interrupts */
-       writel(SEC_CORE_INT_ENABLE, qm->io_base + SEC_CORE_INT_MASK);
-
        /* enable RAS int */
        writel(SEC_RAS_CE_ENB_MSK, qm->io_base + SEC_RAS_CE_REG);
        writel(SEC_RAS_FE_ENB_MSK, qm->io_base + SEC_RAS_FE_REG);
        writel(SEC_RAS_NFE_ENB_MSK, qm->io_base + SEC_RAS_NFE_REG);
 
        /* enable SEC block master OOO when m-bit error occur */
+       val = readl(qm->io_base + SEC_CONTROL_REG);
        val = val | SEC_AXI_SHUTDOWN_ENABLE;
-
        writel(val, qm->io_base + SEC_CONTROL_REG);
+
+       /* enable SEC hw error interrupts */
+       writel(SEC_CORE_INT_ENABLE, qm->io_base + SEC_CORE_INT_MASK);
 }
 
 static void sec_hw_error_disable(struct hisi_qm *qm)
 {
        u32 val;
 
-       val = readl(qm->io_base + SEC_CONTROL_REG);
-
-       /* disable RAS int */
-       writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_CE_REG);
-       writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_FE_REG);
-       writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_NFE_REG);
-
        /* disable SEC hw error interrupts */
        writel(SEC_CORE_INT_DISABLE, qm->io_base + SEC_CORE_INT_MASK);
 
        /* disable SEC block master OOO when m-bit error occur */
+       val = readl(qm->io_base + SEC_CONTROL_REG);
        val = val & SEC_AXI_SHUTDOWN_DISABLE;
-
        writel(val, qm->io_base + SEC_CONTROL_REG);
+
+       /* disable RAS int */
+       writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_CE_REG);
+       writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_FE_REG);
+       writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_NFE_REG);
 }
 
 static u32 sec_clear_enable_read(struct sec_debug_file *file)

diff --git a/drivers/crypto/hisilicon/zip/zip_main.c b/drivers/crypto/hisilicon/zip/zip_main.c
index 2178b40e9f825bcb5114f6f16efc66abca2e9c2d..8e3a52218774a564e20ea634cd3c076efd181c8c 100644 (file)
--- a/drivers/crypto/hisilicon/zip/zip_main.c
+++ b/drivers/crypto/hisilicon/zip/zip_main.c
@@ -333,13 +333,13 @@ static void hisi_zip_hw_error_enable(struct hisi_qm *qm)
        writel(HZIP_CORE_INT_RAS_NFE_ENABLE,
               qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB);
 
-       /* enable ZIP hw error interrupts */
-       writel(0, qm->io_base + HZIP_CORE_INT_MASK_REG);
-
        /* enable ZIP block master OOO when m-bit error occur */
        val = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);
        val = val | HZIP_AXI_SHUTDOWN_ENABLE;
        writel(val, qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);
+
+       /* enable ZIP hw error interrupts */
+       writel(0, qm->io_base + HZIP_CORE_INT_MASK_REG);
 }
 
 static void hisi_zip_hw_error_disable(struct hisi_qm *qm)