drm/amd/pm: drop unnecessary gfxoff controls
authorEvan Quan <evan.quan@amd.com>
Wed, 24 Nov 2021 03:12:31 +0000 (11:12 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 14 Jan 2022 22:51:15 +0000 (17:51 -0500)
Those gfxoff controls added for some specific ASICs are unnecessary.
The functionalities are not affected without them. Also to align with
other ASICs, they should also be dropped.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

index c898ea67354a54b6840231a087d11c8763359144..8895b2b595a4a4b12a33a2e22ea6102810c27ac9 100644 (file)
@@ -1542,8 +1542,6 @@ static int smu_reset(struct smu_context *smu)
        struct amdgpu_device *adev = smu->adev;
        int ret;
 
-       amdgpu_gfx_off_ctrl(smu->adev, false);
-
        ret = smu_hw_fini(adev);
        if (ret)
                return ret;
@@ -1556,8 +1554,6 @@ static int smu_reset(struct smu_context *smu)
        if (ret)
                return ret;
 
-       amdgpu_gfx_off_ctrl(smu->adev, true);
-
        return 0;
 }
 
index efe6b2eff6a0bc896b15202be01e3928518ce7f4..4e37cd8025ed0950bcbf510864f498c41fafb13c 100644 (file)
@@ -1036,10 +1036,6 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
                if (ret)
                        goto print_clk_out;
 
-               /* no need to disable gfxoff when retrieving the current gfxclk */
-               if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
-                       amdgpu_gfx_off_ctrl(adev, false);
-
                ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
                if (ret)
                        goto print_clk_out;
@@ -1168,25 +1164,18 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
        }
 
 print_clk_out:
-       if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
-               amdgpu_gfx_off_ctrl(adev, true);
-
        return size;
 }
 
 static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
                                   enum smu_clk_type clk_type, uint32_t mask)
 {
-       struct amdgpu_device *adev = smu->adev;
        int ret = 0;
        uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
 
        soft_min_level = mask ? (ffs(mask) - 1) : 0;
        soft_max_level = mask ? (fls(mask) - 1) : 0;
 
-       if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
-               amdgpu_gfx_off_ctrl(adev, false);
-
        switch (clk_type) {
        case SMU_GFXCLK:
        case SMU_SCLK:
@@ -1220,9 +1209,6 @@ static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
        }
 
 forec_level_out:
-       if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
-               amdgpu_gfx_off_ctrl(adev, true);
-
        return 0;
 }
 
@@ -1865,16 +1851,7 @@ static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu,
                                enum smu_clk_type clk_type,
                                uint32_t *min, uint32_t *max)
 {
-       struct amdgpu_device *adev = smu->adev;
-       int ret;
-
-       if (clk_type == SMU_GFXCLK)
-               amdgpu_gfx_off_ctrl(adev, false);
-       ret = smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
-       if (clk_type == SMU_GFXCLK)
-               amdgpu_gfx_off_ctrl(adev, true);
-
-       return ret;
+       return smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
 }
 
 static void sienna_cichlid_dump_od_table(struct smu_context *smu,
index e176e6a74f4445ec46b2e02e03286b2a6a2bf54d..9acf2c045a97545f3e8391007cbfa1756151cffc 100644 (file)
@@ -1798,7 +1798,6 @@ int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu,
                                          uint32_t min,
                                          uint32_t max)
 {
-       struct amdgpu_device *adev = smu->adev;
        int ret = 0, clk_id = 0;
        uint32_t param;
 
@@ -1811,9 +1810,6 @@ int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu,
        if (clk_id < 0)
                return clk_id;
 
-       if (clk_type == SMU_GFXCLK)
-               amdgpu_gfx_off_ctrl(adev, false);
-
        if (max > 0) {
                param = (uint32_t)((clk_id << 16) | (max & 0xffff));
                ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
@@ -1831,9 +1827,6 @@ int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu,
        }
 
 out:
-       if (clk_type == SMU_GFXCLK)
-               amdgpu_gfx_off_ctrl(adev, true);
-
        return ret;
 }
 
index f1d7b4900aa1b10473dab9e5dcf90c77c00e592c..f66d8b9135ca1b60c0a0aa4ac388ed42a4cd3306 100644 (file)
@@ -1533,7 +1533,6 @@ int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu,
                                          uint32_t min,
                                          uint32_t max)
 {
-       struct amdgpu_device *adev = smu->adev;
        int ret = 0, clk_id = 0;
        uint32_t param;
 
@@ -1546,9 +1545,6 @@ int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu,
        if (clk_id < 0)
                return clk_id;
 
-       if (clk_type == SMU_GFXCLK)
-               amdgpu_gfx_off_ctrl(adev, false);
-
        if (max > 0) {
                param = (uint32_t)((clk_id << 16) | (max & 0xffff));
                ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
@@ -1566,9 +1562,6 @@ int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu,
        }
 
 out:
-       if (clk_type == SMU_GFXCLK)
-               amdgpu_gfx_off_ctrl(adev, true);
-
        return ret;
 }