--- /dev/null
+# Copyright (C) 2019--2020 Intel Corporation
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
+
+# register rflags
+# - f field LSB MSB rflags
+# - e enum value # after a field
+# - e enum value [LSB MSB]
+# - b bool bit
+# - l arg name min max elsize [discontig...]
+#
+# rflags
+# 8, 16, 32 register bits (default is 8)
+# v1.1 defined in version 1.1
+# f formula
+# float_ireal iReal or IEEE 754; 32 bits
+# ireal unsigned iReal
+
+# general status registers
+module_model_id 0x0000 16
+module_revision_number_major 0x0002 8
+frame_count 0x0005 8
+pixel_order 0x0006 8
+- e GRBG 0
+- e RGGB 1
+- e BGGR 2
+- e GBRG 3
+MIPI_CCS_version 0x0007 8
+- e v1_0 0x10
+- e v1_1 0x11
+- f major 4 7
+- f minor 0 3
+data_pedestal 0x0008 16
+module_manufacturer_id 0x000e 16
+module_revision_number_minor 0x0010 8
+module_date_year 0x0012 8
+module_date_month 0x0013 8
+module_date_day 0x0014 8
+module_date_phase 0x0015 8
+- f 0 2
+- e ts 0
+- e es 1
+- e cs 2
+- e mp 3
+sensor_model_id 0x0016 16
+sensor_revision_number 0x0018 8
+sensor_firmware_version 0x001a 8
+serial_number 0x001c 32
+sensor_manufacturer_id 0x0020 16
+sensor_revision_number_16 0x0022 16
+
+# frame format description registers
+frame_format_model_type 0x0040 8
+- e 2-byte 1
+- e 4-byte 2
+frame_format_model_subtype 0x0041 8
+- f rows 0 3
+- f columns 4 7
+frame_format_descriptor(n) 0x0042 16 f
+- l n 0 14 2
+- f pixels 0 11
+- f pcode 12 15
+- e embedded 1
+- e dummy_pixel 2
+- e black_pixel 3
+- e dark_pixel 4
+- e visible_pixel 5
+- e manuf_specific_0 8
+- e manuf_specific_1 9
+- e manuf_specific_2 10
+- e manuf_specific_3 11
+- e manuf_specific_4 12
+- e manuf_specific_5 13
+- e manuf_specific_6 14
+frame_format_descriptor_4(n) 0x0060 32 f
+- l n 0 7 4
+- f pixels 0 15
+- f pcode 28 31
+- e embedded 1
+- e dummy_pixel 2
+- e black_pixel 3
+- e dark_pixel 4
+- e visible_pixel 5
+- e manuf_specific_0 8
+- e manuf_specific_1 9
+- e manuf_specific_2 10
+- e manuf_specific_3 11
+- e manuf_specific_4 12
+- e manuf_specific_5 13
+- e manuf_specific_6 14
+
+# analog gain description registers
+analog_gain_capability 0x0080 16
+- e global 0
+- e alternate_global 2
+analog_gain_code_min 0x0084 16
+analog_gain_code_max 0x0086 16
+analog_gain_code_step 0x0088 16
+analog_gain_type 0x008a 16
+analog_gain_m0 0x008c 16
+analog_gain_c0 0x008e 16
+analog_gain_m1 0x0090 16
+analog_gain_c1 0x0092 16
+analog_linear_gain_min 0x0094 16 v1.1
+analog_linear_gain_max 0x0096 16 v1.1
+analog_linear_gain_step_size 0x0098 16 v1.1
+analog_exponential_gain_min 0x009a 16 v1.1
+analog_exponential_gain_max 0x009c 16 v1.1
+analog_exponential_gain_step_size 0x009e 16 v1.1
+
+# data format description registers
+data_format_model_type 0x00c0 8
+- e normal 1
+- e extended 2
+data_format_model_subtype 0x00c1 8
+- f rows 0 3
+- f columns 4 7
+data_format_descriptor(n) 0x00c2 16 f
+- l n 0 15 2
+- f compressed 0 7
+- f uncompressed 8 15
+
+# general set-up registers
+mode_select 0x0100 8
+- e software_standby 0
+- e streaming 1
+image_orientation 0x0101 8
+- b horizontal_mirror 0
+- b vertical_flip 1
+software_reset 0x0103 8
+- e off 0
+- e on 1
+grouped_parameter_hold 0x0104 8
+mask_corrupted_frames 0x0105 8
+- e allow 0
+- e mask 1
+fast_standby_ctrl 0x0106 8
+- e complete_frames 0
+- e frame_truncation 1
+CCI_address_ctrl 0x0107 8
+2nd_CCI_if_ctrl 0x0108 8
+- b enable 0
+- b ack 1
+2nd_CCI_address_ctrl 0x0109 8
+CSI_channel_identifier 0x0110 8
+CSI_signaling_mode 0x0111 8
+- e csi_2_dphy 2
+- e csi_2_cphy 3
+CSI_data_format 0x0112 16
+CSI_lane_mode 0x0114 8
+DPCM_Frame_DT 0x011d 8
+Bottom_embedded_data_DT 0x011e 8
+Bottom_embedded_data_VC 0x011f 8
+
+gain_mode 0x0120 8
+- e global 0
+- e alternate 1
+ADC_bit_depth 0x0121 8
+emb_data_ctrl 0x0122 v1.1
+- b raw8_packing_for_raw16 0
+- b raw10_packing_for_raw20 1
+- b raw12_packing_for_raw24 2
+
+GPIO_TRIG_mode 0x0130 8
+extclk_frequency_mhz 0x0136 16 ireal
+temp_sensor_ctrl 0x0138 8
+- b enable 0
+temp_sensor_mode 0x0139 8
+temp_sensor_output 0x013a 8
+
+# integration time registers
+fine_integration_time 0x0200 16
+coarse_integration_time 0x0202 16
+
+# analog gain registers
+analog_gain_code_global 0x0204 16
+analog_linear_gain_global 0x0206 16 v1.1
+analog_exponential_gain_global 0x0208 16 v1.1
+
+# digital gain registers
+digital_gain_global 0x020e 16
+
+# hdr control registers
+Short_analog_gain_global 0x0216 16
+Short_digital_gain_global 0x0218 16
+
+HDR_mode 0x0220 8
+- b enabled 0
+- b separate_analog_gain 1
+- b upscaling 2
+- b reset_sync 3
+- b timing_mode 4
+- b exposure_ctrl_direct 5
+- b separate_digital_gain 6
+HDR_resolution_reduction 0x0221 8
+- f row 0 3
+- f column 4 7
+Exposure_ratio 0x0222 8
+HDR_internal_bit_depth 0x0223 8
+Direct_short_integration_time 0x0224 16
+Short_analog_linear_gain_global 0x0226 16 v1.1
+Short_analog_exponential_gain_global 0x0228 16 v1.1
+
+# clock set-up registers
+vt_pix_clk_div 0x0300 16
+vt_sys_clk_div 0x0302 16
+pre_pll_clk_div 0x0304 16
+#vt_pre_pll_clk_div 0x0304 16
+pll_multiplier 0x0306 16
+#vt_pll_multiplier 0x0306 16
+op_pix_clk_div 0x0308 16
+op_sys_clk_div 0x030a 16
+op_pre_pll_clk_div 0x030c 16
+op_pll_multiplier 0x031e 16
+pll_mode 0x0310 8
+- f 0 0
+- e single 0
+- e dual 1
+op_pix_clk_div_rev 0x0312 16 v1.1
+op_sys_clk_div_rev 0x0314 16 v1.1
+
+# frame timing registers
+frame_length_lines 0x0340 16
+line_length_pck 0x0342 16
+
+# image size registers
+x_addr_start 0x0344 16
+y_addr_start 0x0346 16
+x_addr_end 0x0348 16
+y_addr_end 0x034a 16
+x_output_size 0x034c 16
+y_output_size 0x034e 16
+
+# timing mode registers
+Frame_length_ctrl 0x0350 8
+- b automatic 0
+Timing_mode_ctrl 0x0352 8
+- b manual_readout 0
+- b delayed_exposure 1
+Start_readout_rs 0x0353 8
+- b manual_readout_start 0
+Frame_margin 0x0354 16
+
+# sub-sampling registers
+x_even_inc 0x0380 16
+x_odd_inc 0x0382 16
+y_even_inc 0x0384 16
+y_odd_inc 0x0386 16
+
+# monochrome readout registers
+monochrome_en 0x0390 v1.1
+- e enabled 0
+
+# image scaling registers
+Scaling_mode 0x0400 16
+- e no_scaling 0
+- e horizontal 1
+scale_m 0x0404 16
+scale_n 0x0406 16
+digital_crop_x_offset 0x0408 16
+digital_crop_y_offset 0x040a 16
+digital_crop_image_width 0x040c 16
+digital_crop_image_height 0x040e 16
+
+# image compression registers
+compression_mode 0x0500 16
+- e none 0
+- e dpcm_pcm_simple 1
+
+# test pattern registers
+test_pattern_mode 0x0600 16
+- e none 0
+- e solid_color 1
+- e color_bars 2
+- e fade_to_grey 3
+- e pn9 4
+- e color_tile 5
+test_data_red 0x0602 16
+test_data_greenR 0x0604 16
+test_data_blue 0x0606 16
+test_data_greenB 0x0608 16
+value_step_size_smooth 0x060a 8
+value_step_size_quantised 0x060b 8
+
+# phy configuration registers
+tclk_post 0x0800 8
+ths_prepare 0x0801 8
+ths_zero_min 0x0802 8
+ths_trail 0x0803 8
+tclk_trail_min 0x0804 8
+tclk_prepare 0x0805 8
+tclk_zero 0x0806 8
+tlpx 0x0807 8
+phy_ctrl 0x0808 8
+- e auto 0
+- e UI 1
+- e manual 2
+tclk_post_ex 0x080a 16
+ths_prepare_ex 0x080c 16
+ths_zero_min_ex 0x080e 16
+ths_trail_ex 0x0810 16
+tclk_trail_min_ex 0x0812 16
+tclk_prepare_ex 0x0814 16
+tclk_zero_ex 0x0816 16
+tlpx_ex 0x0818 16
+
+# link rate register
+requested_link_rate 0x0820 32 u16.16
+
+# equalization control registers
+DPHY_equalization_mode 0x0824 8 v1.1
+- b eq2 0
+PHY_equalization_ctrl 0x0825 8 v1.1
+- b enable 0
+
+# d-phy preamble control registers
+DPHY_preamble_ctrl 0x0826 8 v1.1
+- b enable 0
+DPHY_preamble_length 0x0826 8 v1.1
+
+# d-phy spread spectrum control registers
+PHY_SSC_ctrl 0x0828 8 v1.1
+- b enable 0
+
+# manual lp control register
+manual_LP_ctrl 0x0829 8 v1.1
+- b enable 0
+
+# additional phy configuration registers
+twakeup 0x082a v1.1
+tinit 0x082b v1.1
+ths_exit 0x082c v1.1
+ths_exit_ex 0x082e 16 v1.1
+
+# phy calibration configuration registers
+PHY_periodic_calibration_ctrl 0x0830 8
+- b frame_blanking 0
+PHY_periodic_calibration_interval 0x0831 8
+PHY_init_calibration_ctrl 0x0832 8
+- b stream_start 0
+DPHY_calibration_mode 0x0833 8 v1.1
+- b also_alternate 0
+CPHY_calibration_mode 0x0834 8 v1.1
+- e format_1 0
+- e format_2 1
+- e format_3 2
+t3_calpreamble_length 0x0835 8 v1.1
+t3_calpreamble_length_per 0x0836 8 v1.1
+t3_calaltseq_length 0x0837 8 v1.1
+t3_calaltseq_length_per 0x0838 8 v1.1
+FM2_init_seed 0x083a 16 v1.1
+t3_caludefseq_length 0x083c 16 v1.1
+t3_caludefseq_length_per 0x083e 16 v1.1
+
+# c-phy manual control registers
+TGR_Preamble_Length 0x0841 8
+- b preamable_prog_seq 7
+- f begin_preamble_length 0 5
+TGR_Post_Length 0x0842 8
+- f post_length 0 4
+TGR_Preamble_Prog_Sequence(n2) 0x0843
+- l n2 0 6 1
+- f symbol_n_1 3 5
+- f symbol_n 0 2
+t3_prepare 0x084e 16
+t3_lpx 0x0850 16
+
+# alps control register
+ALPS_ctrl 0x085a 8
+- b lvlp_dphy 0
+- b lvlp_cphy 1
+- b alp_cphy 2
+
+# lrte control registers
+TX_REG_CSI_EPD_EN_SSP_cphy 0x0860 16
+TX_REG_CSI_EPD_OP_SLP_cphy 0x0862 16
+TX_REG_CSI_EPD_EN_SSP_dphy 0x0864 16
+TX_REG_CSI_EPD_OP_SLP_dphy 0x0866 16
+TX_REG_CSI_EPD_MISC_OPTION_cphy 0x0868 v1.1
+TX_REG_CSI_EPD_MISC_OPTION_dphy 0x0869 v1.1
+
+# scrambling control registers
+Scrambling_ctrl 0x0870
+- b enabled 0
+- f 2 3
+- e 1_seed_cphy 0
+- e 4_seed_cphy 3
+lane_seed_value(seed, lane) 0x0872 16
+- l seed 0 3 0x10
+- l lane 0 7 0x2
+
+# usl control registers
+TX_USL_REV_ENTRY 0x08c0 16 v1.1
+TX_USL_REV_Clock_Counter 0x08c2 16 v1.1
+TX_USL_REV_LP_Counter 0x08c4 16 v1.1
+TX_USL_REV_Frame_Counter 0x08c6 16 v1.1
+TX_USL_REV_Chronological_Timer 0x08c8 16 v1.1
+TX_USL_FWD_ENTRY 0x08ca 16 v1.1
+TX_USL_GPIO 0x08cc 16 v1.1
+TX_USL_Operation 0x08ce 16 v1.1
+- b reset 0
+TX_USL_ALP_ctrl 0x08d0 16 v1.1
+- b clock_pause 0
+TX_USL_APP_BTA_ACK_TIMEOUT 0x08d2 16 v1.1
+TX_USL_SNS_BTA_ACK_TIMEOUT 0x08d2 16 v1.1
+USL_Clock_Mode_d_ctrl 0x08d2 v1.1
+- b cont_clock_standby 0
+- b cont_clock_vblank 1
+- b cont_clock_hblank 2
+
+# binning configuration registers
+binning_mode 0x0900 8
+binning_type 0x0901 8
+binning_weighting 0x0902 8
+
+# data transfer interface registers
+data_transfer_if_1_ctrl 0x0a00 8
+- b enable 0
+- b write 1
+- b clear_error 2
+data_transfer_if_1_status 0x0a01 8
+- b read_if_ready 0
+- b write_if_ready 1
+- b data_corrupted 2
+- b improper_if_usage 3
+data_transfer_if_1_page_select 0x0a02 8
+data_transfer_if_1_data(p) 0x0a04 8 f
+- l p 0 63 1
+
+# image processing and sensor correction configuration registers
+shading_correction_en 0x0b00 8
+- b enable 0
+luminance_correction_level 0x0b01 8
+green_imbalance_filter_en 0x0b02 8
+- b enable 0
+mapped_defect_correct_en 0x0b05 8
+- b enable 0
+single_defect_correct_en 0x0b06 8
+- b enable 0
+dynamic_couplet_correct_en 0x0b08 8
+- b enable 0
+combined_defect_correct_en 0x0b0a 8
+- b enable 0
+module_specific_correction_en 0x0b0c 8
+- b enable 0
+dynamic_triplet_defect_correct_en 0x0b13 8
+- b enable 0
+NF_ctrl 0x0b15 8
+- b luma 0
+- b chroma 1
+- b combined 2
+
+# optical black pixel readout registers
+OB_readout_control 0x0b30 8
+- b enable 0
+- b interleaving 1
+OB_virtual_channel 0x0b31 8
+OB_DT 0x0b32 8
+OB_data_format 0x0b33 8
+
+# color temperature feedback registers
+color_temperature 0x0b8c 16
+absolute_gain_greenr 0x0b8e 16
+absolute_gain_red 0x0b90 16
+absolute_gain_blue 0x0b92 16
+absolute_gain_greenb 0x0b94 16
+
+# cfa conversion registers
+CFA_conversion_ctrl 0x0ba0 v1.1
+- b bayer_conversion_enable 0
+
+# flash strobe and sa strobe control registers
+flash_strobe_adjustment 0x0c12 8
+flash_strobe_start_point 0x0c14 16
+tflash_strobe_delay_rs_ctrl 0x0c16 16
+tflash_strobe_width_high_rs_ctrl 0x0c18 16
+flash_mode_rs 0x0c1a 8
+- b continuous 0
+- b truncate 1
+- b async 3
+flash_trigger_rs 0x0c1b 8
+flash_status 0x0c1c 8
+- b retimed 0
+sa_strobe_mode 0x0c1d 8
+- b continuous 0
+- b truncate 1
+- b async 3
+- b adjust_edge 4
+sa_strobe_start_point 0x0c1e 16
+tsa_strobe_delay_ctrl 0x0c20 16
+tsa_strobe_width_ctrl 0x0c22 16
+sa_strobe_trigger 0x0c24 8
+sa_strobe_status 0x0c25 8
+- b retimed 0
+tSA_strobe_re_delay_ctrl 0x0c30 16
+tSA_strobe_fe_delay_ctrl 0x0c32 16
+
+# pdaf control registers
+PDAF_ctrl 0x0d00 16
+- b enable 0
+- b processed 1
+- b interleaved 2
+- b visible_pdaf_correction 3
+PDAF_VC 0x0d02 8
+PDAF_DT 0x0d03 8
+pd_x_addr_start 0x0d04 16
+pd_y_addr_start 0x0d06 16
+pd_x_addr_end 0x0d08 16
+pd_y_addr_end 0x0d0a 16
+
+# bracketing interface configuration registers
+bracketing_LUT_ctrl 0x0e00 8
+bracketing_LUT_mode 0x0e01 8
+- b continue_streaming 0
+- b loop_mode 1
+bracketing_LUT_entry_ctrl 0x0e02 8
+bracketing_LUT_frame(n) 0x0e10 v1.1 f
+- l n 0 0xef 1
+
+# integration time and gain parameter limit registers
+integration_time_capability 0x1000 16
+- b fine 0
+coarse_integration_time_min 0x1004 16
+coarse_integration_time_max_margin 0x1006 16
+fine_integration_time_min 0x1008 16
+fine_integration_time_max_margin 0x100a 16
+
+# digital gain parameter limit registers
+digital_gain_capability 0x1081
+- e none 0
+- e global 2
+digital_gain_min 0x1084 16
+digital_gain_max 0x1086 16
+digital_gain_step_size 0x1088 16
+
+# data pedestal capability registers
+Pedestal_capability 0x10e0 8 v1.1
+
+# adc capability registers
+ADC_capability 0x10f0 8
+- b bit_depth_ctrl 0
+ADC_bit_depth_capability 0x10f4 32 v1.1
+
+# video timing parameter limit registers
+min_ext_clk_freq_mhz 0x1100 32 float_ireal
+max_ext_clk_freq_mhz 0x1104 32 float_ireal
+min_pre_pll_clk_div 0x1108 16
+# min_vt_pre_pll_clk_div 0x1108 16
+max_pre_pll_clk_div 0x110a 16
+# max_vt_pre_pll_clk_div 0x110a 16
+min_pll_ip_clk_freq_mhz 0x110c 32 float_ireal
+# min_vt_pll_ip_clk_freq_mhz 0x110c 32 float_ireal
+max_pll_ip_clk_freq_mhz 0x1110 32 float_ireal
+# max_vt_pll_ip_clk_freq_mhz 0x1110 32 float_ireal
+min_pll_multiplier 0x1114 16
+# min_vt_pll_multiplier 0x1114 16
+max_pll_multiplier 0x1116 16
+# max_vt_pll_multiplier 0x1116 16
+min_pll_op_clk_freq_mhz 0x1118 32 float_ireal
+max_pll_op_clk_freq_mhz 0x111c 32 float_ireal
+
+# video timing set-up capability registers
+min_vt_sys_clk_div 0x1120 16
+max_vt_sys_clk_div 0x1122 16
+min_vt_sys_clk_freq_mhz 0x1124 32 float_ireal
+max_vt_sys_clk_freq_mhz 0x1128 32 float_ireal
+min_vt_pix_clk_freq_mhz 0x112c 32 float_ireal
+max_vt_pix_clk_freq_mhz 0x1130 32 float_ireal
+min_vt_pix_clk_div 0x1134 16
+max_vt_pix_clk_div 0x1136 16
+clock_calculation 0x1138
+- b lane_speed 0
+- b link_decoupled 1
+- b dual_pll_op_sys_ddr 2
+- b dual_pll_op_pix_ddr 3
+num_of_vt_lanes 0x1139
+num_of_op_lanes 0x113a
+op_bits_per_lane 0x113b 8 v1.1
+
+# frame timing parameter limits
+min_frame_length_lines 0x1140 16
+max_frame_length_lines 0x1142 16
+min_line_length_pck 0x1144 16
+max_line_length_pck 0x1146 16
+min_line_blanking_pck 0x1148 16
+min_frame_blanking_lines 0x114a 16
+min_line_length_pck_step_size 0x114c
+timing_mode_capability 0x114d
+- b auto_frame_length 0
+- b rolling_shutter_manual_readout 2
+- b delayed_exposure_start 3
+- b manual_exposure_embedded_data 4
+frame_margin_max_value 0x114e 16
+frame_margin_min_value 0x1150
+gain_delay_type 0x1151
+- e fixed 0
+- e variable 1
+
+# output clock set-up capability registers
+min_op_sys_clk_div 0x1160 16
+max_op_sys_clk_div 0x1162 16
+min_op_sys_clk_freq_mhz 0x1164 32 float_ireal
+max_op_sys_clk_freq_mhz 0x1168 32 float_ireal
+min_op_pix_clk_div 0x116c 16
+max_op_pix_clk_div 0x116e 16
+min_op_pix_clk_freq_mhz 0x1170 32 float_ireal
+max_op_pix_clk_freq_mhz 0x1174 32 float_ireal
+
+# image size parameter limit registers
+x_addr_min 0x1180 16
+y_addr_min 0x1182 16
+x_addr_max 0x1184 16
+y_addr_max 0x1186 16
+min_x_output_size 0x1188 16
+min_y_output_size 0x118a 16
+max_x_output_size 0x118c 16
+max_y_output_size 0x118e 16
+
+x_addr_start_div_constant 0x1190 v1.1
+y_addr_start_div_constant 0x1191 v1.1
+x_addr_end_div_constant 0x1192 v1.1
+y_addr_end_div_constant 0x1193 v1.1
+x_size_div 0x1194 v1.1
+y_size_div 0x1195 v1.1
+x_output_div 0x1196 v1.1
+y_output_div 0x1197 v1.1
+non_flexible_resolution_support 0x1198 v1.1
+- b new_pix_addr 0
+- b new_output_res 1
+- b output_crop_no_pad 2
+- b output_size_lane_dep 3
+
+min_op_pre_pll_clk_div 0x11a0 16
+max_op_pre_pll_clk_div 0x11a2 16
+min_op_pll_ip_clk_freq_mhz 0x11a4 32 float_ireal
+max_op_pll_ip_clk_freq_mhz 0x11a8 32 float_ireal
+min_op_pll_multiplier 0x11ac 16
+max_op_pll_multiplier 0x11ae 16
+min_op_pll_op_clk_freq_mhz 0x11b0 32 float_ireal
+max_op_pll_op_clk_freq_mhz 0x11b4 32 float_ireal
+clock_tree_pll_capability 0x11b8 8
+- b dual_pll 0
+- b single_pll 1
+- b ext_divider 2
+- b flexible_op_pix_clk_div 3
+clock_capa_type_capability 0x11b9 v1.1
+- b ireal 0
+
+# sub-sampling parameters limit registers
+min_even_inc 0x11c0 16
+min_odd_inc 0x11c2 16
+max_even_inc 0x11c4 16
+max_odd_inc 0x11c6 16
+aux_subsamp_capability 0x11c8 v1.1
+- b factor_power_of_2 1
+aux_subsamp_mono_capability 0x11c9 v1.1
+- b factor_power_of_2 1
+monochrome_capability 0x11ca v1.1
+- e inc_odd 0
+- e inc_even 1
+pixel_readout_capability 0x11cb v1.1
+- e bayer 0
+- e monochrome 1
+- e bayer_and_mono 2
+min_even_inc_mono 0x11cc 16 v1.1
+max_even_inc_mono 0x11ce 16 v1.1
+min_odd_inc_mono 0x11d0 16 v1.1
+max_odd_inc_mono 0x11d2 16 v1.1
+min_even_inc_bc2 0x11d4 16 v1.1
+max_even_inc_bc2 0x11d6 16 v1.1
+min_odd_inc_bc2 0x11d8 16 v1.1
+max_odd_inc_bc2 0x11da 16 v1.1
+min_even_inc_mono_bc2 0x11dc 16 v1.1
+max_even_inc_mono_bc2 0x11de 16 v1.1
+min_odd_inc_mono_bc2 0x11f0 16 v1.1
+max_odd_inc_mono_bc2 0x11f2 16 v1.1
+
+# image scaling limit parameters
+scaling_capability 0x1200 16
+- e none 0
+- e horizontal 1
+- e reserved 2
+scaler_m_min 0x1204 16
+scaler_m_max 0x1206 16
+scaler_n_min 0x1208 16
+scaler_n_max 0x120a 16
+digital_crop_capability 0x120e
+- e none 0
+- e input_crop 1
+
+# hdr limit registers
+hdr_capability_1 0x1210
+- b 2x2_binning 0
+- b combined_analog_gain 1
+- b separate_analog_gain 2
+- b upscaling 3
+- b reset_sync 4
+- b direct_short_exp_timing 5
+- b direct_short_exp_synthesis 6
+min_hdr_bit_depth 0x1211
+hdr_resolution_sub_types 0x1212
+hdr_resolution_sub_type(n) 0x1213
+- l n 0 1 1
+- f row 0 3
+- f column 4 7
+hdr_capability_2 0x121b
+- b combined_digital_gain 0
+- b separate_digital_gain 1
+- b timing_mode 3
+- b synthesis_mode 4
+max_hdr_bit_depth 0x121c
+
+# usl capability register
+usl_support_capability 0x1230 v1.1
+- b clock_tree 0
+- b rev_clock_tree 1
+- b rev_clock_calc 2
+usl_clock_mode_d_capability 0x1231 v1.1
+- b cont_clock_standby 0
+- b cont_clock_vblank 1
+- b cont_clock_hblank 2
+- b noncont_clock_standby 3
+- b noncont_clock_vblank 4
+- b noncont_clock_hblank 5
+min_op_sys_clk_div_rev 0x1234 v1.1
+max_op_sys_clk_div_rev 0x1236 v1.1
+min_op_pix_clk_div_rev 0x1238 v1.1
+max_op_pix_clk_div_rev 0x123a v1.1
+min_op_sys_clk_freq_rev_mhz 0x123c 32 v1.1 float_ireal
+max_op_sys_clk_freq_rev_mhz 0x1240 32 v1.1 float_ireal
+min_op_pix_clk_freq_rev_mhz 0x1244 32 v1.1 float_ireal
+max_op_pix_clk_freq_rev_mhz 0x1248 32 v1.1 float_ireal
+max_bitrate_rev_d_mode_mbps 0x124c 32 v1.1 ireal
+max_symrate_rev_c_mode_msps 0x1250 32 v1.1 ireal
+
+# image compression capability registers
+compression_capability 0x1300
+- b dpcm_pcm_simple 0
+
+# test mode capability registers
+test_mode_capability 0x1310 16
+- b solid_color 0
+- b color_bars 1
+- b fade_to_grey 2
+- b pn9 3
+- b color_tile 5
+pn9_data_format1 0x1312
+pn9_data_format2 0x1313
+pn9_data_format3 0x1314
+pn9_data_format4 0x1315
+pn9_misc_capability 0x1316
+- f num_pixels 0 2
+- b compression 3
+test_pattern_capability 0x1317 v1.1
+- b no_repeat 1
+pattern_size_div_m1 0x1318 v1.1
+
+# fifo capability registers
+fifo_support_capability 0x1502
+- e none 0
+- e derating 1
+- e derating_overrating 2
+
+# csi-2 capability registers
+phy_ctrl_capability 0x1600
+- b auto_phy_ctl 0
+- b ui_phy_ctl 1
+- b dphy_time_ui_reg_1_ctl 2
+- b dphy_time_ui_reg_2_ctl 3
+- b dphy_time_ctl 4
+- b dphy_ext_time_ui_reg_1_ctl 5
+- b dphy_ext_time_ui_reg_2_ctl 6
+- b dphy_ext_time_ctl 7
+csi_dphy_lane_mode_capability 0x1601
+- b 1_lane 0
+- b 2_lane 1
+- b 3_lane 2
+- b 4_lane 3
+- b 5_lane 4
+- b 6_lane 5
+- b 7_lane 6
+- b 8_lane 7
+csi_signaling_mode_capability 0x1602
+- b csi_dphy 2
+- b csi_cphy 3
+fast_standby_capability 0x1603
+- e no_frame_truncation 0
+- e frame_truncation 1
+csi_address_control_capability 0x1604
+- b cci_addr_change 0
+- b 2nd_cci_addr 1
+- b sw_changeable_2nd_cci_addr 2
+data_type_capability 0x1605
+- b dpcm_programmable 0
+- b bottom_embedded_dt_programmable 1
+- b bottom_embedded_vc_programmable 2
+- b ext_vc_range 3
+csi_cphy_lane_mode_capability 0x1606
+- b 1_lane 0
+- b 2_lane 1
+- b 3_lane 2
+- b 4_lane 3
+- b 5_lane 4
+- b 6_lane 5
+- b 7_lane 6
+- b 8_lane 7
+emb_data_capability 0x1607 v1.1
+- b two_bytes_per_raw16 0
+- b two_bytes_per_raw20 1
+- b two_bytes_per_raw24 2
+- b no_one_byte_per_raw16 3
+- b no_one_byte_per_raw20 4
+- b no_one_byte_per_raw24 5
+max_per_lane_bitrate_lane_d_mode_mbps(n) 0x1608 32 ireal
+- l n 0 7 4 4,0x32
+temp_sensor_capability 0x1618
+- b supported 0
+- b CCS_format 1
+- b reset_0x80 2
+max_per_lane_bitrate_lane_c_mode_mbps(n) 0x161a 32 ireal
+- l n 0 7 4 4,0x30
+dphy_equalization_capability 0x162b
+- b equalization_ctrl 0
+- b eq1 1
+- b eq2 2
+cphy_equalization_capability 0x162c
+- b equalization_ctrl 0
+dphy_preamble_capability 0x162d
+- b preamble_seq_ctrl 0
+dphy_ssc_capability 0x162e
+- b supported 0
+cphy_calibration_capability 0x162f
+- b manual 0
+- b manual_streaming 1
+- b format_1_ctrl 2
+- b format_2_ctrl 3
+- b format_3_ctrl 4
+dphy_calibration_capability 0x1630
+- b manual 0
+- b manual_streaming 1
+- b alternate_seq 2
+phy_ctrl_capability_2 0x1631
+- b tgr_length 0
+- b tgr_preamble_prog_seq 1
+- b extra_cphy_manual_timing 2
+- b clock_based_manual_cdphy 3
+- b clock_based_manual_dphy 4
+- b clock_based_manual_cphy 5
+- b manual_lp_dphy 6
+- b manual_lp_cphy 7
+lrte_cphy_capability 0x1632
+- b pdq_short 0
+- b spacer_short 1
+- b pdq_long 2
+- b spacer_long 3
+- b spacer_no_pdq 4
+lrte_dphy_capability 0x1633
+- b pdq_short_opt1 0
+- b spacer_short_opt1 1
+- b pdq_long_opt1 2
+- b spacer_long_opt1 3
+- b spacer_short_opt2 4
+- b spacer_long_opt2 5
+- b spacer_no_pdq_opt1 6
+- b spacer_variable_opt2 7
+alps_capability_dphy 0x1634
+- e lvlp_not_supported 0 0x3
+- e lvlp_supported 1 0x3
+- e controllable_lvlp 2 0x3
+alps_capability_cphy 0x1635
+- e lvlp_not_supported 0 0x3
+- e lvlp_supported 1 0x3
+- e controllable_lvlp 2 0x3
+- e alp_not_supported 0xc 0xc
+- e alp_supported 0xd 0xc
+- e controllable_alp 0xe 0xc
+scrambling_capability 0x1636
+- b scrambling_supported 0
+- f max_seeds_per_lane_c 1 2
+- e 1 0
+- e 4 3
+- f num_seed_regs 3 5
+- e 0 0
+- e 1 1
+- e 4 4
+- b num_seed_per_lane 6
+dphy_manual_constant 0x1637
+cphy_manual_constant 0x1638
+CSI2_interface_capability_misc 0x1639 v1.1
+- b eotp_short_pkt_opt2 0
+PHY_ctrl_capability_3 0x165c v1.1
+- b dphy_timing_not_multiple 0
+- b dphy_min_timing_value_1 1
+- b twakeup_supported 2
+- b tinit_supported 3
+- b ths_exit_supported 4
+- b cphy_timing_not_multiple 5
+- b cphy_min_timing_value_1 6
+dphy_sf 0x165d v1.1
+cphy_sf 0x165e v1.1
+- f twakeup 0 3
+- f tinit 4 7
+dphy_limits_1 0x165f v1.1
+- f ths_prepare 0 3
+- f ths_zero 4 7
+dphy_limits_2 0x1660 v1.1
+- f ths_trail 0 3
+- f tclk_trail_min 4 7
+dphy_limits_3 0x1661 v1.1
+- f tclk_prepare 0 3
+- f tclk_zero 4 7
+dphy_limits_4 0x1662 v1.1
+- f tclk_post 0 3
+- f tlpx 4 7
+dphy_limits_5 0x1663 v1.1
+- f ths_exit 0 3
+- f twakeup 4 7
+dphy_limits_6 0x1664 v1.1
+- f tinit 0 3
+cphy_limits_1 0x1665 v1.1
+- f t3_prepare_max 0 3
+- f t3_lpx_max 4 7
+cphy_limits_2 0x1666 v1.1
+- f ths_exit_max 0 3
+- f twakeup_max 4 7
+cphy_limits_3 0x1667 v1.1
+- f tinit_max 0 3
+
+# binning capability registers
+min_frame_length_lines_bin 0x1700 16
+max_frame_length_lines_bin 0x1702 16
+min_line_length_pck_bin 0x1704 16
+max_line_length_pck_bin 0x1706 16
+min_line_blanking_pck_bin 0x1708 16
+fine_integration_time_min_bin 0x170a 16
+fine_integration_time_max_margin_bin 0x170c 16
+binning_capability 0x1710
+- e unsupported 0
+- e binning_then_subsampling 1
+- e subsampling_then_binning 2
+binning_weighting_capability 0x1711
+- b averaged 0
+- b summed 1
+- b bayer_corrected 2
+- b module_specific_weight 3
+binning_sub_types 0x1712
+binning_sub_type(n) 0x1713
+- l n 0 63 1
+- f row 0 3
+- f column 4 7
+binning_weighting_mono_capability 0x1771 v1.1
+- b averaged 0
+- b summed 1
+- b bayer_corrected 2
+- b module_specific_weight 3
+binning_sub_types_mono 0x1772 v1.1
+binning_sub_type_mono(n) 0x1773 v1.1 f
+- l n 0 63 1
+
+# data transfer interface capability registers
+data_transfer_if_capability 0x1800
+- b supported 0
+- b polling 2
+
+# sensor correction capability registers
+shading_correction_capability 0x1900
+- b color_shading 0
+- b luminance_correction 1
+green_imbalance_capability 0x1901
+- b supported 0
+module_specific_correction_capability 0x1903
+defect_correction_capability 0x1904 16
+- b mapped_defect 0
+- b dynamic_couplet 2
+- b dynamic_single 5
+- b combined_dynamic 8
+defect_correction_capability_2 0x1906 16
+- b dynamic_triplet 3
+nf_capability 0x1908
+- b luma 0
+- b chroma 1
+- b combined 2
+
+# optical black readout capability registers
+ob_readout_capability 0x1980
+- b controllable_readout 0
+- b visible_pixel_readout 1
+- b different_vc_readout 2
+- b different_dt_readout 3
+- b prog_data_format 4
+
+# color feedback capability registers
+color_feedback_capability 0x1987
+- b kelvin 0
+- b awb_gain 1
+
+# cfa pattern capability registers
+CFA_pattern_capability 0x1990 v1.1
+- e bayer 0
+- e monochrome 1
+- e 4x4_quad_bayer 2
+- e vendor_specific 3
+CFA_pattern_conversion_capability 0x1991 v1.1
+- b bayer 0
+
+# timer capability registers
+flash_mode_capability 0x1a02
+- b single_strobe 0
+sa_strobe_mode_capability 0x1a03
+- b fixed_width 0
+- b edge_ctrl 1
+
+# soft reset capability registers
+reset_max_delay 0x1a10 v1.1
+reset_min_time 0x1a11 v1.1
+
+# pdaf capability registers
+pdaf_capability_1 0x1b80
+- b supported 0
+- b processed_bottom_embedded 1
+- b processed_interleaved 2
+- b raw_bottom_embedded 3
+- b raw_interleaved 4
+- b visible_pdaf_correction 5
+- b vc_interleaving 6
+- b dt_interleaving 7
+pdaf_capability_2 0x1b81
+- b ROI 0
+- b after_digital_crop 1
+- b ctrl_retimed 2
+
+# bracketing interface capability registers
+bracketing_lut_capability_1 0x1c00
+- b coarse_integration 0
+- b global_analog_gain 1
+- b flash 4
+- b global_digital_gain 5
+- b alternate_global_analog_gain 6
+bracketing_lut_capability_2 0x1c01
+- b single_bracketing_mode 0
+- b looped_bracketing_mode 1
+bracketing_lut_size 0x1c02
+++ /dev/null
-# Copyright (C) 2019--2020 Intel Corporation
-# SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
-
-# register rflags
-# - f field LSB MSB rflags
-# - e enum value # after a field
-# - e enum value [LSB MSB]
-# - b bool bit
-# - l arg name min max elsize [discontig...]
-#
-# rflags
-# 8, 16, 32 register bits (default is 8)
-# v1.1 defined in version 1.1
-# f formula
-# float_ireal iReal or IEEE 754; 32 bits
-# ireal unsigned iReal
-
-# general status registers
-module_model_id 0x0000 16
-module_revision_number_major 0x0002 8
-frame_count 0x0005 8
-pixel_order 0x0006 8
-- e GRBG 0
-- e RGGB 1
-- e BGGR 2
-- e GBRG 3
-MIPI_CCS_version 0x0007 8
-- e v1_0 0x10
-- e v1_1 0x11
-- f major 4 7
-- f minor 0 3
-data_pedestal 0x0008 16
-module_manufacturer_id 0x000e 16
-module_revision_number_minor 0x0010 8
-module_date_year 0x0012 8
-module_date_month 0x0013 8
-module_date_day 0x0014 8
-module_date_phase 0x0015 8
-- f 0 2
-- e ts 0
-- e es 1
-- e cs 2
-- e mp 3
-sensor_model_id 0x0016 16
-sensor_revision_number 0x0018 8
-sensor_firmware_version 0x001a 8
-serial_number 0x001c 32
-sensor_manufacturer_id 0x0020 16
-sensor_revision_number_16 0x0022 16
-
-# frame format description registers
-frame_format_model_type 0x0040 8
-- e 2-byte 1
-- e 4-byte 2
-frame_format_model_subtype 0x0041 8
-- f rows 0 3
-- f columns 4 7
-frame_format_descriptor(n) 0x0042 16 f
-- l n 0 14 2
-- f pixels 0 11
-- f pcode 12 15
-- e embedded 1
-- e dummy_pixel 2
-- e black_pixel 3
-- e dark_pixel 4
-- e visible_pixel 5
-- e manuf_specific_0 8
-- e manuf_specific_1 9
-- e manuf_specific_2 10
-- e manuf_specific_3 11
-- e manuf_specific_4 12
-- e manuf_specific_5 13
-- e manuf_specific_6 14
-frame_format_descriptor_4(n) 0x0060 32 f
-- l n 0 7 4
-- f pixels 0 15
-- f pcode 28 31
-- e embedded 1
-- e dummy_pixel 2
-- e black_pixel 3
-- e dark_pixel 4
-- e visible_pixel 5
-- e manuf_specific_0 8
-- e manuf_specific_1 9
-- e manuf_specific_2 10
-- e manuf_specific_3 11
-- e manuf_specific_4 12
-- e manuf_specific_5 13
-- e manuf_specific_6 14
-
-# analog gain description registers
-analog_gain_capability 0x0080 16
-- e global 0
-- e alternate_global 2
-analog_gain_code_min 0x0084 16
-analog_gain_code_max 0x0086 16
-analog_gain_code_step 0x0088 16
-analog_gain_type 0x008a 16
-analog_gain_m0 0x008c 16
-analog_gain_c0 0x008e 16
-analog_gain_m1 0x0090 16
-analog_gain_c1 0x0092 16
-analog_linear_gain_min 0x0094 16 v1.1
-analog_linear_gain_max 0x0096 16 v1.1
-analog_linear_gain_step_size 0x0098 16 v1.1
-analog_exponential_gain_min 0x009a 16 v1.1
-analog_exponential_gain_max 0x009c 16 v1.1
-analog_exponential_gain_step_size 0x009e 16 v1.1
-
-# data format description registers
-data_format_model_type 0x00c0 8
-- e normal 1
-- e extended 2
-data_format_model_subtype 0x00c1 8
-- f rows 0 3
-- f columns 4 7
-data_format_descriptor(n) 0x00c2 16 f
-- l n 0 15 2
-- f compressed 0 7
-- f uncompressed 8 15
-
-# general set-up registers
-mode_select 0x0100 8
-- e software_standby 0
-- e streaming 1
-image_orientation 0x0101 8
-- b horizontal_mirror 0
-- b vertical_flip 1
-software_reset 0x0103 8
-- e off 0
-- e on 1
-grouped_parameter_hold 0x0104 8
-mask_corrupted_frames 0x0105 8
-- e allow 0
-- e mask 1
-fast_standby_ctrl 0x0106 8
-- e complete_frames 0
-- e frame_truncation 1
-CCI_address_ctrl 0x0107 8
-2nd_CCI_if_ctrl 0x0108 8
-- b enable 0
-- b ack 1
-2nd_CCI_address_ctrl 0x0109 8
-CSI_channel_identifier 0x0110 8
-CSI_signaling_mode 0x0111 8
-- e csi_2_dphy 2
-- e csi_2_cphy 3
-CSI_data_format 0x0112 16
-CSI_lane_mode 0x0114 8
-DPCM_Frame_DT 0x011d 8
-Bottom_embedded_data_DT 0x011e 8
-Bottom_embedded_data_VC 0x011f 8
-
-gain_mode 0x0120 8
-- e global 0
-- e alternate 1
-ADC_bit_depth 0x0121 8
-emb_data_ctrl 0x0122 v1.1
-- b raw8_packing_for_raw16 0
-- b raw10_packing_for_raw20 1
-- b raw12_packing_for_raw24 2
-
-GPIO_TRIG_mode 0x0130 8
-extclk_frequency_mhz 0x0136 16 ireal
-temp_sensor_ctrl 0x0138 8
-- b enable 0
-temp_sensor_mode 0x0139 8
-temp_sensor_output 0x013a 8
-
-# integration time registers
-fine_integration_time 0x0200 16
-coarse_integration_time 0x0202 16
-
-# analog gain registers
-analog_gain_code_global 0x0204 16
-analog_linear_gain_global 0x0206 16 v1.1
-analog_exponential_gain_global 0x0208 16 v1.1
-
-# digital gain registers
-digital_gain_global 0x020e 16
-
-# hdr control registers
-Short_analog_gain_global 0x0216 16
-Short_digital_gain_global 0x0218 16
-
-HDR_mode 0x0220 8
-- b enabled 0
-- b separate_analog_gain 1
-- b upscaling 2
-- b reset_sync 3
-- b timing_mode 4
-- b exposure_ctrl_direct 5
-- b separate_digital_gain 6
-HDR_resolution_reduction 0x0221 8
-- f row 0 3
-- f column 4 7
-Exposure_ratio 0x0222 8
-HDR_internal_bit_depth 0x0223 8
-Direct_short_integration_time 0x0224 16
-Short_analog_linear_gain_global 0x0226 16 v1.1
-Short_analog_exponential_gain_global 0x0228 16 v1.1
-
-# clock set-up registers
-vt_pix_clk_div 0x0300 16
-vt_sys_clk_div 0x0302 16
-pre_pll_clk_div 0x0304 16
-#vt_pre_pll_clk_div 0x0304 16
-pll_multiplier 0x0306 16
-#vt_pll_multiplier 0x0306 16
-op_pix_clk_div 0x0308 16
-op_sys_clk_div 0x030a 16
-op_pre_pll_clk_div 0x030c 16
-op_pll_multiplier 0x031e 16
-pll_mode 0x0310 8
-- f 0 0
-- e single 0
-- e dual 1
-op_pix_clk_div_rev 0x0312 16 v1.1
-op_sys_clk_div_rev 0x0314 16 v1.1
-
-# frame timing registers
-frame_length_lines 0x0340 16
-line_length_pck 0x0342 16
-
-# image size registers
-x_addr_start 0x0344 16
-y_addr_start 0x0346 16
-x_addr_end 0x0348 16
-y_addr_end 0x034a 16
-x_output_size 0x034c 16
-y_output_size 0x034e 16
-
-# timing mode registers
-Frame_length_ctrl 0x0350 8
-- b automatic 0
-Timing_mode_ctrl 0x0352 8
-- b manual_readout 0
-- b delayed_exposure 1
-Start_readout_rs 0x0353 8
-- b manual_readout_start 0
-Frame_margin 0x0354 16
-
-# sub-sampling registers
-x_even_inc 0x0380 16
-x_odd_inc 0x0382 16
-y_even_inc 0x0384 16
-y_odd_inc 0x0386 16
-
-# monochrome readout registers
-monochrome_en 0x0390 v1.1
-- e enabled 0
-
-# image scaling registers
-Scaling_mode 0x0400 16
-- e no_scaling 0
-- e horizontal 1
-scale_m 0x0404 16
-scale_n 0x0406 16
-digital_crop_x_offset 0x0408 16
-digital_crop_y_offset 0x040a 16
-digital_crop_image_width 0x040c 16
-digital_crop_image_height 0x040e 16
-
-# image compression registers
-compression_mode 0x0500 16
-- e none 0
-- e dpcm_pcm_simple 1
-
-# test pattern registers
-test_pattern_mode 0x0600 16
-- e none 0
-- e solid_color 1
-- e color_bars 2
-- e fade_to_grey 3
-- e pn9 4
-- e color_tile 5
-test_data_red 0x0602 16
-test_data_greenR 0x0604 16
-test_data_blue 0x0606 16
-test_data_greenB 0x0608 16
-value_step_size_smooth 0x060a 8
-value_step_size_quantised 0x060b 8
-
-# phy configuration registers
-tclk_post 0x0800 8
-ths_prepare 0x0801 8
-ths_zero_min 0x0802 8
-ths_trail 0x0803 8
-tclk_trail_min 0x0804 8
-tclk_prepare 0x0805 8
-tclk_zero 0x0806 8
-tlpx 0x0807 8
-phy_ctrl 0x0808 8
-- e auto 0
-- e UI 1
-- e manual 2
-tclk_post_ex 0x080a 16
-ths_prepare_ex 0x080c 16
-ths_zero_min_ex 0x080e 16
-ths_trail_ex 0x0810 16
-tclk_trail_min_ex 0x0812 16
-tclk_prepare_ex 0x0814 16
-tclk_zero_ex 0x0816 16
-tlpx_ex 0x0818 16
-
-# link rate register
-requested_link_rate 0x0820 32 u16.16
-
-# equalization control registers
-DPHY_equalization_mode 0x0824 8 v1.1
-- b eq2 0
-PHY_equalization_ctrl 0x0825 8 v1.1
-- b enable 0
-
-# d-phy preamble control registers
-DPHY_preamble_ctrl 0x0826 8 v1.1
-- b enable 0
-DPHY_preamble_length 0x0826 8 v1.1
-
-# d-phy spread spectrum control registers
-PHY_SSC_ctrl 0x0828 8 v1.1
-- b enable 0
-
-# manual lp control register
-manual_LP_ctrl 0x0829 8 v1.1
-- b enable 0
-
-# additional phy configuration registers
-twakeup 0x082a v1.1
-tinit 0x082b v1.1
-ths_exit 0x082c v1.1
-ths_exit_ex 0x082e 16 v1.1
-
-# phy calibration configuration registers
-PHY_periodic_calibration_ctrl 0x0830 8
-- b frame_blanking 0
-PHY_periodic_calibration_interval 0x0831 8
-PHY_init_calibration_ctrl 0x0832 8
-- b stream_start 0
-DPHY_calibration_mode 0x0833 8 v1.1
-- b also_alternate 0
-CPHY_calibration_mode 0x0834 8 v1.1
-- e format_1 0
-- e format_2 1
-- e format_3 2
-t3_calpreamble_length 0x0835 8 v1.1
-t3_calpreamble_length_per 0x0836 8 v1.1
-t3_calaltseq_length 0x0837 8 v1.1
-t3_calaltseq_length_per 0x0838 8 v1.1
-FM2_init_seed 0x083a 16 v1.1
-t3_caludefseq_length 0x083c 16 v1.1
-t3_caludefseq_length_per 0x083e 16 v1.1
-
-# c-phy manual control registers
-TGR_Preamble_Length 0x0841 8
-- b preamable_prog_seq 7
-- f begin_preamble_length 0 5
-TGR_Post_Length 0x0842 8
-- f post_length 0 4
-TGR_Preamble_Prog_Sequence(n2) 0x0843
-- l n2 0 6 1
-- f symbol_n_1 3 5
-- f symbol_n 0 2
-t3_prepare 0x084e 16
-t3_lpx 0x0850 16
-
-# alps control register
-ALPS_ctrl 0x085a 8
-- b lvlp_dphy 0
-- b lvlp_cphy 1
-- b alp_cphy 2
-
-# lrte control registers
-TX_REG_CSI_EPD_EN_SSP_cphy 0x0860 16
-TX_REG_CSI_EPD_OP_SLP_cphy 0x0862 16
-TX_REG_CSI_EPD_EN_SSP_dphy 0x0864 16
-TX_REG_CSI_EPD_OP_SLP_dphy 0x0866 16
-TX_REG_CSI_EPD_MISC_OPTION_cphy 0x0868 v1.1
-TX_REG_CSI_EPD_MISC_OPTION_dphy 0x0869 v1.1
-
-# scrambling control registers
-Scrambling_ctrl 0x0870
-- b enabled 0
-- f 2 3
-- e 1_seed_cphy 0
-- e 4_seed_cphy 3
-lane_seed_value(seed, lane) 0x0872 16
-- l seed 0 3 0x10
-- l lane 0 7 0x2
-
-# usl control registers
-TX_USL_REV_ENTRY 0x08c0 16 v1.1
-TX_USL_REV_Clock_Counter 0x08c2 16 v1.1
-TX_USL_REV_LP_Counter 0x08c4 16 v1.1
-TX_USL_REV_Frame_Counter 0x08c6 16 v1.1
-TX_USL_REV_Chronological_Timer 0x08c8 16 v1.1
-TX_USL_FWD_ENTRY 0x08ca 16 v1.1
-TX_USL_GPIO 0x08cc 16 v1.1
-TX_USL_Operation 0x08ce 16 v1.1
-- b reset 0
-TX_USL_ALP_ctrl 0x08d0 16 v1.1
-- b clock_pause 0
-TX_USL_APP_BTA_ACK_TIMEOUT 0x08d2 16 v1.1
-TX_USL_SNS_BTA_ACK_TIMEOUT 0x08d2 16 v1.1
-USL_Clock_Mode_d_ctrl 0x08d2 v1.1
-- b cont_clock_standby 0
-- b cont_clock_vblank 1
-- b cont_clock_hblank 2
-
-# binning configuration registers
-binning_mode 0x0900 8
-binning_type 0x0901 8
-binning_weighting 0x0902 8
-
-# data transfer interface registers
-data_transfer_if_1_ctrl 0x0a00 8
-- b enable 0
-- b write 1
-- b clear_error 2
-data_transfer_if_1_status 0x0a01 8
-- b read_if_ready 0
-- b write_if_ready 1
-- b data_corrupted 2
-- b improper_if_usage 3
-data_transfer_if_1_page_select 0x0a02 8
-data_transfer_if_1_data(p) 0x0a04 8 f
-- l p 0 63 1
-
-# image processing and sensor correction configuration registers
-shading_correction_en 0x0b00 8
-- b enable 0
-luminance_correction_level 0x0b01 8
-green_imbalance_filter_en 0x0b02 8
-- b enable 0
-mapped_defect_correct_en 0x0b05 8
-- b enable 0
-single_defect_correct_en 0x0b06 8
-- b enable 0
-dynamic_couplet_correct_en 0x0b08 8
-- b enable 0
-combined_defect_correct_en 0x0b0a 8
-- b enable 0
-module_specific_correction_en 0x0b0c 8
-- b enable 0
-dynamic_triplet_defect_correct_en 0x0b13 8
-- b enable 0
-NF_ctrl 0x0b15 8
-- b luma 0
-- b chroma 1
-- b combined 2
-
-# optical black pixel readout registers
-OB_readout_control 0x0b30 8
-- b enable 0
-- b interleaving 1
-OB_virtual_channel 0x0b31 8
-OB_DT 0x0b32 8
-OB_data_format 0x0b33 8
-
-# color temperature feedback registers
-color_temperature 0x0b8c 16
-absolute_gain_greenr 0x0b8e 16
-absolute_gain_red 0x0b90 16
-absolute_gain_blue 0x0b92 16
-absolute_gain_greenb 0x0b94 16
-
-# cfa conversion registers
-CFA_conversion_ctrl 0x0ba0 v1.1
-- b bayer_conversion_enable 0
-
-# flash strobe and sa strobe control registers
-flash_strobe_adjustment 0x0c12 8
-flash_strobe_start_point 0x0c14 16
-tflash_strobe_delay_rs_ctrl 0x0c16 16
-tflash_strobe_width_high_rs_ctrl 0x0c18 16
-flash_mode_rs 0x0c1a 8
-- b continuous 0
-- b truncate 1
-- b async 3
-flash_trigger_rs 0x0c1b 8
-flash_status 0x0c1c 8
-- b retimed 0
-sa_strobe_mode 0x0c1d 8
-- b continuous 0
-- b truncate 1
-- b async 3
-- b adjust_edge 4
-sa_strobe_start_point 0x0c1e 16
-tsa_strobe_delay_ctrl 0x0c20 16
-tsa_strobe_width_ctrl 0x0c22 16
-sa_strobe_trigger 0x0c24 8
-sa_strobe_status 0x0c25 8
-- b retimed 0
-tSA_strobe_re_delay_ctrl 0x0c30 16
-tSA_strobe_fe_delay_ctrl 0x0c32 16
-
-# pdaf control registers
-PDAF_ctrl 0x0d00 16
-- b enable 0
-- b processed 1
-- b interleaved 2
-- b visible_pdaf_correction 3
-PDAF_VC 0x0d02 8
-PDAF_DT 0x0d03 8
-pd_x_addr_start 0x0d04 16
-pd_y_addr_start 0x0d06 16
-pd_x_addr_end 0x0d08 16
-pd_y_addr_end 0x0d0a 16
-
-# bracketing interface configuration registers
-bracketing_LUT_ctrl 0x0e00 8
-bracketing_LUT_mode 0x0e01 8
-- b continue_streaming 0
-- b loop_mode 1
-bracketing_LUT_entry_ctrl 0x0e02 8
-bracketing_LUT_frame(n) 0x0e10 v1.1 f
-- l n 0 0xef 1
-
-# integration time and gain parameter limit registers
-integration_time_capability 0x1000 16
-- b fine 0
-coarse_integration_time_min 0x1004 16
-coarse_integration_time_max_margin 0x1006 16
-fine_integration_time_min 0x1008 16
-fine_integration_time_max_margin 0x100a 16
-
-# digital gain parameter limit registers
-digital_gain_capability 0x1081
-- e none 0
-- e global 2
-digital_gain_min 0x1084 16
-digital_gain_max 0x1086 16
-digital_gain_step_size 0x1088 16
-
-# data pedestal capability registers
-Pedestal_capability 0x10e0 8 v1.1
-
-# adc capability registers
-ADC_capability 0x10f0 8
-- b bit_depth_ctrl 0
-ADC_bit_depth_capability 0x10f4 32 v1.1
-
-# video timing parameter limit registers
-min_ext_clk_freq_mhz 0x1100 32 float_ireal
-max_ext_clk_freq_mhz 0x1104 32 float_ireal
-min_pre_pll_clk_div 0x1108 16
-# min_vt_pre_pll_clk_div 0x1108 16
-max_pre_pll_clk_div 0x110a 16
-# max_vt_pre_pll_clk_div 0x110a 16
-min_pll_ip_clk_freq_mhz 0x110c 32 float_ireal
-# min_vt_pll_ip_clk_freq_mhz 0x110c 32 float_ireal
-max_pll_ip_clk_freq_mhz 0x1110 32 float_ireal
-# max_vt_pll_ip_clk_freq_mhz 0x1110 32 float_ireal
-min_pll_multiplier 0x1114 16
-# min_vt_pll_multiplier 0x1114 16
-max_pll_multiplier 0x1116 16
-# max_vt_pll_multiplier 0x1116 16
-min_pll_op_clk_freq_mhz 0x1118 32 float_ireal
-max_pll_op_clk_freq_mhz 0x111c 32 float_ireal
-
-# video timing set-up capability registers
-min_vt_sys_clk_div 0x1120 16
-max_vt_sys_clk_div 0x1122 16
-min_vt_sys_clk_freq_mhz 0x1124 32 float_ireal
-max_vt_sys_clk_freq_mhz 0x1128 32 float_ireal
-min_vt_pix_clk_freq_mhz 0x112c 32 float_ireal
-max_vt_pix_clk_freq_mhz 0x1130 32 float_ireal
-min_vt_pix_clk_div 0x1134 16
-max_vt_pix_clk_div 0x1136 16
-clock_calculation 0x1138
-- b lane_speed 0
-- b link_decoupled 1
-- b dual_pll_op_sys_ddr 2
-- b dual_pll_op_pix_ddr 3
-num_of_vt_lanes 0x1139
-num_of_op_lanes 0x113a
-op_bits_per_lane 0x113b 8 v1.1
-
-# frame timing parameter limits
-min_frame_length_lines 0x1140 16
-max_frame_length_lines 0x1142 16
-min_line_length_pck 0x1144 16
-max_line_length_pck 0x1146 16
-min_line_blanking_pck 0x1148 16
-min_frame_blanking_lines 0x114a 16
-min_line_length_pck_step_size 0x114c
-timing_mode_capability 0x114d
-- b auto_frame_length 0
-- b rolling_shutter_manual_readout 2
-- b delayed_exposure_start 3
-- b manual_exposure_embedded_data 4
-frame_margin_max_value 0x114e 16
-frame_margin_min_value 0x1150
-gain_delay_type 0x1151
-- e fixed 0
-- e variable 1
-
-# output clock set-up capability registers
-min_op_sys_clk_div 0x1160 16
-max_op_sys_clk_div 0x1162 16
-min_op_sys_clk_freq_mhz 0x1164 32 float_ireal
-max_op_sys_clk_freq_mhz 0x1168 32 float_ireal
-min_op_pix_clk_div 0x116c 16
-max_op_pix_clk_div 0x116e 16
-min_op_pix_clk_freq_mhz 0x1170 32 float_ireal
-max_op_pix_clk_freq_mhz 0x1174 32 float_ireal
-
-# image size parameter limit registers
-x_addr_min 0x1180 16
-y_addr_min 0x1182 16
-x_addr_max 0x1184 16
-y_addr_max 0x1186 16
-min_x_output_size 0x1188 16
-min_y_output_size 0x118a 16
-max_x_output_size 0x118c 16
-max_y_output_size 0x118e 16
-
-x_addr_start_div_constant 0x1190 v1.1
-y_addr_start_div_constant 0x1191 v1.1
-x_addr_end_div_constant 0x1192 v1.1
-y_addr_end_div_constant 0x1193 v1.1
-x_size_div 0x1194 v1.1
-y_size_div 0x1195 v1.1
-x_output_div 0x1196 v1.1
-y_output_div 0x1197 v1.1
-non_flexible_resolution_support 0x1198 v1.1
-- b new_pix_addr 0
-- b new_output_res 1
-- b output_crop_no_pad 2
-- b output_size_lane_dep 3
-
-min_op_pre_pll_clk_div 0x11a0 16
-max_op_pre_pll_clk_div 0x11a2 16
-min_op_pll_ip_clk_freq_mhz 0x11a4 32 float_ireal
-max_op_pll_ip_clk_freq_mhz 0x11a8 32 float_ireal
-min_op_pll_multiplier 0x11ac 16
-max_op_pll_multiplier 0x11ae 16
-min_op_pll_op_clk_freq_mhz 0x11b0 32 float_ireal
-max_op_pll_op_clk_freq_mhz 0x11b4 32 float_ireal
-clock_tree_pll_capability 0x11b8 8
-- b dual_pll 0
-- b single_pll 1
-- b ext_divider 2
-- b flexible_op_pix_clk_div 3
-clock_capa_type_capability 0x11b9 v1.1
-- b ireal 0
-
-# sub-sampling parameters limit registers
-min_even_inc 0x11c0 16
-min_odd_inc 0x11c2 16
-max_even_inc 0x11c4 16
-max_odd_inc 0x11c6 16
-aux_subsamp_capability 0x11c8 v1.1
-- b factor_power_of_2 1
-aux_subsamp_mono_capability 0x11c9 v1.1
-- b factor_power_of_2 1
-monochrome_capability 0x11ca v1.1
-- e inc_odd 0
-- e inc_even 1
-pixel_readout_capability 0x11cb v1.1
-- e bayer 0
-- e monochrome 1
-- e bayer_and_mono 2
-min_even_inc_mono 0x11cc 16 v1.1
-max_even_inc_mono 0x11ce 16 v1.1
-min_odd_inc_mono 0x11d0 16 v1.1
-max_odd_inc_mono 0x11d2 16 v1.1
-min_even_inc_bc2 0x11d4 16 v1.1
-max_even_inc_bc2 0x11d6 16 v1.1
-min_odd_inc_bc2 0x11d8 16 v1.1
-max_odd_inc_bc2 0x11da 16 v1.1
-min_even_inc_mono_bc2 0x11dc 16 v1.1
-max_even_inc_mono_bc2 0x11de 16 v1.1
-min_odd_inc_mono_bc2 0x11f0 16 v1.1
-max_odd_inc_mono_bc2 0x11f2 16 v1.1
-
-# image scaling limit parameters
-scaling_capability 0x1200 16
-- e none 0
-- e horizontal 1
-- e reserved 2
-scaler_m_min 0x1204 16
-scaler_m_max 0x1206 16
-scaler_n_min 0x1208 16
-scaler_n_max 0x120a 16
-digital_crop_capability 0x120e
-- e none 0
-- e input_crop 1
-
-# hdr limit registers
-hdr_capability_1 0x1210
-- b 2x2_binning 0
-- b combined_analog_gain 1
-- b separate_analog_gain 2
-- b upscaling 3
-- b reset_sync 4
-- b direct_short_exp_timing 5
-- b direct_short_exp_synthesis 6
-min_hdr_bit_depth 0x1211
-hdr_resolution_sub_types 0x1212
-hdr_resolution_sub_type(n) 0x1213
-- l n 0 1 1
-- f row 0 3
-- f column 4 7
-hdr_capability_2 0x121b
-- b combined_digital_gain 0
-- b separate_digital_gain 1
-- b timing_mode 3
-- b synthesis_mode 4
-max_hdr_bit_depth 0x121c
-
-# usl capability register
-usl_support_capability 0x1230 v1.1
-- b clock_tree 0
-- b rev_clock_tree 1
-- b rev_clock_calc 2
-usl_clock_mode_d_capability 0x1231 v1.1
-- b cont_clock_standby 0
-- b cont_clock_vblank 1
-- b cont_clock_hblank 2
-- b noncont_clock_standby 3
-- b noncont_clock_vblank 4
-- b noncont_clock_hblank 5
-min_op_sys_clk_div_rev 0x1234 v1.1
-max_op_sys_clk_div_rev 0x1236 v1.1
-min_op_pix_clk_div_rev 0x1238 v1.1
-max_op_pix_clk_div_rev 0x123a v1.1
-min_op_sys_clk_freq_rev_mhz 0x123c 32 v1.1 float_ireal
-max_op_sys_clk_freq_rev_mhz 0x1240 32 v1.1 float_ireal
-min_op_pix_clk_freq_rev_mhz 0x1244 32 v1.1 float_ireal
-max_op_pix_clk_freq_rev_mhz 0x1248 32 v1.1 float_ireal
-max_bitrate_rev_d_mode_mbps 0x124c 32 v1.1 ireal
-max_symrate_rev_c_mode_msps 0x1250 32 v1.1 ireal
-
-# image compression capability registers
-compression_capability 0x1300
-- b dpcm_pcm_simple 0
-
-# test mode capability registers
-test_mode_capability 0x1310 16
-- b solid_color 0
-- b color_bars 1
-- b fade_to_grey 2
-- b pn9 3
-- b color_tile 5
-pn9_data_format1 0x1312
-pn9_data_format2 0x1313
-pn9_data_format3 0x1314
-pn9_data_format4 0x1315
-pn9_misc_capability 0x1316
-- f num_pixels 0 2
-- b compression 3
-test_pattern_capability 0x1317 v1.1
-- b no_repeat 1
-pattern_size_div_m1 0x1318 v1.1
-
-# fifo capability registers
-fifo_support_capability 0x1502
-- e none 0
-- e derating 1
-- e derating_overrating 2
-
-# csi-2 capability registers
-phy_ctrl_capability 0x1600
-- b auto_phy_ctl 0
-- b ui_phy_ctl 1
-- b dphy_time_ui_reg_1_ctl 2
-- b dphy_time_ui_reg_2_ctl 3
-- b dphy_time_ctl 4
-- b dphy_ext_time_ui_reg_1_ctl 5
-- b dphy_ext_time_ui_reg_2_ctl 6
-- b dphy_ext_time_ctl 7
-csi_dphy_lane_mode_capability 0x1601
-- b 1_lane 0
-- b 2_lane 1
-- b 3_lane 2
-- b 4_lane 3
-- b 5_lane 4
-- b 6_lane 5
-- b 7_lane 6
-- b 8_lane 7
-csi_signaling_mode_capability 0x1602
-- b csi_dphy 2
-- b csi_cphy 3
-fast_standby_capability 0x1603
-- e no_frame_truncation 0
-- e frame_truncation 1
-csi_address_control_capability 0x1604
-- b cci_addr_change 0
-- b 2nd_cci_addr 1
-- b sw_changeable_2nd_cci_addr 2
-data_type_capability 0x1605
-- b dpcm_programmable 0
-- b bottom_embedded_dt_programmable 1
-- b bottom_embedded_vc_programmable 2
-- b ext_vc_range 3
-csi_cphy_lane_mode_capability 0x1606
-- b 1_lane 0
-- b 2_lane 1
-- b 3_lane 2
-- b 4_lane 3
-- b 5_lane 4
-- b 6_lane 5
-- b 7_lane 6
-- b 8_lane 7
-emb_data_capability 0x1607 v1.1
-- b two_bytes_per_raw16 0
-- b two_bytes_per_raw20 1
-- b two_bytes_per_raw24 2
-- b no_one_byte_per_raw16 3
-- b no_one_byte_per_raw20 4
-- b no_one_byte_per_raw24 5
-max_per_lane_bitrate_lane_d_mode_mbps(n) 0x1608 32 ireal
-- l n 0 7 4 4,0x32
-temp_sensor_capability 0x1618
-- b supported 0
-- b CCS_format 1
-- b reset_0x80 2
-max_per_lane_bitrate_lane_c_mode_mbps(n) 0x161a 32 ireal
-- l n 0 7 4 4,0x30
-dphy_equalization_capability 0x162b
-- b equalization_ctrl 0
-- b eq1 1
-- b eq2 2
-cphy_equalization_capability 0x162c
-- b equalization_ctrl 0
-dphy_preamble_capability 0x162d
-- b preamble_seq_ctrl 0
-dphy_ssc_capability 0x162e
-- b supported 0
-cphy_calibration_capability 0x162f
-- b manual 0
-- b manual_streaming 1
-- b format_1_ctrl 2
-- b format_2_ctrl 3
-- b format_3_ctrl 4
-dphy_calibration_capability 0x1630
-- b manual 0
-- b manual_streaming 1
-- b alternate_seq 2
-phy_ctrl_capability_2 0x1631
-- b tgr_length 0
-- b tgr_preamble_prog_seq 1
-- b extra_cphy_manual_timing 2
-- b clock_based_manual_cdphy 3
-- b clock_based_manual_dphy 4
-- b clock_based_manual_cphy 5
-- b manual_lp_dphy 6
-- b manual_lp_cphy 7
-lrte_cphy_capability 0x1632
-- b pdq_short 0
-- b spacer_short 1
-- b pdq_long 2
-- b spacer_long 3
-- b spacer_no_pdq 4
-lrte_dphy_capability 0x1633
-- b pdq_short_opt1 0
-- b spacer_short_opt1 1
-- b pdq_long_opt1 2
-- b spacer_long_opt1 3
-- b spacer_short_opt2 4
-- b spacer_long_opt2 5
-- b spacer_no_pdq_opt1 6
-- b spacer_variable_opt2 7
-alps_capability_dphy 0x1634
-- e lvlp_not_supported 0 0x3
-- e lvlp_supported 1 0x3
-- e controllable_lvlp 2 0x3
-alps_capability_cphy 0x1635
-- e lvlp_not_supported 0 0x3
-- e lvlp_supported 1 0x3
-- e controllable_lvlp 2 0x3
-- e alp_not_supported 0xc 0xc
-- e alp_supported 0xd 0xc
-- e controllable_alp 0xe 0xc
-scrambling_capability 0x1636
-- b scrambling_supported 0
-- f max_seeds_per_lane_c 1 2
-- e 1 0
-- e 4 3
-- f num_seed_regs 3 5
-- e 0 0
-- e 1 1
-- e 4 4
-- b num_seed_per_lane 6
-dphy_manual_constant 0x1637
-cphy_manual_constant 0x1638
-CSI2_interface_capability_misc 0x1639 v1.1
-- b eotp_short_pkt_opt2 0
-PHY_ctrl_capability_3 0x165c v1.1
-- b dphy_timing_not_multiple 0
-- b dphy_min_timing_value_1 1
-- b twakeup_supported 2
-- b tinit_supported 3
-- b ths_exit_supported 4
-- b cphy_timing_not_multiple 5
-- b cphy_min_timing_value_1 6
-dphy_sf 0x165d v1.1
-cphy_sf 0x165e v1.1
-- f twakeup 0 3
-- f tinit 4 7
-dphy_limits_1 0x165f v1.1
-- f ths_prepare 0 3
-- f ths_zero 4 7
-dphy_limits_2 0x1660 v1.1
-- f ths_trail 0 3
-- f tclk_trail_min 4 7
-dphy_limits_3 0x1661 v1.1
-- f tclk_prepare 0 3
-- f tclk_zero 4 7
-dphy_limits_4 0x1662 v1.1
-- f tclk_post 0 3
-- f tlpx 4 7
-dphy_limits_5 0x1663 v1.1
-- f ths_exit 0 3
-- f twakeup 4 7
-dphy_limits_6 0x1664 v1.1
-- f tinit 0 3
-cphy_limits_1 0x1665 v1.1
-- f t3_prepare_max 0 3
-- f t3_lpx_max 4 7
-cphy_limits_2 0x1666 v1.1
-- f ths_exit_max 0 3
-- f twakeup_max 4 7
-cphy_limits_3 0x1667 v1.1
-- f tinit_max 0 3
-
-# binning capability registers
-min_frame_length_lines_bin 0x1700 16
-max_frame_length_lines_bin 0x1702 16
-min_line_length_pck_bin 0x1704 16
-max_line_length_pck_bin 0x1706 16
-min_line_blanking_pck_bin 0x1708 16
-fine_integration_time_min_bin 0x170a 16
-fine_integration_time_max_margin_bin 0x170c 16
-binning_capability 0x1710
-- e unsupported 0
-- e binning_then_subsampling 1
-- e subsampling_then_binning 2
-binning_weighting_capability 0x1711
-- b averaged 0
-- b summed 1
-- b bayer_corrected 2
-- b module_specific_weight 3
-binning_sub_types 0x1712
-binning_sub_type(n) 0x1713
-- l n 0 63 1
-- f row 0 3
-- f column 4 7
-binning_weighting_mono_capability 0x1771 v1.1
-- b averaged 0
-- b summed 1
-- b bayer_corrected 2
-- b module_specific_weight 3
-binning_sub_types_mono 0x1772 v1.1
-binning_sub_type_mono(n) 0x1773 v1.1 f
-- l n 0 63 1
-
-# data transfer interface capability registers
-data_transfer_if_capability 0x1800
-- b supported 0
-- b polling 2
-
-# sensor correction capability registers
-shading_correction_capability 0x1900
-- b color_shading 0
-- b luminance_correction 1
-green_imbalance_capability 0x1901
-- b supported 0
-module_specific_correction_capability 0x1903
-defect_correction_capability 0x1904 16
-- b mapped_defect 0
-- b dynamic_couplet 2
-- b dynamic_single 5
-- b combined_dynamic 8
-defect_correction_capability_2 0x1906 16
-- b dynamic_triplet 3
-nf_capability 0x1908
-- b luma 0
-- b chroma 1
-- b combined 2
-
-# optical black readout capability registers
-ob_readout_capability 0x1980
-- b controllable_readout 0
-- b visible_pixel_readout 1
-- b different_vc_readout 2
-- b different_dt_readout 3
-- b prog_data_format 4
-
-# color feedback capability registers
-color_feedback_capability 0x1987
-- b kelvin 0
-- b awb_gain 1
-
-# cfa pattern capability registers
-CFA_pattern_capability 0x1990 v1.1
-- e bayer 0
-- e monochrome 1
-- e 4x4_quad_bayer 2
-- e vendor_specific 3
-CFA_pattern_conversion_capability 0x1991 v1.1
-- b bayer 0
-
-# timer capability registers
-flash_mode_capability 0x1a02
-- b single_strobe 0
-sa_strobe_mode_capability 0x1a03
-- b fixed_width 0
-- b edge_ctrl 1
-
-# soft reset capability registers
-reset_max_delay 0x1a10 v1.1
-reset_min_time 0x1a11 v1.1
-
-# pdaf capability registers
-pdaf_capability_1 0x1b80
-- b supported 0
-- b processed_bottom_embedded 1
-- b processed_interleaved 2
-- b raw_bottom_embedded 3
-- b raw_interleaved 4
-- b visible_pdaf_correction 5
-- b vc_interleaving 6
-- b dt_interleaving 7
-pdaf_capability_2 0x1b81
-- b ROI 0
-- b after_digital_crop 1
-- b ctrl_retimed 2
-
-# bracketing interface capability registers
-bracketing_lut_capability_1 0x1c00
-- b coarse_integration 0
-- b global_analog_gain 1
-- b flash 4
-- b global_digital_gain 5
-- b alternate_global_analog_gain 6
-bracketing_lut_capability_2 0x1c01
-- b single_bracketing_mode 0
-- b looped_bracketing_mode 1
-bracketing_lut_size 0x1c02
Register definition generator
-----------------------------
-The ccs-regs.txt file contains MIPI CCS register definitions that are used
+The ccs-regs.asc file contains MIPI CCS register definitions that are used
to produce C source code files for definitions that can be better used by
programs written in C language. As there are many dependencies between the
produced files, please do not modify them manually as it's error-prone and
-e drivers/media/i2c/ccs/ccs-regs.h \
-L drivers/media/i2c/ccs/ccs-limits.h \
-l drivers/media/i2c/ccs/ccs-limits.c \
- -c Documentation/driver-api/media/drivers/ccs/ccs-regs.txt
+ -c Documentation/driver-api/media/drivers/ccs/ccs-regs.asc
**Copyright** |copy| 2020 Intel Corporation
use Getopt::Long qw(:config no_ignore_case);
use File::Basename;
-my $ccsregs = "ccs-regs.txt";
+my $ccsregs = "ccs-regs.asc";
my $header;
my $regarray;
my $limitc;
print <<EOH
$0 - Create CCS register definitions for C
-usage: $0 -c ccs-regs.txt -e header -r regarray -l limit-c -L limit-header [-k]
+usage: $0 -c ccs-regs.asc -e header -r regarray -l limit-c -L limit-header [-k]
-c ccs register file
-e header file name
projects / linux.git / commitdiff