arm64: dts: imx8mm: Deduplicate PCIe clock-names property

Move the PCIe clock-names property from various DTs into SoC dtsi to
reduce duplication. In case of a couple of boards, reorder the clock
so they match the order in yaml DT bindings.

Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com> # imx8mm.dtsi, imx8mm-tqma8mqml-mba8mx.dts
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
index 03266bd90a06baa86204491021f6b08a9806a3c8..f3cb7e27799e740a67739926c24d00c6d8884c18 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
@@ -241,9 +241,8 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pcie0>;
        reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
-       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
-                <&pcie0_refclk_gated>;
-       clock-names = "pcie", "pcie_aux", "pcie_bus";
+       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk_gated>,
+                <&clk IMX8MM_CLK_PCIE1_AUX>;
        assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
                          <&clk IMX8MM_CLK_PCIE1_CTRL>;
        assigned-clock-rates = <10000000>, <250000000>;

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts
index 24f61db33eba2a7b0f14adc55e87466a0dae0213..b337af03dacf256ed78f54da2ed097ada0fe60a4 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts
@@ -904,9 +904,8 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pcie0>;
        reset-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>;
-       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
-                <&pcieclk 0>;
-       clock-names = "pcie", "pcie_aux", "pcie_bus";
+       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcieclk 0>,
+                <&clk IMX8MM_CLK_PCIE1_AUX>;
        assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
                          <&clk IMX8MM_CLK_PCIE1_CTRL>;
        assigned-clock-rates = <10000000>, <250000000>;

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
index e0b604ac0da4f34bc75a626c406719512491bb61..0ce3005d578d2270178227e74e37bd95da33aee4 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
@@ -360,9 +360,8 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pcie0>;
        reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
-       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
-                <&pcie0_refclk>;
-       clock-names = "pcie", "pcie_aux", "pcie_bus";
+       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
+                <&clk IMX8MM_CLK_PCIE1_AUX>;
        assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
                          <&clk IMX8MM_CLK_PCIE1_CTRL>;
        assigned-clock-rates = <10000000>, <250000000>;

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi
index 44e87b1568e79b6ecc1dd4a09ad489f7ae45cf4e..299752aa827724f6037ae7209b38ea1706807f51 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi
@@ -210,9 +210,6 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pcie0>;
        reset-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>;
-       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_PHY>,
-                <&clk IMX8MM_CLK_PCIE1_AUX>;
-       clock-names = "pcie", "pcie_bus", "pcie_aux";
        fsl,max-link-speed = <1>;
        assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, <&clk IMX8MM_CLK_PCIE1_CTRL>;
        assigned-clock-rates = <10000000>, <250000000>;

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts
index 4a3df2b77b0bedc8d1b3dbf2e57070151d8bcaa0..266129b4a70d980a87be011b906c20d1d470478e 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts
@@ -175,9 +175,6 @@
        assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
                                 <&clk IMX8MM_SYS_PLL2_250M>;
        assigned-clock-rates = <10000000>, <250000000>;
-       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
-                <&clk IMX8MM_CLK_PCIE1_PHY>;
-       clock-names = "pcie", "pcie_aux", "pcie_bus";
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pcie>;
        reset-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>;

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts
index a0aeac61992996bf56bf741ef1dcd21ca7898a14..156d793a0c97236e44b1609494460d0ebdf3cb07 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts
@@ -79,9 +79,8 @@
 
 &pcie0 {
        reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>;
-       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
-               <&pcie0_refclk>;
-       clock-names = "pcie", "pcie_aux", "pcie_bus";
+       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
+                <&clk IMX8MM_CLK_PCIE1_AUX>;
        assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
                                <&clk IMX8MM_CLK_PCIE1_CTRL>;
        assigned-clock-rates = <10000000>, <250000000>;

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
index c557dbf4dcd609e22f879ef8b41e5b5c4d14909e..0ce60ad9c7d50fd0e8043a7739610cd66056bfff 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
@@ -120,9 +120,8 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pcie0>;
        reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
-       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
-                <&pcie0_refclk>;
-       clock-names = "pcie", "pcie_aux", "pcie_bus";
+       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
+                <&clk IMX8MM_CLK_PCIE1_AUX>;
        assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
                          <&clk IMX8MM_CLK_PCIE1_CTRL>;
        assigned-clock-rates = <10000000>, <250000000>;

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi
index 41d0de6a7027bbecf44e8f73e603c30d6bff0df8..570992a52b75960484567c1124f0dfb02a05f301 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi
@@ -142,9 +142,8 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pcie0>;
        reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
-       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
-                <&pcie0_refclk>;
-       clock-names = "pcie", "pcie_aux", "pcie_bus";
+       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
+                <&clk IMX8MM_CLK_PCIE1_AUX>;
        assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
                          <&clk IMX8MM_CLK_PCIE1_CTRL>;
        assigned-clock-rates = <10000000>, <250000000>;

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi
index 244ef8d6cc688ccd0211820df60bf65e4b1320ce..47ba0be554fa25fd0bb07e396cb4ebb528e9158b 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi
@@ -162,9 +162,8 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pcie0>;
        reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
-       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
-                <&pcie0_refclk>;
-       clock-names = "pcie", "pcie_aux", "pcie_bus";
+       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
+                <&clk IMX8MM_CLK_PCIE1_AUX>;
        assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
                          <&clk IMX8MM_CLK_PCIE1_CTRL>;
        assigned-clock-rates = <10000000>, <250000000>;

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
index 750a1f07ecb7a67ff17b4dc69a11e5d5424ad1b3..2bd117cefef849a15bca7ef86a2340f03538bcd6 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
@@ -702,9 +702,8 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pcie0>;
        reset-gpio = <&gpio5 2 GPIO_ACTIVE_LOW>;
-       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
-                <&pcie0_refclk>;
-       clock-names = "pcie", "pcie_aux", "pcie_bus";
+       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
+                <&clk IMX8MM_CLK_PCIE1_AUX>;
        assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
                          <&clk IMX8MM_CLK_PCIE1_CTRL>;
        assigned-clock-rates = <10000000>, <250000000>;

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts
index 32872b0b1aaf33c30ce1eb1e24cd58eedcc50017..feae2198654176ecf1b8610e8c9ded30c2308284 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts
@@ -623,9 +623,8 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pcie0>;
        reset-gpio = <&gpio4 5 GPIO_ACTIVE_LOW>;
-       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
-                <&pcie0_refclk>;
-       clock-names = "pcie", "pcie_aux", "pcie_bus";
+       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
+                <&clk IMX8MM_CLK_PCIE1_AUX>;
        assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
                          <&clk IMX8MM_CLK_PCIE1_CTRL>;
        assigned-clock-rates = <10000000>, <250000000>;

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts
index 8ce562246a08ecfbb4d2fabf96520f43993998cd..e7c79a82ab33d99f0338978250ca936f98f2f022 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts
@@ -557,9 +557,8 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pcie0>;
        reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>;
-       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
-                <&pcie0_refclk>;
-       clock-names = "pcie", "pcie_aux", "pcie_bus";
+       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
+                <&clk IMX8MM_CLK_PCIE1_AUX>;
        assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
                          <&clk IMX8MM_CLK_PCIE1_CTRL>;
        assigned-clock-rates = <10000000>, <250000000>;

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts
index eceed9816f5dc1ebb9861439d0d3daad851ae63a..93088fa1c3b9c9948d7477ef804db51fadea395f 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts
@@ -618,9 +618,8 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pcie0>;
        reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>;
-       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
-                <&pcie0_refclk>;
-       clock-names = "pcie", "pcie_aux", "pcie_bus";
+       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
+                <&clk IMX8MM_CLK_PCIE1_AUX>;
        assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
                          <&clk IMX8MM_CLK_PCIE1_CTRL>;
        assigned-clock-rates = <10000000>, <250000000>;

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
index 7e8b3b0fa306626ef63c9f4dacf385c318e2042b..5b2493bb8dd9376f50597de3d343a0f3136b7883 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
@@ -657,10 +657,6 @@
        assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
                                 <&clk IMX8MM_SYS_PLL2_250M>;
        assigned-clock-rates = <10000000>, <250000000>;
-       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
-                <&clk IMX8MM_CLK_PCIE1_AUX>,
-                <&clk IMX8MM_CLK_PCIE1_PHY>;
-       clock-names = "pcie", "pcie_aux", "pcie_bus";
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pcie0>;
        /* PCIE_1_RESET# (SODIMM 244) */

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 04cf2c3c9928bb58ee704c3acc0b05be549bcc3c..31f4548f85cfa544921b00a0f1568a7062af4a6d 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1302,6 +1302,10 @@
                                        <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
                        fsl,max-link-speed = <2>;
                        linux,pci-domain = <0>;
+                       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
+                                <&clk IMX8MM_CLK_PCIE1_PHY>,
+                                <&clk IMX8MM_CLK_PCIE1_AUX>;
+                       clock-names = "pcie", "pcie_bus", "pcie_aux";
                        power-domains = <&pgc_pcie>;
                        resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
                                 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;