arm64: dts: qcom: sa8775p: Add PCIe bridge node

On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-8-1eb790c53e43@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 231cea1f0fa8f46d890146ed8d7f469bbf40d210..31de73594839097da9cadf21c3fb74385537be7e 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -3677,6 +3677,16 @@
                phy-names = "pciephy";
 
                status = "disabled";
+
+               pcie@0 {
+                       device_type = "pci";
+                       reg = <0x0 0x0 0x0 0x0 0x0>;
+                       bus-range = <0x01 0xff>;
+
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       ranges;
+               };
        };
 
        pcie0_phy: phy@1c04000 {
@@ -3777,6 +3787,16 @@
                phy-names = "pciephy";
 
                status = "disabled";
+
+               pcie@0 {
+                       device_type = "pci";
+                       reg = <0x0 0x0 0x0 0x0 0x0>;
+                       bus-range = <0x01 0xff>;
+
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       ranges;
+               };
        };
 
        pcie1_phy: phy@1c14000 {