&s->pchip.reg_mem, &s->pchip.reg_io,
0, 64, TYPE_PCI_BUS);
phb->bus = b;
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
/* Host memory as seen from the PCI side, via the IOMMU. */
memory_region_init_iommu(&s->pchip.iommu, sizeof(s->pchip.iommu),
qdev_prop_set_uint8(dev, "rd_q_dep", 8);
qdev_prop_set_uint8(dev, "data_width", width);
qdev_prop_set_uint16(dev, "data_buffer_dep", width);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, base);
object_property_set_int(OBJECT(orgate), nevents + 1, "num-lines",
for (i = 0; i < EXYNOS4210_NCPUS; i++) {
dev = qdev_new("exynos4210.irq_gate");
qdev_prop_set_uint32(dev, "n_in", EXYNOS4210_IRQ_GATE_NINPUTS);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
/* Get IRQ Gate input in gate_irq */
for (n = 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) {
gate_irq[i][n] = qdev_get_gpio_in(dev, n);
/* Private memory region and Internal GIC */
dev = qdev_new(TYPE_A9MPCORE_PRIV);
qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR);
for (n = 0; n < EXYNOS4210_NCPUS; n++) {
sysbus_connect_irq(busdev, n, gate_irq[n][0]);
/* External GIC */
dev = qdev_new("exynos4210.gic");
qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(busdev, &error_fatal);
/* Map CPU interface */
sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR);
/* Map Distributer interface */
/* Internal Interrupt Combiner */
dev = qdev_new("exynos4210.combiner");
- qdev_realize_and_unref(dev, NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(busdev, &error_fatal);
for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
sysbus_connect_irq(busdev, n, s->irqs.int_gic_irq[n]);
}
/* External Interrupt Combiner */
dev = qdev_new("exynos4210.combiner");
qdev_prop_set_uint32(dev, "external", 1);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(busdev, &error_fatal);
for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]);
}
/* Multi Core Timer */
dev = qdev_new("exynos4210.mct");
- qdev_realize_and_unref(dev, NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(busdev, &error_fatal);
for (n = 0; n < 4; n++) {
/* Connect global timer interrupts to Combiner gpio_in */
sysbus_connect_irq(busdev, n,
}
dev = qdev_new("exynos4210.i2c");
- qdev_realize_and_unref(dev, NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_connect_irq(busdev, 0, i2c_irq);
sysbus_mmio_map(busdev, 0, addr);
s->i2c_if[n] = (I2CBus *)qdev_get_child_bus(dev, "i2c");
*/
dev = qdev_new(TYPE_S3C_SDHCI);
qdev_prop_set_uint64(dev, "capareg", EXYNOS4210_SDHCI_CAPABILITIES);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, EXYNOS4210_SDHCI_ADDR(n));
sysbus_connect_irq(busdev, 0, s->irq_table[exynos4210_get_irq(29, n)]);
dev = qdev_new(TYPE_LAN9118);
qdev_set_nic_properties(dev, &nd_table[0]);
qdev_prop_set_uint32(dev, "mode_16bit", 1);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, base);
sysbus_connect_irq(s, 0, irq);
}
switch (machine_id) {
case CALXEDA_HIGHBANK:
dev = qdev_new("l2x0");
- qdev_realize_and_unref(dev, NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, 0xfff12000);
dev = qdev_new(TYPE_A9MPCORE_PRIV);
}
qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
for (n = 0; n < smp_cpus; n++) {
sysbus_connect_irq(busdev, n, cpu_irq[n]);
dev = qdev_new("sp804");
qdev_prop_set_uint32(dev, "freq0", 150000000);
qdev_prop_set_uint32(dev, "freq1", 150000000);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, 0xfff34000);
sysbus_connect_irq(busdev, 0, pic[18]);
pl011_create(0xfff36000, pic[20], serial_hd(0));
dev = qdev_new(TYPE_HIGHBANK_REGISTERS);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, 0xfff3c000);
sysbus_create_simple("pl061", 0xfff30000, pic[14]);
qemu_check_nic_model(&nd_table[0], "xgmac");
dev = qdev_new("xgmac");
qdev_set_nic_properties(dev, &nd_table[0]);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff50000);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[77]);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[78]);
qemu_check_nic_model(&nd_table[1], "xgmac");
dev = qdev_new("xgmac");
qdev_set_nic_properties(dev, &nd_table[1]);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff51000);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[80]);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[81]);
dev = qdev_new(TYPE_INTEGRATOR_CM);
qdev_prop_set_uint32(dev, "memsz", ram_size >> 20);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000);
dev = sysbus_create_varargs(TYPE_INTEGRATOR_PIC, 0x14000000,
qemu_check_nic_model(nd, "lan9118");
mms->lan9118 = qdev_new(TYPE_LAN9118);
qdev_set_nic_properties(mms->lan9118, nd);
- qdev_realize_and_unref(mms->lan9118, NULL, &error_fatal);
s = SYS_BUS_DEVICE(mms->lan9118);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 16));
return sysbus_mmio_get_region(s, 0);
}
qdev_prop_set_uint32(dev, "apb0div", 2);
qdev_prop_set_uint32(dev, "apb1div", 2);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
soc = MSF2_SOC(dev);
qemu_check_nic_model(&nd_table[0], "mv88w8618");
dev = qdev_new(TYPE_MV88W8618_ETH);
qdev_set_nic_properties(dev, &nd_table[0]);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, MP_ETH_BASE);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[MP_ETH_IRQ]);
s = SYS_BUS_DEVICE(dev);
object_property_set_link(OBJECT(dev), OBJECT(wm8750_dev),
"wm8750", NULL);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, MP_AUDIO_BASE);
sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]);
dev = qdev_new(TYPE_STM32F205_SOC);
qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"));
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
FLASH_SIZE);
dev = qdev_new(TYPE_STM32F405_SOC);
qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
armv7m_load_kernel(ARM_CPU(first_cpu),
machine->kernel_filename,
qdev_prop_set_drive(s->nand, "drive", blk_by_legacy_dinfo(dinfo),
&error_fatal);
}
- qdev_realize_and_unref(s->nand, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(s->nand), &error_fatal);
sysbus_connect_irq(SYS_BUS_DEVICE(s->nand), 0,
qdev_get_gpio_in(s->mpu->gpio, N8X0_ONENAND_GPIO));
omap_gpmc_attach(s->mpu->gpmc, N8X0_ONENAND_CS,
SysBusDevice *dev;
s->usb = qdev_new("tusb6010");
dev = SYS_BUS_DEVICE(s->usb);
- qdev_realize_and_unref(s->usb, NULL, &error_fatal);
+ sysbus_realize_and_unref(dev, &error_fatal);
sysbus_connect_irq(dev, 0,
qdev_get_gpio_in(s->mpu->gpio, N8X0_TUSB_INT_GPIO));
/* Using the NOR interface */
s->ih[0] = qdev_new("omap-intc");
qdev_prop_set_uint32(s->ih[0], "size", 0x100);
omap_intc_set_iclk(OMAP_INTC(s->ih[0]), omap_findclk(s, "arminth_ck"));
- qdev_realize_and_unref(s->ih[0], NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(s->ih[0]);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_connect_irq(busdev, 0,
qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
sysbus_connect_irq(busdev, 1,
s->ih[1] = qdev_new("omap-intc");
qdev_prop_set_uint32(s->ih[1], "size", 0x800);
omap_intc_set_iclk(OMAP_INTC(s->ih[1]), omap_findclk(s, "arminth_ck"));
- qdev_realize_and_unref(s->ih[1], NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(s->ih[1]);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_connect_irq(busdev, 0,
qdev_get_gpio_in(s->ih[0], OMAP_INT_15XX_IH2_IRQ));
/* The second interrupt controller's FIQ output is not wired up */
s->gpio = qdev_new("omap-gpio");
qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model);
omap_gpio_set_clk(OMAP1_GPIO(s->gpio), omap_findclk(s, "arm_gpio_ck"));
- qdev_realize_and_unref(s->gpio, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(s->gpio), &error_fatal);
sysbus_connect_irq(SYS_BUS_DEVICE(s->gpio), 0,
qdev_get_gpio_in(s->ih[0], OMAP_INT_GPIO_BANK1));
sysbus_mmio_map(SYS_BUS_DEVICE(s->gpio), 0, 0xfffce000);
s->i2c[0] = qdev_new("omap_i2c");
qdev_prop_set_uint8(s->i2c[0], "revision", 0x11);
omap_i2c_set_fclk(OMAP_I2C(s->i2c[0]), omap_findclk(s, "mpuper_ck"));
- qdev_realize_and_unref(s->i2c[0], NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(s->i2c[0]);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(s->ih[1], OMAP_INT_I2C));
sysbus_connect_irq(busdev, 1, s->drq[OMAP_DMA_I2C_TX]);
sysbus_connect_irq(busdev, 2, s->drq[OMAP_DMA_I2C_RX]);
qdev_prop_set_uint8(s->ih[0], "revision", 0x21);
omap_intc_set_fclk(OMAP_INTC(s->ih[0]), omap_findclk(s, "mpu_intc_fclk"));
omap_intc_set_iclk(OMAP_INTC(s->ih[0]), omap_findclk(s, "mpu_intc_iclk"));
- qdev_realize_and_unref(s->ih[0], NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(s->ih[0]);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_connect_irq(busdev, 0,
qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
sysbus_connect_irq(busdev, 1,
qdev_prop_set_uint8(s->i2c[0], "revision", 0x34);
omap_i2c_set_iclk(OMAP_I2C(s->i2c[0]), omap_findclk(s, "i2c1.iclk"));
omap_i2c_set_fclk(OMAP_I2C(s->i2c[0]), omap_findclk(s, "i2c1.fclk"));
- qdev_realize_and_unref(s->i2c[0], NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(s->i2c[0]);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_connect_irq(busdev, 0,
qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_I2C1_IRQ));
sysbus_connect_irq(busdev, 1, s->drq[OMAP24XX_DMA_I2C1_TX]);
qdev_prop_set_uint8(s->i2c[1], "revision", 0x34);
omap_i2c_set_iclk(OMAP_I2C(s->i2c[1]), omap_findclk(s, "i2c2.iclk"));
omap_i2c_set_fclk(OMAP_I2C(s->i2c[1]), omap_findclk(s, "i2c2.fclk"));
- qdev_realize_and_unref(s->i2c[1], NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(s->i2c[1]);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_connect_irq(busdev, 0,
qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_I2C2_IRQ));
sysbus_connect_irq(busdev, 1, s->drq[OMAP24XX_DMA_I2C2_TX]);
omap2_gpio_set_fclk(OMAP2_GPIO(s->gpio), 4,
omap_findclk(s, "gpio5_dbclk"));
}
- qdev_realize_and_unref(s->gpio, NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(s->gpio);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_connect_irq(busdev, 0,
qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK1));
sysbus_connect_irq(busdev, 3,
dev = qdev_new(TYPE_PXA2XX_I2C);
qdev_prop_set_uint32(dev, "size", region_size + 1);
qdev_prop_set_uint32(dev, "offset", base & region_size);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
i2c_dev = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(i2c_dev, &error_fatal);
sysbus_mmio_map(i2c_dev, 0, base & ~region_size);
sysbus_connect_irq(i2c_dev, 0, irq);
dev = qdev_new(TYPE_PXA2XX_FIR);
qdev_prop_set_chr(dev, "chardev", chr);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
sbd = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(sbd, &error_fatal);
sysbus_mmio_map(sbd, 0, base);
sysbus_connect_irq(sbd, 0, irq);
sysbus_connect_irq(sbd, 1, rx_dma);
dev = qdev_new(TYPE_PXA2XX_GPIO);
qdev_prop_set_int32(dev, "lines", lines);
qdev_prop_set_int32(dev, "ncpu", cs->cpu_index);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
s->is_fiq[0] = 0;
s->is_fiq[1] = 0;
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
qdev_init_gpio_in(dev, pxa2xx_pic_set_irq, PXA2XX_PIC_SRCS);
sysctl = qdev_new("realview_sysctl");
qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
qdev_prop_set_uint32(sysctl, "proc_id", proc_id);
- qdev_realize_and_unref(sysctl, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(sysctl), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000);
if (is_mpcore) {
dev = qdev_new(is_pb ? TYPE_A9MPCORE_PRIV : "realview_mpcore");
qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, periphbase);
for (n = 0; n < smp_cpus; n++) {
sysbus_connect_irq(busdev, n, cpu_irq[n]);
pl041 = qdev_new("pl041");
qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
- qdev_realize_and_unref(pl041, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(pl041), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, 0x10004000);
sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[19]);
dev = qdev_new("pl081");
object_property_set_link(OBJECT(dev), OBJECT(sysmem), "downstream",
&error_fatal);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, 0x10030000);
sysbus_connect_irq(busdev, 0, pic[24]);
if (!is_pb) {
dev = qdev_new("realview_pci");
busdev = SYS_BUS_DEVICE(dev);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, 0x10019000); /* PCI controller registers */
sysbus_mmio_map(busdev, 1, 0x60000000); /* PCI self-config */
sysbus_mmio_map(busdev, 2, 0x61000000); /* PCI config */
assert(QEMU_IS_ALIGNED(size, SBSA_FLASH_SECTOR_SIZE));
assert(size / SBSA_FLASH_SECTOR_SIZE <= UINT32_MAX);
qdev_prop_set_uint32(dev, "num-blocks", size / SBSA_FLASH_SECTOR_SIZE);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
memory_region_add_subregion(sysmem, base,
sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
qdev_prop_set_uint32(sms->gic, "len-redist-region-count", 1);
qdev_prop_set_uint32(sms->gic, "redist-region-count[0]", redist0_count);
- qdev_realize_and_unref(sms->gic, NULL, &error_fatal);
gicbusdev = SYS_BUS_DEVICE(sms->gic);
+ sysbus_realize_and_unref(gicbusdev, &error_fatal);
sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base);
sysbus_mmio_map(gicbusdev, 1, sbsa_ref_memmap[SBSA_GIC_REDIST].base);
SysBusDevice *s = SYS_BUS_DEVICE(dev);
qdev_prop_set_chr(dev, "chardev", chr);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
memory_region_add_subregion(mem, base,
sysbus_mmio_get_region(s, 0));
sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq));
dev = qdev_new("sysbus-ahci");
qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq));
object_property_set_link(OBJECT(dev), OBJECT(bus), "primary-bus",
&error_abort);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
for (i = 0; i < NUM_SMMU_IRQS; i++) {
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
int i;
dev = qdev_new(TYPE_GPEX_HOST);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
/* Map ECAM space */
ecam_alias = g_new0(MemoryRegion, 1);
else if (size == FLASH_1024M)
qdev_prop_set_uint8(dev, "chip_id", 0xf1);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, FLASH_BASE);
}
object_property_set_link(OBJECT(nvic), OBJECT(get_system_memory()),
"memory", &error_abort);
/* This will exit with an error if the user passed us a bad cpu_type */
- qdev_realize_and_unref(nvic, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(nvic), &error_fatal);
qdev_connect_gpio_out_named(nvic, "SYSRESETREQ", 0,
qemu_allocate_irq(&do_sys_reset, NULL, 0));
uint32_t mainclk = NANOSECONDS_PER_SECOND / system_clock_scale;
qdev_prop_set_uint32(dev, "wdogclk-frq", mainclk);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev),
0,
0x40000000u);
enet = qdev_new("stellaris_enet");
qdev_set_nic_properties(enet, &nd_table[0]);
- qdev_realize_and_unref(enet, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(enet), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000);
sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, qdev_get_gpio_in(nvic, 42));
}
int i;
dev = qdev_new(TYPE_STRONGARM_GPIO);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
for (i = 0; i < 12; i++)
for (i = 0; sa_serial[i].io_base; i++) {
DeviceState *dev = qdev_new(TYPE_STRONGARM_UART);
qdev_prop_set_chr(dev, "chardev", serial_hd(i));
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0,
sa_serial[i].io_base);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
sysctl = qdev_new("realview_sysctl");
qdev_prop_set_uint32(sysctl, "sys_id", 0x41007004);
qdev_prop_set_uint32(sysctl, "proc_id", 0x02000000);
- qdev_realize_and_unref(sysctl, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(sysctl), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000);
dev = sysbus_create_varargs("pl190", 0x10140000,
dev = qdev_new("versatile_pci");
busdev = SYS_BUS_DEVICE(dev);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, 0x10001000); /* PCI controller regs */
sysbus_mmio_map(busdev, 1, 0x41000000); /* PCI self-config */
sysbus_mmio_map(busdev, 2, 0x42000000); /* PCI config */
dev = qdev_new("pl080");
object_property_set_link(OBJECT(dev), OBJECT(sysmem), "downstream",
&error_fatal);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, 0x10130000);
sysbus_connect_irq(busdev, 0, pic[17]);
/* Add PL041 AACI Interface to the LM4549 codec */
pl041 = qdev_new("pl041");
qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
- qdev_realize_and_unref(pl041, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(pl041), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, 0x10004000);
sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, sic[24]);
*/
dev = qdev_new(privdev);
qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, periphbase);
/* Interrupts [42:0] are from the motherboard;
qdev_prop_set_uint16(dev, "id2", 0x00);
qdev_prop_set_uint16(dev, "id3", 0x00);
qdev_prop_set_string(dev, "name", name);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
return PFLASH_CFI01(dev);
qdev_prop_set_uint32(sysctl, propname, daughterboard->clocks[i]);
g_free(propname);
}
- qdev_realize_and_unref(sysctl, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(sysctl), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]);
/* VE_SP810: not modelled */
pl041 = qdev_new("pl041");
qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
- qdev_realize_and_unref(pl041, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(pl041), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, map[VE_PL041]);
sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[11]);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq));
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
return dev;
}
object_property_set_link(OBJECT(dev), OBJECT(vms->gic), "parent-gicv3",
&error_abort);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base);
fdt_add_its_gic_node(vms);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base);
qdev_prop_set_uint32(dev, "base-spi", irq);
qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
for (i = 0; i < NUM_GICV2M_SPIS; i++) {
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
vms->virt);
}
}
- qdev_realize_and_unref(vms->gic, NULL, &error_fatal);
gicbusdev = SYS_BUS_DEVICE(vms->gic);
+ sysbus_realize_and_unref(gicbusdev, &error_fatal);
sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base);
if (type == 3) {
sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base);
SysBusDevice *s = SYS_BUS_DEVICE(dev);
qdev_prop_set_chr(dev, "chardev", chr);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
memory_region_add_subregion(mem, base,
sysbus_mmio_get_region(s, 0));
sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq));
assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE));
assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
memory_region_add_subregion(sysmem, base,
sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
object_property_set_link(OBJECT(dev), OBJECT(bus), "primary-bus",
&error_abort);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
for (i = 0; i < NUM_SMMU_IRQS; i++) {
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
PCIHostState *pci;
dev = qdev_new(TYPE_GPEX_HOST);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
ecam_id = VIRT_ECAM_ID(vms->highmem_ecam);
base_ecam = vms->memmap[ecam_id].base;
dev->id = TYPE_PLATFORM_BUS_DEVICE;
qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS);
qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
vms->platform_bus_dev = dev;
s = SYS_BUS_DEVICE(dev);
qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
qdev_set_nic_properties(dev, nd);
}
- qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, base);
sysbus_connect_irq(s, 0, irq);
}
qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1);
qdev_prop_set_uint8(dev, "num-ss-bits", num_ss);
qdev_prop_set_uint8(dev, "num-busses", num_busses);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, base_addr);
if (is_qspi) {
sysbus_mmio_map(busdev, 1, 0xFC000000);
/* Create slcr, keep a pointer to connect clocks */
slcr = qdev_new("xilinx,zynq_slcr");
- qdev_realize_and_unref(slcr, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(slcr), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000);
/* Create the main clock source, and feed slcr with it */
dev = qdev_new(TYPE_A9MPCORE_PRIV);
qdev_prop_set_uint32(dev, "num-cpu", 1);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
sysbus_connect_irq(busdev, 0,
qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
dev = qdev_new(TYPE_SYSBUS_SDHCI);
qdev_prop_set_uint8(dev, "sd-spec-version", 2);
qdev_prop_set_uint64(dev, "capareg", ZYNQ_SDHCI_CAPABILITIES);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, hci_addr);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[hci_irq - IRQ_OFFSET]);
}
dev = qdev_new(TYPE_ZYNQ_XADC);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8007100);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-IRQ_OFFSET]);
qdev_prop_set_uint8(dev, "rd_q_dep", 16);
qdev_prop_set_uint16(dev, "data_buffer_dep", 256);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, 0xF8003000);
sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]); /* abort irq line */
for (n = 0; n < ARRAY_SIZE(dma_irqs); ++n) { /* event irqs */
}
dev = qdev_new("xlnx.ps7-dev-cfg");
- qdev_realize_and_unref(dev, NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_connect_irq(busdev, 0, pic[40 - IRQ_OFFSET]);
sysbus_mmio_map(busdev, 0, 0xF8007000);
pic_irq = qdev_get_gpio_in(DEVICE(&s->soc.fpd.apu.gic), irq);
dev = qdev_new("virtio-mmio");
object_property_add_child(OBJECT(&s->soc), name, OBJECT(dev));
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic_irq);
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
memory_region_add_subregion(&s->soc.mr_ps, base, mr);
qdev_prop_set_string(dev, "name", name);
qdev_prop_set_uint64(dev, "size", size);
object_property_add_child(OBJECT(s), name, OBJECT(dev));
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
mr_dev = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
memory_region_add_subregion(mr, base, mr_dev);
qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fds[1]),
&error_fatal);
}
- qdev_realize_and_unref(dev, NULL, &error_fatal);
sbd = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(sbd, &error_fatal);
sysbus_connect_irq(sbd, 0, irq);
sysbus_mmio_map(sbd, 0, mmio_base);
}
qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(fds[0]),
&error_fatal);
}
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sys = SYSBUS_FDC(dev);
sysbus_connect_irq(SYS_BUS_DEVICE(sys), 0, irq);
sysbus_mmio_map(SYS_BUS_DEVICE(sys), 0, io_base);
qdev_prop_set_uint16(dev, "id2", id2);
qdev_prop_set_uint16(dev, "id3", id3);
qdev_prop_set_string(dev, "name", name);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
return PFLASH_CFI01(dev);
qdev_prop_set_uint16(dev, "unlock-addr0", unlock_addr0);
qdev_prop_set_uint16(dev, "unlock-addr1", unlock_addr1);
qdev_prop_set_string(dev, "name", name);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
return PFLASH_CFI02(dev);
qdev_prop_set_uint32(dev, "tx-size", fifo_size);
bus = SYS_BUS_DEVICE(dev);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(bus, &error_fatal);
if (addr != (hwaddr)-1) {
sysbus_mmio_map(bus, 0, addr);
}
if (chrdrv) {
qdev_prop_set_chr(dev, "chardev", chrdrv);
}
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
qdev_prop_set_chr(DEVICE(smm), "chardev", chr);
qdev_set_legacy_instance_id(DEVICE(smm), base, 2);
qdev_prop_set_uint8(DEVICE(smm), "endianness", end);
- qdev_realize_and_unref(DEVICE(smm), NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(smm), &error_fatal);
sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, irq);
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(smm), 0);
dev = qdev_new(name);
s = SYS_BUS_DEVICE(dev);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(s, &error_fatal);
if (addr != (hwaddr)-1) {
sysbus_mmio_map(s, 0, addr);
}
dev = qdev_new("etraxfs,pic");
- qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, 0x3001c000);
sysbus_connect_irq(s, 0, qdev_get_gpio_in(DEVICE(cpu), CRIS_CPU_IRQ));
sysbus_connect_irq(s, 1, qdev_get_gpio_in(DEVICE(cpu), CRIS_CPU_NMI));
XCloseDisplay(d);
dev = qdev_new(TYPE_MILKYMIST_TMU2);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
usb_dev = qdev_new("sysbus-ohci");
qdev_prop_set_uint32(usb_dev, "num-ports", 2);
qdev_prop_set_uint64(usb_dev, "dma-offset", s->base);
- qdev_realize_and_unref(usb_dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(usb_dev), &error_fatal);
memory_region_add_subregion(&s->state.mmio_region, SM501_USB_HOST,
sysbus_mmio_get_region(SYS_BUS_DEVICE(usb_dev), 0));
sysbus_pass_irq(sbd, SYS_BUS_DEVICE(usb_dev));
dev = qdev_new("pxa2xx-dma");
qdev_prop_set_int32(dev, "channels", PXA27X_DMA_NUM_CHANNELS);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
dev = qdev_new("pxa2xx-dma");
qdev_prop_set_int32(dev, "channels", PXA27X_DMA_NUM_CHANNELS);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
DeviceState *dev;
dev = qdev_new(TYPE_RC4030);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
*dmas = rc4030_allocate_dmas(dev, 4);
*dma_mr = &RC4030(dev)->dma_mr;
esp->dma_opaque = SPARC32_DMA_DEVICE(dev);
sysbus->it_shift = 2;
esp->dma_enabled = 1;
- qdev_realize_and_unref(d, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(d), &error_fatal);
}
static void sparc32_espdma_device_class_init(ObjectClass *klass, void *data)
object_property_add_child(OBJECT(dev), "lance", OBJECT(d));
qdev_set_nic_properties(d, nd);
object_property_set_link(OBJECT(d), OBJECT(dev), "dma", errp);
- qdev_realize_and_unref(d, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(d), &error_fatal);
}
static void sparc32_ledma_device_class_init(ObjectClass *klass, void *data)
espdma = qdev_new(TYPE_SPARC32_ESPDMA_DEVICE);
object_property_set_link(OBJECT(espdma), iommu, "iommu", errp);
object_property_add_child(OBJECT(s), "espdma", OBJECT(espdma));
- qdev_realize_and_unref(espdma, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(espdma), &error_fatal);
esp = DEVICE(object_resolve_path_component(OBJECT(espdma), "esp"));
sbd = SYS_BUS_DEVICE(esp);
ledma = qdev_new(TYPE_SPARC32_LEDMA_DEVICE);
object_property_set_link(OBJECT(ledma), iommu, "iommu", errp);
object_property_add_child(OBJECT(s), "ledma", OBJECT(ledma));
- qdev_realize_and_unref(ledma, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(ledma), &error_fatal);
lance = DEVICE(object_resolve_path_component(OBJECT(ledma), "lance"));
sbd = SYS_BUS_DEVICE(lance);
&s->pci_mem, get_system_io(),
PCI_DEVFN(0, 0), 32, TYPE_PCI_BUS);
s->parent_obj.bus = b;
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
/* Set up windows into PCI bus memory. */
for (i = 1; i < 31; i++) {
s, "lasi", 0x100000);
memory_region_add_subregion(address_space, LASI_HPA, &s->this_mem);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
/* LAN */
if (enable_lasi_lan()) {
/* Graphics setup. */
if (machine->enable_graphics && vga_interface_type != VGA_NONE) {
dev = qdev_new("artist");
- qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, LASI_GFX_HPA);
sysbus_mmio_map(s, 1, ARTIST_FB_ADDR);
}
if (!compat) {
qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
}
- qdev_realize_and_unref(hpet, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
for (i = 0; i < GSI_NUM_PINS; i++) {
object_property_set_int(OBJECT(q35_host), x86ms->above_4g_mem_size,
PCI_HOST_ABOVE_4G_MEM_SIZE, NULL);
/* pci */
- qdev_realize_and_unref(DEVICE(q35_host), NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(q35_host), &error_fatal);
phb = PCI_HOST_BRIDGE(q35_host);
host_bus = phb->bus;
/* create ISA bus */
total_size += size;
qdev_prop_set_uint32(DEVICE(system_flash), "num-blocks",
size / FLASH_SECTOR_SIZE);
- qdev_realize_and_unref(DEVICE(system_flash), NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(system_flash), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(system_flash), 0,
0x100000000ULL - total_size);
}
object_property_add_child(object_resolve_path(parent_name, NULL),
"ioapic", OBJECT(dev));
- qdev_realize_and_unref(dev, NULL, &error_fatal);
d = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(d, &error_fatal);
sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS);
for (i = 0; i < IOAPIC_NUM_PINS; i++) {
s->gic = qdev_new("arm_gic");
qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu);
qdev_prop_set_uint32(s->gic, "num-irq", EXYNOS4210_GIC_NIRQ);
- qdev_realize_and_unref(s->gic, NULL, &error_fatal);
gicbusdev = SYS_BUS_DEVICE(s->gic);
+ sysbus_realize_and_unref(gicbusdev, &error_fatal);
/* Pass through outbound IRQ lines from the GIC */
sysbus_pass_irq(sbd, gicbusdev);
object_property_add_child(qdev_get_machine(), TYPE_QEMU_S390_FLIC,
OBJECT(dev));
}
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
}
static int qemu_s390_register_io_adapter(S390FLICState *fs, uint32_t id,
}
if (!dev) {
dev = qdev_new("isabus-bridge");
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
}
isabus = ISA_BUS(qbus_create(TYPE_ISA_BUS, dev, NULL));
SysBusDevice *d;
dev = qdev_new("lm32-pic");
- qdev_realize_and_unref(dev, NULL, &error_fatal);
d = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(d, &error_fatal);
sysbus_connect_irq(d, 0, cpu_irq);
return dev;
dev = qdev_new(TYPE_LM32_JUART);
qdev_prop_set_chr(dev, "chardev", chr);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
return dev;
}
dev = qdev_new("lm32-uart");
s = SYS_BUS_DEVICE(dev);
qdev_prop_set_chr(dev, "chardev", chr);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, addr);
sysbus_connect_irq(s, 0, irq);
return dev;
dev = qdev_new("milkymist-uart");
qdev_prop_set_chr(dev, "chardev", chr);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
DeviceState *dev;
dev = qdev_new("milkymist-hpdmc");
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
return dev;
DeviceState *dev;
dev = qdev_new("milkymist-memcard");
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
return dev;
dev = qdev_new("milkymist-vgafb");
qdev_prop_set_uint32(dev, "fb_offset", fb_offset);
qdev_prop_set_uint32(dev, "fb_mask", fb_mask);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
return dev;
qdev_prop_set_uint32(dev, "systemid", system_id);
qdev_prop_set_uint32(dev, "capabilities", capabilities);
qdev_prop_set_uint32(dev, "gpio_strappings", gpio_strappings);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, gpio_irq);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, timer0_irq);
DeviceState *dev;
dev = qdev_new("milkymist-pfpu");
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
return dev;
DeviceState *dev;
dev = qdev_new("milkymist-ac97");
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, crrequest_irq);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, crreply_irq);
qemu_check_nic_model(&nd_table[0], "minimac2");
dev = qdev_new("milkymist-minimac2");
qdev_set_nic_properties(dev, &nd_table[0]);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, buffers_base);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, rx_irq);
dev = qdev_new("milkymist-softusb");
qdev_prop_set_uint32(dev, "pmem_size", pmem_size);
qdev_prop_set_uint32(dev, "dmem_size", dmem_size);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, pmem_base);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, dmem_base);
qemu_check_nic_model(nd, TYPE_MCF_FEC_NET);
dev = qdev_new(TYPE_MCF_FEC_NET);
qdev_set_nic_properties(dev, nd);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
for (i = 0; i < FEC_NUM_IRQ; i++) {
sysbus_connect_irq(s, i, irqs[i]);
}
mcf_intc_state *s;
dev = qdev_new(TYPE_MCF_INTC);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
s = MCF_INTC(dev);
s->cpu = cpu;
qdev_prop_set_chr(dev, "chrA", serial_hd(0));
qdev_prop_set_uint32(dev, "chnBtype", escc_serial);
qdev_prop_set_uint32(dev, "chnAtype", escc_serial);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_connect_irq(s, 0, ser_irq[0]);
sysbus_connect_irq(s, 1, ser_irq[1]);
sysbus_mmio_map(s, 0, 0x2118000);
/* Framebuffer */
dev = qdev_new(TYPE_NEXTFB);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x0B000000);
/* MMIO */
/* KBD */
dev = qdev_new(TYPE_NEXTKBD);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x0200e000);
/* Load ROM here */
qdev_prop_set_drive(via_dev, "drive", blk_by_legacy_dinfo(dinfo),
&error_abort);
}
- qdev_realize_and_unref(via_dev, NULL, &error_fatal);
sysbus = SYS_BUS_DEVICE(via_dev);
+ sysbus_realize_and_unref(sysbus, &error_fatal);
sysbus_mmio_map(sysbus, 0, VIA_BASE);
qdev_connect_gpio_out_named(DEVICE(sysbus), "irq", 0, pic[0]);
qdev_connect_gpio_out_named(DEVICE(sysbus), "irq", 1, pic[1]);
qdev_prop_set_bit(dev, "big_endian", true);
object_property_set_link(OBJECT(dev), OBJECT(get_system_memory()),
"dma_mr", &error_abort);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
sysbus = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(sysbus, &error_fatal);
sysbus_mmio_map(sysbus, 0, SONIC_BASE);
sysbus_mmio_map(sysbus, 1, SONIC_PROM_BASE);
sysbus_connect_irq(sysbus, 0, pic[2]);
qdev_prop_set_chr(dev, "chrB", serial_hd(1));
qdev_prop_set_uint32(dev, "chnBtype", 0);
qdev_prop_set_uint32(dev, "chnAtype", 0);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
sysbus = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(sysbus, &error_fatal);
sysbus_connect_irq(sysbus, 0, pic[3]);
sysbus_connect_irq(sysbus, 1, pic[3]);
sysbus_mmio_map(sysbus, 0, SCC_BASE);
esp->dma_opaque = NULL;
sysbus_esp->it_shift = 4;
esp->dma_enabled = 1;
- qdev_realize_and_unref(dev, NULL, &error_fatal);
sysbus = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(sysbus, &error_fatal);
sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in_named(via_dev,
"via2-irq",
VIA2_IRQ_SCSI_BIT));
/* SWIM floppy controller */
dev = qdev_new(TYPE_SWIM);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, SWIM_BASE);
/* NuBus */
dev = qdev_new(TYPE_MAC_NUBUS_BRIDGE);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, NUBUS_SUPER_SLOT_BASE);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, NUBUS_SLOT_BASE);
dev = qdev_new("xlnx.xps-intc");
qdev_prop_set_uint32(dev, "kind-of-intr", 1 << TIMER_IRQ);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
qdev_get_gpio_in(DEVICE(cpu), MB_CPU_IRQ));
dev = qdev_new("xlnx.xps-timer");
qdev_prop_set_uint32(dev, "one-timer-only", 0);
qdev_prop_set_uint32(dev, "clock-frequency", 100 * 1000000);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]);
"axistream-connected", &error_abort);
object_property_set_link(OBJECT(eth0), cs,
"axistream-control-connected", &error_abort);
- qdev_realize_and_unref(eth0, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(eth0), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(eth0), 0, AXIENET_BASEADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(eth0), 0, irq[AXIENET_IRQ]);
"axistream-connected", &error_abort);
object_property_set_link(OBJECT(dma), cs,
"axistream-control-connected", &error_abort);
- qdev_realize_and_unref(dma, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dma), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, AXIDMA_BASEADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(dma), 0, irq[AXIDMA_IRQ0]);
sysbus_connect_irq(SYS_BUS_DEVICE(dma), 1, irq[AXIDMA_IRQ1]);
dev = qdev_new("xlnx.xps-spi");
qdev_prop_set_uint8(dev, "num-ss-bits", NUM_SPI_FLASHES);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
busdev = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, SPI_BASEADDR);
sysbus_connect_irq(busdev, 0, irq[SPI_IRQ]);
dev = qdev_new("xlnx.xps-intc");
qdev_prop_set_uint32(dev, "kind-of-intr",
1 << ETHLITE_IRQ | 1 << UARTLITE_IRQ);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
qdev_get_gpio_in(DEVICE(cpu), MB_CPU_IRQ));
dev = qdev_new("xlnx.xps-timer");
qdev_prop_set_uint32(dev, "one-timer-only", 0);
qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]);
qdev_set_nic_properties(dev, &nd_table[0]);
qdev_prop_set_uint32(dev, "tx-ping-pong", 0);
qdev_prop_set_uint32(dev, "rx-ping-pong", 0);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, ETHLITE_BASEADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[ETHLITE_IRQ]);
qdev_prop_set_uint64(dev, "mmio_size", mmio_size);
qdev_prop_set_bit(dev, "link_up", link_up);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
cfg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
memory_region_add_subregion_overlap(sys_mem, cfg_base, cfg, 0);
}
dev = qdev_new(TYPE_MIPS_BOSTON);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
s = BOSTON(dev);
s->mach = machine;
&d->pci0_mem,
get_system_io(),
PCI_DEVFN(18, 0), 4, TYPE_PCI_BUS);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
memory_region_init_io(&d->ISD_mem, OBJECT(dev), &isd_mem_ops, d,
"isd-mem", 0x1000);
switch (jazz_model) {
case JAZZ_MAGNUM:
dev = qdev_new("sysbus-g364");
- qdev_realize_and_unref(dev, NULL, &error_fatal);
sysbus = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(sysbus, &error_fatal);
sysbus_mmio_map(sysbus, 0, 0x60080000);
sysbus_mmio_map(sysbus, 1, 0x40000000);
sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 3));
qdev_prop_set_uint8(dev, "it_shift", 2);
object_property_set_link(OBJECT(dev), OBJECT(rc4030_dma_mr),
"dma_mr", &error_abort);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
sysbus = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(sysbus, &error_fatal);
sysbus_mmio_map(sysbus, 0, 0x80001000);
sysbus_mmio_map(sysbus, 1, 0x8000b000);
sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 4));
sysbus_esp->it_shift = 0;
/* XXX for now until rc4030 has been changed to use DMA enable signal */
esp->dma_enabled = 1;
- qdev_realize_and_unref(dev, NULL, &error_fatal);
sysbus = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(sysbus, &error_fatal);
sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 5));
sysbus_mmio_map(sysbus, 0, 0x80002000);
/* NVRAM */
dev = qdev_new("ds1225y");
- qdev_realize_and_unref(dev, NULL, &error_fatal);
sysbus = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(sysbus, &error_fatal);
sysbus_mmio_map(sysbus, 0, 0x80009000);
/* LED indicator */
*/
empty_slot_init("GT64120", 0, 0x20000000);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
/* create CPU */
mips_create_cpu(machine, s, &cbus_irq, &i8259_irq);
dev = qdev_new("mipsnet");
qdev_set_nic_properties(dev, nd);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_connect_irq(s, 0, irq);
memory_region_add_subregion(get_system_io(),
base,
qdev_prop_set_chr(dev, "chardev", serial_hd(0));
qdev_set_legacy_instance_id(dev, 0x3f8, 2);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, env->irq[4]);
sysbus_add_io(SYS_BUS_DEVICE(dev), 0x3f8,
sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0));
dev = qdev_new(TYPE_EMPTY_SLOT);
qdev_prop_set_uint64(dev, "size", slot_size);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map_overlap(SYS_BUS_DEVICE(dev), 0, addr, -10000);
}
*/
ETRAX_FS_ETH(dev)->dma_out = dma_out;
ETRAX_FS_ETH(dev)->dma_in = dma_in;
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
return dev;
dev = qdev_new("eTSEC");
qdev_set_nic_properties(dev, nd);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, tx_irq);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, rx_irq);
qemu_check_nic_model(nd, "lan9118");
dev = qdev_new(TYPE_LAN9118);
qdev_set_nic_properties(dev, nd);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, base);
sysbus_connect_irq(s, 0, irq);
}
s = SYSBUS_I82596(dev);
s->state.irq = lan_irq;
qdev_set_nic_properties(dev, &nd_table[0]);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
s->state.conf.macaddr = HP_MAC; /* set HP MAC prefix */
/* LASI 82596 ports in main memory. */
qemu_check_nic_model(nd, "smc91c111");
dev = qdev_new(TYPE_SMC91C111);
qdev_set_nic_properties(dev, nd);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, base);
sysbus_connect_irq(s, 0, irq);
}
/* Register: Internal Interrupt Controller (IIC) */
dev = qdev_new("altera,iic");
object_property_add_const_link(OBJECT(dev), "cpu", OBJECT(cpu));
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq[0]);
for (i = 0; i < 32; i++) {
irq[i] = qdev_get_gpio_in(dev, i);
/* Register: Timer sys_clk_timer */
dev = qdev_new("ALTR.timer");
qdev_prop_set_uint32(dev, "clock-frequency", 75 * 1000000);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xf8001440);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[0]);
/* Register: Timer sys_clk_timer_1 */
dev = qdev_new("ALTR.timer");
qdev_prop_set_uint32(dev, "clock-frequency", 75 * 1000000);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xe0000880);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[5]);
object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
OBJECT(dev));
- qdev_realize_and_unref(dev, NULL, &error_fatal);
sbd = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(sbd, &error_fatal);
ios = FW_CFG_IO(dev);
sysbus_add_io(sbd, iobase, &ios->comb_iomem);
object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
OBJECT(dev));
- qdev_realize_and_unref(dev, NULL, &error_fatal);
sbd = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(sbd, &error_fatal);
sysbus_mmio_map(sbd, 0, ctl_addr);
sysbus_mmio_map(sbd, 1, data_addr);
dev = qdev_new("open_eth");
qdev_set_nic_properties(dev, nd);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
for (i = 0; i < num_cpus; i++) {
sysbus_connect_irq(s, 0, cpu_irqs[i][irq_pin]);
}
dev = qdev_new("or1k-ompic");
qdev_prop_set_uint32(dev, "num-cpus", num_cpus);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
for (i = 0; i < num_cpus; i++) {
sysbus_connect_irq(s, i, cpu_irqs[i][irq_pin]);
}
goto err_register_bus;
}
- qdev_realize_and_unref(ds, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(ds), &error_fatal);
if (bds) {
qdev_realize_and_unref(bds, &bus->qbus, &error_fatal);
}
phb = PCI_HOST_BRIDGE(dev);
pcihost = BONITO_PCI_HOST_BRIDGE(dev);
pcihost->pic = pic;
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
d = pci_new(PCI_DEVFN(0, 0), TYPE_PCI_BONITO);
s = PCI_BONITO(d);
address_space_io, 0, TYPE_PCI_BUS);
s->bus = b;
object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev));
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
d = pci_create_simple(b, 0, pci_type);
*pi440fx_state = I440FX_PCI_DEVICE(d);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
s = PXA2XX_PCMCIA(dev);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
return s;
}
qdev_prop_set_uint32(dev, "model", pmc->mpic_version);
qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
k = 0;
for (i = 0; i < smp_cpus; i++) {
dev = qdev_new(TYPE_KVM_OPENPIC);
qdev_prop_set_uint32(dev, "model", pmc->mpic_version);
- qdev_realize_and_unref(dev, NULL, &err);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &err);
if (err) {
error_propagate(errp, err);
object_unparent(OBJECT(dev));
dev = qdev_new("e500-ccsr");
object_property_add_child(qdev_get_machine(), "e500-ccsr",
OBJECT(dev));
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
ccsr = CCSR(dev);
ccsr_addr_space = &ccsr->ccsr_space;
memory_region_add_subregion(address_space_mem, pmc->ccsrbar_base,
/* I2C */
dev = qdev_new("mpc-i2c");
s = SYS_BUS_DEVICE(dev);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8544_I2C_IRQ));
memory_region_add_subregion(ccsr_addr_space, MPC8544_I2C_REGS_OFFSET,
sysbus_mmio_get_region(s, 0));
/* General Utility device */
dev = qdev_new("mpc8544-guts");
- qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET,
sysbus_mmio_get_region(s, 0));
object_property_add_child(qdev_get_machine(), "pci-host", OBJECT(dev));
qdev_prop_set_uint32(dev, "first_slot", pmc->pci_first_slot);
qdev_prop_set_uint32(dev, "first_pin_irq", pci_irq_nrs[0]);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
for (i = 0; i < PCI_NUM_PINS; i++) {
sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, pci_irq_nrs[i]));
}
dev = qdev_new("mpc8xxx_gpio");
s = SYS_BUS_DEVICE(dev);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8XXX_GPIO_IRQ));
memory_region_add_subregion(ccsr_addr_space, MPC8XXX_GPIO_OFFSET,
sysbus_mmio_get_region(s, 0));
dev->id = TYPE_PLATFORM_BUS_DEVICE;
qdev_prop_set_uint32(dev, "num_irqs", pmc->platform_bus_num_irqs);
qdev_prop_set_uint32(dev, "mmio_size", pmc->platform_bus_size);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
pms->pbus_dev = PLATFORM_BUS_DEVICE(dev);
s = SYS_BUS_DEVICE(pms->pbus_dev);
/* UniN init */
dev = qdev_new(TYPE_UNI_NORTH);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
memory_region_add_subregion(get_system_memory(), 0xf8000000,
sysbus_mmio_get_region(s, 0));
pic_dev = qdev_new(TYPE_OPENPIC);
qdev_prop_set_uint32(pic_dev, "model", OPENPIC_MODEL_KEYLARGO);
- qdev_realize_and_unref(pic_dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(pic_dev);
+ sysbus_realize_and_unref(s, &error_fatal);
k = 0;
for (i = 0; i < smp_cpus; i++) {
for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
dev = qdev_new(TYPE_U3_AGP_HOST_BRIDGE);
object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic",
&error_abort);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
uninorth_pci = U3_AGP_HOST_BRIDGE(dev);
s = SYS_BUS_DEVICE(dev);
/* PCI hole */
dev = qdev_new(TYPE_UNI_NORTH_AGP_HOST_BRIDGE);
object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic",
&error_abort);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, 0xf0800000);
sysbus_mmio_map(s, 1, 0xf0c00000);
dev = qdev_new(TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE);
object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic",
&error_abort);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, 0xf4800000);
sysbus_mmio_map(s, 1, 0xf4c00000);
qdev_prop_set_uint32(dev, "ofw-addr", 0xf2000000);
object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic",
&error_abort);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
uninorth_pci = UNI_NORTH_PCI_HOST_BRIDGE(dev);
s = SYS_BUS_DEVICE(dev);
/* PCI hole */
dev = qdev_new(TYPE_MACIO_NVRAM);
qdev_prop_set_uint32(dev, "size", 0x2000);
qdev_prop_set_uint32(dev, "it_shift", 1);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, nvram_addr);
nvr = MACIO_NVRAM(dev);
pmac_format_nvram_partition(nvr, 0x2000);
qdev_prop_set_bit(dev, "dma_enabled", false);
object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
OBJECT(fw_cfg));
- qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, CFG_ADDR);
sysbus_mmio_map(s, 1, CFG_ADDR + 2);
/* XXX: we register only 1 output pin for heathrow PIC */
pic_dev = qdev_new(TYPE_HEATHROW);
- qdev_realize_and_unref(pic_dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(pic_dev), &error_fatal);
/* Connect the heathrow PIC outputs to the 6xx bus */
for (i = 0; i < smp_cpus; i++) {
qdev_prop_set_uint32(dev, "ofw-addr", 0x80000000);
object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic",
&error_abort);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, GRACKLE_BASE);
sysbus_mmio_map(s, 1, GRACKLE_BASE + 0x200000);
/* PCI hole */
qdev_prop_set_bit(dev, "dma_enabled", false);
object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
OBJECT(fw_cfg));
- qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, CFG_ADDR);
sysbus_mmio_map(s, 1, CFG_ADDR + 2);
qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor),
&error_abort);
}
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
pnv->pnor = PNV_PNOR(dev);
/* load skiboot firmware */
object_property_set_link(chip, OBJECT(pnv), "xive-fabric",
&error_abort);
}
- qdev_realize_and_unref(DEVICE(chip), NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal);
}
g_free(chip_typename);
object_property_set_int(OBJECT(phb), i, "index", &error_fatal);
object_property_set_int(OBJECT(phb), chip->chip_id, "chip-id",
&error_fatal);
- qdev_realize(DEVICE(phb), NULL, &local_err);
+ sysbus_realize(SYS_BUS_DEVICE(phb), &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
object_property_set_int(obj, PNV_PHB4_DEVICE_ID, "device-id",
&error_fatal);
object_property_set_link(obj, OBJECT(stack), "stack", &error_abort);
- qdev_realize(DEVICE(obj), NULL, &local_err);
+ sysbus_realize(SYS_BUS_DEVICE(obj), &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
dev = qdev_new(TYPE_PPC460EX_PCIE_HOST);
qdev_prop_set_int32(dev, "dcrn-base", DCRN_PCIE0_BASE);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
ppc460ex_pcie_register_dcrs(PPC460EX_PCIE_HOST(dev), env);
dev = qdev_new(TYPE_PPC460EX_PCIE_HOST);
qdev_prop_set_int32(dev, "dcrn-base", DCRN_PCIE1_BASE);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
ppc460ex_pcie_register_dcrs(PPC460EX_PCIE_HOST(dev), env);
}
qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE);
pcihost = SYS_BUS_DEVICE(dev);
object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev));
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(pcihost, &error_fatal);
pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0"));
if (!pci_bus) {
error_report("could not create PCI host controller");
qdev_prop_set_bit(dev, "dma_enabled", false);
object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
OBJECT(fw_cfg));
- qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, CFG_ADDR);
sysbus_mmio_map(s, 1, CFG_ADDR + 2);
dev = qdev_new("sysbus-ohci");
qdev_prop_set_string(dev, "masterbus", "usb-bus.0");
qdev_prop_set_uint32(dev, "num-ports", 6);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
sbdev = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(sbdev, &error_fatal);
sysbus_mmio_map(sbdev, 0, 0x4bffd0000);
sysbus_connect_irq(sbdev, 0, uic[2][30]);
usb_create_simple(usb_bus_find(-1), "usb-kbd");
dev = qdev_new(TYPE_SPAPR_PCI_HOST_BRIDGE);
qdev_prop_set_uint32(dev, "index", 0);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
return PCI_HOST_BRIDGE(dev);
}
qdev_prop_set_uint32(dev, "nr-ends", nr_servers << 3);
object_property_set_link(OBJECT(dev), OBJECT(spapr), "xive-fabric",
&error_abort);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
spapr->xive = SPAPR_XIVE(dev);
/* Create bridge device */
dev = qdev_new(TYPE_SPAPR_VIO_BRIDGE);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
/* Create bus on bridge device */
qbus = qbus_create(TYPE_SPAPR_VIO_BUS, dev, "spapr-vio");
cpu_irq = (qemu_irq *) &env->irq_inputs[PPC40x_INPUT_INT];
dev = qdev_new("xlnx.xps-intc");
qdev_prop_set_uint32(dev, "kind-of-intr", 0);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq[0]);
for (i = 0; i < 32; i++) {
dev = qdev_new("xlnx.xps-timer");
qdev_prop_set_uint32(dev, "one-timer-only", 0);
qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]);
qdev_prop_set_uint32(dev, "timecmp-base", timecmp_base);
qdev_prop_set_uint32(dev, "time-base", time_base);
qdev_prop_set_uint32(dev, "aperture-size", size);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
return dev;
}
DeviceState *sifive_e_prci_create(hwaddr addr)
{
DeviceState *dev = qdev_new(TYPE_SIFIVE_E_PRCI);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
return dev;
}
qdev_prop_set_uint32(dev, "context-base", context_base);
qdev_prop_set_uint32(dev, "context-stride", context_stride);
qdev_prop_set_uint32(dev, "aperture-size", aperture_size);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
return dev;
}
DeviceState *sifive_test_create(hwaddr addr)
{
DeviceState *dev = qdev_new(TYPE_SIFIVE_TEST);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
return dev;
}
assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE));
assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
memory_region_add_subregion(sysmem, base,
sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
dev = qdev_new(TYPE_GPEX_HOST);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
ecam_alias = g_new0(MemoryRegion, 1);
ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
dev = qdev_new(m48txx_sysbus_info[i].bus_name);
qdev_prop_set_int32(dev, "base-year", base_year);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_connect_irq(s, 0, IRQ);
if (io_base != 0) {
memory_region_add_subregion(get_system_io(), io_base,
dev = qdev_new(TYPE_SUN4V_RTC);
s = SYS_BUS_DEVICE(dev);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, addr);
}
dev = qdev_new(TYPE_AP_BRIDGE);
object_property_add_child(qdev_get_machine(), TYPE_AP_BRIDGE,
OBJECT(dev));
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
/* Create bus on bridge device */
bus = qbus_create(TYPE_AP_BUS, dev, TYPE_AP_BUS);
dev = qdev_new(TYPE_VIRTUAL_CSS_BRIDGE);
object_property_add_child(qdev_get_machine(), TYPE_VIRTUAL_CSS_BRIDGE,
OBJECT(dev));
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
/* Create bus on bridge device */
bus = qbus_create(TYPE_VIRTUAL_CSS_BUS, dev, "virtual-css");
dev = qdev_new(TYPE_S390_PCI_HOST_BRIDGE);
object_property_add_child(qdev_get_machine(), TYPE_S390_PCI_HOST_BRIDGE,
OBJECT(dev));
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
/* register hypercalls */
virtio_ccw_register_hcalls();
* as we can't find a fitting bus via the qom tree, we have to add the
* event facility to the sysbus, so e.g. a sclp console can be created.
*/
- qdev_realize(DEVICE(sclp->event_facility), NULL, &err);
+ sysbus_realize(SYS_BUS_DEVICE(sclp->event_facility), &err);
if (err) {
goto out;
}
sysbus_connect_irq(sbd, 0, irq);
qdev_connect_gpio_out_named(dev, "rx-dma", 0, rx_dma);
qdev_connect_gpio_out_named(dev, "tx-dma", 0, tx_dma);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(sbd, &error_fatal);
/* Create and plug in the sd card */
carddev = qdev_new(TYPE_SD_CARD);
dev = qdev_new("sh_pci");
busdev = SYS_BUS_DEVICE(dev);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(busdev, &error_fatal);
pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci"));
sysbus_mmio_map(busdev, 0, P4ADDR(0x1e200000));
sysbus_mmio_map(busdev, 1, A7ADDR(0x1e200000));
qdev_prop_set_uint32(dev, "vram-size", SM501_VRAM_SIZE);
qdev_prop_set_uint32(dev, "base", 0x10000000);
qdev_prop_set_chr(dev, "chardev", serial_hd(2));
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, 0x10000000);
sysbus_mmio_map(busdev, 1, 0x13e00000);
sysbus_connect_irq(busdev, 0, irq[SM501]);
busdev = SYS_BUS_DEVICE(dev);
sysbus_connect_irq(busdev, 0, irq[CF_IDE]);
qdev_prop_set_uint32(dev, "shift", 1);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, 0x14001000);
sysbus_mmio_map(busdev, 1, 0x1400080c);
mmio_ide_init_drives(dev, dinfo, NULL);
qemu_register_reset(main_cpu_reset, reset_info);
ahb_pnp = GRLIB_AHB_PNP(qdev_new(TYPE_GRLIB_AHB_PNP));
- qdev_realize_and_unref(DEVICE(ahb_pnp), NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(ahb_pnp), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(ahb_pnp), 0, LEON3_AHB_PNP_OFFSET);
grlib_ahb_pnp_add_entry(ahb_pnp, 0, 0, GRLIB_VENDOR_GAISLER,
GRLIB_LEON3_DEV, GRLIB_AHB_MASTER,
GRLIB_CPU_AREA);
apb_pnp = GRLIB_APB_PNP(qdev_new(TYPE_GRLIB_APB_PNP));
- qdev_realize_and_unref(DEVICE(apb_pnp), NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(apb_pnp), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(apb_pnp), 0, LEON3_APB_PNP_OFFSET);
grlib_ahb_pnp_add_entry(ahb_pnp, LEON3_APB_PNP_OFFSET, 0xFFF,
GRLIB_VENDOR_GAISLER, GRLIB_APBMST_DEV,
env, "pil", 1);
qdev_connect_gpio_out_named(dev, "grlib-irq", 0,
qdev_get_gpio_in_named(DEVICE(cpu), "pil", 0));
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, LEON3_IRQMP_OFFSET);
env->irq_manager = dev;
env->qemu_irq_ack = leon3_irq_manager;
qdev_prop_set_uint32(dev, "nr-timers", LEON3_TIMER_COUNT);
qdev_prop_set_uint32(dev, "frequency", CPU_CLK);
qdev_prop_set_uint32(dev, "irq-line", LEON3_TIMER_IRQ);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, LEON3_TIMER_OFFSET);
for (i = 0; i < LEON3_TIMER_COUNT; i++) {
/* Allocate uart */
dev = qdev_new(TYPE_GRLIB_APB_UART);
qdev_prop_set_chr(dev, "chrdev", serial_hd(0));
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, LEON3_UART_OFFSET);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irqs[LEON3_UART_IRQ]);
grlib_apb_pnp_add_entry(apb_pnp, LEON3_UART_OFFSET, 0xFFF,
dev = qdev_new(TYPE_SUN4M_IOMMU);
qdev_prop_set_uint32(dev, "version", version);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_connect_irq(s, 0, irq);
sysbus_mmio_map(s, 0, addr);
SysBusPCNetState *lance;
dma = qdev_new(TYPE_SPARC32_DMA);
- qdev_realize_and_unref(dma, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dma), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base);
espdma = SPARC32_ESPDMA_DEVICE(object_resolve_path_component(
unsigned int i, j;
dev = qdev_new("slavio_intctl");
- qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
for (i = 0; i < MAX_CPUS; i++) {
for (j = 0; j < MAX_PILS; j++) {
dev = qdev_new("slavio_timer");
qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_connect_irq(s, 0, master_irq);
sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
SysBusDevice *s;
dev = qdev_new("slavio_misc");
- qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
if (base) {
/* 8 bit registers */
/* Slavio control */
dev = qdev_new("eccmemctl");
qdev_prop_set_uint32(dev, "version", version);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_connect_irq(s, 0, irq);
sysbus_mmio_map(s, 0, base);
if (version == 0) { // SS-600MP only
SysBusDevice *s;
dev = qdev_new("apc");
- qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
/* Power management (APC) XXX: not a Slavio device */
sysbus_mmio_map(s, 0, power_base);
sysbus_connect_irq(s, 0, cpu_halt);
qdev_prop_set_uint16(dev, "width", width);
qdev_prop_set_uint16(dev, "height", height);
qdev_prop_set_uint16(dev, "depth", depth);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
/* 10/ROM : FCode ROM */
sysbus_mmio_map(s, 0, addr);
qdev_prop_set_uint16(dev, "width", width);
qdev_prop_set_uint16(dev, "height", height);
qdev_prop_set_uint16(dev, "depth", depth);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
/* FCode ROM */
sysbus_mmio_map(s, 0, addr);
SysBusDevice *s;
dev = qdev_new(TYPE_MACIO_ID_REGISTER);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, addr);
address_space_write_rom(&address_space_memory, addr,
SysBusDevice *s;
dev = qdev_new(TYPE_TCX_AFX);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, addr);
}
int ret;
dev = qdev_new(TYPE_OPENPROM);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, addr);
/* Create and map RAM frontend */
dev = qdev_new("memory");
object_property_set_link(OBJECT(dev), ram_memdev, "memdev", &error_fatal);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0);
/* models without ECC don't trap when missing ram is accessed */
qdev_prop_set_chr(dev, "chrA", NULL);
qdev_prop_set_uint32(dev, "chnBtype", escc_mouse);
qdev_prop_set_uint32(dev, "chnAtype", escc_kbd);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_connect_irq(s, 0, slavio_irq[14]);
sysbus_connect_irq(s, 1, slavio_irq[14]);
sysbus_mmio_map(s, 0, hwdef->ms_kb_base);
qdev_prop_set_chr(dev, "chrA", serial_hd(0));
qdev_prop_set_uint32(dev, "chnBtype", escc_serial);
qdev_prop_set_uint32(dev, "chnAtype", escc_serial);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_connect_irq(s, 0, slavio_irq[15]);
sysbus_connect_irq(s, 1, slavio_irq[15]);
sysbus_mmio_map(s, 0, hwdef->serial_base);
qdev_prop_set_bit(dev, "dma_enabled", false);
object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
OBJECT(fw_cfg));
- qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, CFG_ADDR);
sysbus_mmio_map(s, 1, CFG_ADDR + 2);
/* Power */
dev = qdev_new(TYPE_SUN4U_POWER);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
sbd = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(sbd, &error_fatal);
memory_region_add_subregion(pci_address_space_io(pci_dev), 0x7240,
sysbus_mmio_get_region(sbd, 0));
int ret;
dev = qdev_new(TYPE_OPENPROM);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, addr);
d = SUN4U_RAM(dev);
d->size = RAM_size;
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, addr);
}
/* IOMMU */
iommu = qdev_new(TYPE_SUN4U_IOMMU);
- qdev_realize_and_unref(iommu, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(iommu), &error_fatal);
/* set up devices */
ram_init(0, machine->ram_size);
qdev_prop_set_uint64(DEVICE(sabre), "mem-base", PBM_MEM_BASE);
object_property_set_link(OBJECT(sabre), OBJECT(iommu), "iommu",
&error_abort);
- qdev_realize_and_unref(DEVICE(sabre), NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(sabre), &error_fatal);
/* Wire up PCI interrupts to CPU */
for (i = 0; i < IVEC_MAX; i++) {
dev = qdev_new(TYPE_FW_CFG_IO);
qdev_prop_set_bit(dev, "dma_enabled", false);
object_property_add_child(OBJECT(ebus), TYPE_FW_CFG, OBJECT(dev));
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
memory_region_add_subregion(pci_address_space_io(ebus), BIOS_CFG_IOPORT,
&FW_CFG_IO(dev)->comb_iomem);
DeviceState *dev = qdev_new(TYPE_XEN_BRIDGE);
BusState *bus = qbus_create(TYPE_XEN_BUS, dev, NULL);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
qbus_set_bus_hotplug_handler(bus, &error_abort);
}
}
xen_sysdev = qdev_new(TYPE_XENSYSDEV);
- qdev_realize_and_unref(xen_sysdev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(xen_sysdev), &error_fatal);
xen_sysbus = qbus_create(TYPE_XENSYSBUS, xen_sysdev, "xen-sysbus");
qbus_set_bus_hotplug_handler(xen_sysbus, &error_abort);
int i;
dev = qdev_new(TYPE_GPEX_HOST);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
/* Map only the first size_ecam bytes of ECAM space. */
ecam_alias = g_new0(MemoryRegion, 1);
dev = qdev_new("open_eth");
qdev_set_nic_properties(dev, nd);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_connect_irq(s, 0, irq);
memory_region_add_subregion(address_space, base,
sysbus_mmio_get_region(s, 0));
qdev_prop_set_uint8(dev, "width", 2);
qdev_prop_set_bit(dev, "big-endian", be);
qdev_prop_set_string(dev, "name", "xtfpga.io.flash");
- qdev_realize_and_unref(dev, NULL, &error_fatal);
s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
memory_region_add_subregion(address_space, board->flash->base,
sysbus_mmio_get_region(s, 0));
return PFLASH_CFI01(dev);
dev = qdev_new(TYPE_CADENCE_UART);
s = SYS_BUS_DEVICE(dev);
qdev_prop_set_chr(dev, "chardev", chr);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, addr);
sysbus_connect_irq(s, 0, irq);
s = SYS_BUS_DEVICE(dev);
qdev_prop_set_chr(dev, "chardev", chr);
qdev_prop_set_uint32(dev, "pclk-frq", pclk_frq);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, addr);
sysbus_connect_irq(s, 0, txint);
sysbus_connect_irq(s, 1, rxint);
dev = qdev_new("pl011");
s = SYS_BUS_DEVICE(dev);
qdev_prop_set_chr(dev, "chardev", chr);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, addr);
sysbus_connect_irq(s, 0, irq);
dev = qdev_new("pl011_luminary");
s = SYS_BUS_DEVICE(dev);
qdev_prop_set_chr(dev, "chardev", chr);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, addr);
sysbus_connect_irq(s, 0, irq);
dev = qdev_new("xlnx.xps-uartlite");
s = SYS_BUS_DEVICE(dev);
qdev_prop_set_chr(dev, "chardev", chr);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, addr);
sysbus_connect_irq(s, 0, irq);
dev = qdev_new("etraxfs,serial");
s = SYS_BUS_DEVICE(dev);
qdev_prop_set_chr(dev, "chardev", chr);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, addr);
sysbus_connect_irq(s, 0, irq);
return dev;
qdev_prop_set_string(dev, "name", name);
qdev_prop_set_uint64(dev, "size", size);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map_overlap(SYS_BUS_DEVICE(dev), 0, base, -1000);
}
dev = qdev_new(TYPE_CMSDK_APB_TIMER);
s = SYS_BUS_DEVICE(dev);
qdev_prop_set_uint32(dev, "pclk-frq", pclk_frq);
- qdev_realize_and_unref(dev, NULL, &error_fatal);
+ sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, addr);
sysbus_connect_irq(s, 0, timerint);
return dev;
projects / qemu.git / commitdiff