arm64: dts: rockchip: add naneng combo phy nodes for rk3568

Add the core dt-node for the rk3568's naneng combo phys.

Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Tested-by: Frank Wunderlich <frank-w@public-files.de>
Link: https://lore.kernel.org/r/20220208091326.12495-5-yifeng.zhao@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
index 2fd313a295f8aaa1d5c7a8b1250fc428513baa88..91a0b798b85709902d06ca7f1c4cc00642526a38 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
@@ -8,6 +8,11 @@
 / {
        compatible = "rockchip,rk3568";
 
+       pipe_phy_grf0: syscon@fdc70000 {
+               compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
+               reg = <0x0 0xfdc70000 0x0 0x1000>;
+       };
+
        qos_pcie3x1: qos@fe190080 {
                compatible = "rockchip,rk3568-qos", "syscon";
                reg = <0x0 0xfe190080 0x0 0x20>;
@@ -71,6 +76,22 @@
                        queue0 {};
                };
        };
+
+       combphy0: phy@fe820000 {
+               compatible = "rockchip,rk3568-naneng-combphy";
+               reg = <0x0 0xfe820000 0x0 0x100>;
+               clocks = <&pmucru CLK_PCIEPHY0_REF>,
+                        <&cru PCLK_PIPEPHY0>,
+                        <&cru PCLK_PIPE>;
+               clock-names = "ref", "apb", "pipe";
+               assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
+               assigned-clock-rates = <100000000>;
+               resets = <&cru SRST_PIPEPHY0>;
+               rockchip,pipe-grf = <&pipegrf>;
+               rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
+               #phy-cells = <1>;
+               status = "disabled";
+       };
 };
 
 &cpu0_opp_table {

diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index e20ee3968b5a6ba5d63d7effc8e72b64887921c2..5c6cae76c18000068c40278f1a30307b6c4dd7bf 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -296,11 +296,26 @@
                };
        };
 
+       pipegrf: syscon@fdc50000 {
+               compatible = "rockchip,rk3568-pipe-grf", "syscon";
+               reg = <0x0 0xfdc50000 0x0 0x1000>;
+       };
+
        grf: syscon@fdc60000 {
                compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
                reg = <0x0 0xfdc60000 0x0 0x10000>;
        };
 
+       pipe_phy_grf1: syscon@fdc80000 {
+               compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
+               reg = <0x0 0xfdc80000 0x0 0x1000>;
+       };
+
+       pipe_phy_grf2: syscon@fdc90000 {
+               compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
+               reg = <0x0 0xfdc90000 0x0 0x1000>;
+       };
+
        usb2phy0_grf: syscon@fdca0000 {
                compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
                reg = <0x0 0xfdca0000 0x0 0x8000>;
@@ -1307,6 +1322,38 @@
                status = "disabled";
        };
 
+       combphy1: phy@fe830000 {
+               compatible = "rockchip,rk3568-naneng-combphy";
+               reg = <0x0 0xfe830000 0x0 0x100>;
+               clocks = <&pmucru CLK_PCIEPHY1_REF>,
+                        <&cru PCLK_PIPEPHY1>,
+                        <&cru PCLK_PIPE>;
+               clock-names = "ref", "apb", "pipe";
+               assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
+               assigned-clock-rates = <100000000>;
+               resets = <&cru SRST_PIPEPHY1>;
+               rockchip,pipe-grf = <&pipegrf>;
+               rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
+               #phy-cells = <1>;
+               status = "disabled";
+       };
+
+       combphy2: phy@fe840000 {
+               compatible = "rockchip,rk3568-naneng-combphy";
+               reg = <0x0 0xfe840000 0x0 0x100>;
+               clocks = <&pmucru CLK_PCIEPHY2_REF>,
+                        <&cru PCLK_PIPEPHY2>,
+                        <&cru PCLK_PIPE>;
+               clock-names = "ref", "apb", "pipe";
+               assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
+               assigned-clock-rates = <100000000>;
+               resets = <&cru SRST_PIPEPHY2>;
+               rockchip,pipe-grf = <&pipegrf>;
+               rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
+               #phy-cells = <1>;
+               status = "disabled";
+       };
+
        usb2phy0: usb2phy@fe8a0000 {
                compatible = "rockchip,rk3568-usb2phy";
                reg = <0x0 0xfe8a0000 0x0 0x10000>;