drm/amd/display: Refactor OPTC into component folder
authorParandhaman K <parandhaman.k@amd.com>
Thu, 9 Nov 2023 10:22:17 +0000 (15:52 +0530)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 29 Nov 2023 21:49:01 +0000 (16:49 -0500)
[why]
Move all optc files to unique
folder optc.

[how]
creating optc repo in dc, and moved the dcnxx_optc.c and .h files into
corresponding new folders inside the optc and cleared the linkage
errors by adding relative paths in the Makefile.template.

Reviewed-by: Martin Leung <martin.leung@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Parandhaman K <parandhaman.k@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
49 files changed:
drivers/gpu/drm/amd/display/Makefile
drivers/gpu/drm/amd/display/dc/Makefile
drivers/gpu/drm/amd/display/dc/dcn10/Makefile
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c [deleted file]
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h [deleted file]
drivers/gpu/drm/amd/display/dc/dcn20/Makefile
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c [deleted file]
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h [deleted file]
drivers/gpu/drm/amd/display/dc/dcn201/Makefile
drivers/gpu/drm/amd/display/dc/dcn201/dcn201_optc.c [deleted file]
drivers/gpu/drm/amd/display/dc/dcn201/dcn201_optc.h [deleted file]
drivers/gpu/drm/amd/display/dc/dcn30/Makefile
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c [deleted file]
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h [deleted file]
drivers/gpu/drm/amd/display/dc/dcn301/Makefile
drivers/gpu/drm/amd/display/dc/dcn301/dcn301_optc.c [deleted file]
drivers/gpu/drm/amd/display/dc/dcn301/dcn301_optc.h [deleted file]
drivers/gpu/drm/amd/display/dc/dcn31/Makefile
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c [deleted file]
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h [deleted file]
drivers/gpu/drm/amd/display/dc/dcn314/Makefile
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.c [deleted file]
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.h [deleted file]
drivers/gpu/drm/amd/display/dc/dcn32/Makefile
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c [deleted file]
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h [deleted file]
drivers/gpu/drm/amd/display/dc/dcn35/Makefile
drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c [deleted file]
drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.h [deleted file]
drivers/gpu/drm/amd/display/dc/optc/Makefile [new file with mode: 0644]
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c [new file with mode: 0644]
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h [new file with mode: 0644]
drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c [new file with mode: 0644]
drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h [new file with mode: 0644]
drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c [new file with mode: 0644]
drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.h [new file with mode: 0644]
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c [new file with mode: 0644]
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h [new file with mode: 0644]
drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c [new file with mode: 0644]
drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.h [new file with mode: 0644]
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c [new file with mode: 0644]
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h [new file with mode: 0644]
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c [new file with mode: 0644]
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h [new file with mode: 0644]
drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c [new file with mode: 0644]
drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h [new file with mode: 0644]
drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c [new file with mode: 0644]
drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h [new file with mode: 0644]

index 7b0959da2cacc2f64ba5459e5b30a23f3c52446b..92a5c5efcf9262f5934d2f6abdcea9983cda9cd0 100644 (file)
@@ -32,6 +32,7 @@ subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/clk_mgr
 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/hwss
 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/resource
 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dsc
+subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/optc
 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/inc
 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/freesync
 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/color
index ab51a065cf0e589cf2f3546750916c0048daeb8c..390e7a99be5410e53dfc3b321baaa9f0ec65140d 100644 (file)
@@ -22,7 +22,7 @@
 #
 # Makefile for Display Core (dc) component.
 
-DC_LIBS = basics bios dml clk_mgr dce gpio hwss irq link virtual dsc resource
+DC_LIBS = basics bios dml clk_mgr dce gpio hwss irq link virtual dsc resource optc
 
 ifdef CONFIG_DRM_AMD_DC_FP
 
index 1eb7418ced3aa4376fe5454fcd299334996a31e1..0dd62934a18ce9497dcaadcfc2a3b3364fd52670 100644 (file)
@@ -24,7 +24,7 @@
 
 DCN10 = dcn10_init.o dcn10_ipp.o \
                dcn10_hw_sequencer_debug.o \
-               dcn10_dpp.o dcn10_opp.o dcn10_optc.o \
+               dcn10_dpp.o dcn10_opp.o \
                dcn10_hubp.o dcn10_mpc.o \
                dcn10_dpp_dscl.o dcn10_dpp_cm.o dcn10_cm_common.o \
                dcn10_hubbub.o dcn10_stream_encoder.o dcn10_link_encoder.o
index 92fdab731f4ac9fdc0a05c7f8e4bd8c7f4e334d4..9033b39e0e0c8389594b20ffb710a7ee4822935d 100644 (file)
@@ -32,7 +32,7 @@
 #include "dce/dce_hwseq.h"
 #include "abm.h"
 #include "dmcu.h"
-#include "dcn10_optc.h"
+#include "dcn10/dcn10_optc.h"
 #include "dcn10/dcn10_dpp.h"
 #include "dcn10/dcn10_mpc.h"
 #include "timing_generator.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
deleted file mode 100644 (file)
index 0e8f4f3..0000000
+++ /dev/null
@@ -1,1621 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-
-#include "reg_helper.h"
-#include "dcn10_optc.h"
-#include "dc.h"
-#include "dc_trace.h"
-
-#define REG(reg)\
-       optc1->tg_regs->reg
-
-#define CTX \
-       optc1->base.ctx
-
-#undef FN
-#define FN(reg_name, field_name) \
-       optc1->tg_shift->field_name, optc1->tg_mask->field_name
-
-#define STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN 0x100
-
-/**
- * apply_front_porch_workaround() - This is a workaround for a bug that has
- *                                  existed since R5xx and has not been fixed
- *                                  keep Front porch at minimum 2 for Interlaced
- *                                  mode or 1 for progressive.
- *
- * @timing: Timing parameters used to configure DCN blocks.
- */
-static void apply_front_porch_workaround(struct dc_crtc_timing *timing)
-{
-       if (timing->flags.INTERLACE == 1) {
-               if (timing->v_front_porch < 2)
-                       timing->v_front_porch = 2;
-       } else {
-               if (timing->v_front_porch < 1)
-                       timing->v_front_porch = 1;
-       }
-}
-
-void optc1_program_global_sync(
-               struct timing_generator *optc,
-               int vready_offset,
-               int vstartup_start,
-               int vupdate_offset,
-               int vupdate_width)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       optc1->vready_offset = vready_offset;
-       optc1->vstartup_start = vstartup_start;
-       optc1->vupdate_offset = vupdate_offset;
-       optc1->vupdate_width = vupdate_width;
-
-       if (optc1->vstartup_start == 0) {
-               BREAK_TO_DEBUGGER();
-               return;
-       }
-
-       REG_SET(OTG_VSTARTUP_PARAM, 0,
-               VSTARTUP_START, optc1->vstartup_start);
-
-       REG_SET_2(OTG_VUPDATE_PARAM, 0,
-                       VUPDATE_OFFSET, optc1->vupdate_offset,
-                       VUPDATE_WIDTH, optc1->vupdate_width);
-
-       REG_SET(OTG_VREADY_PARAM, 0,
-                       VREADY_OFFSET, optc1->vready_offset);
-}
-
-static void optc1_disable_stereo(struct timing_generator *optc)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       REG_SET(OTG_STEREO_CONTROL, 0,
-               OTG_STEREO_EN, 0);
-
-       REG_SET_2(OTG_3D_STRUCTURE_CONTROL, 0,
-               OTG_3D_STRUCTURE_EN, 0,
-               OTG_3D_STRUCTURE_STEREO_SEL_OVR, 0);
-}
-
-void optc1_setup_vertical_interrupt0(
-               struct timing_generator *optc,
-               uint32_t start_line,
-               uint32_t end_line)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       REG_SET_2(OTG_VERTICAL_INTERRUPT0_POSITION, 0,
-                       OTG_VERTICAL_INTERRUPT0_LINE_START, start_line,
-                       OTG_VERTICAL_INTERRUPT0_LINE_END, end_line);
-}
-
-void optc1_setup_vertical_interrupt1(
-               struct timing_generator *optc,
-               uint32_t start_line)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       REG_SET(OTG_VERTICAL_INTERRUPT1_POSITION, 0,
-                               OTG_VERTICAL_INTERRUPT1_LINE_START, start_line);
-}
-
-void optc1_setup_vertical_interrupt2(
-               struct timing_generator *optc,
-               uint32_t start_line)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       REG_SET(OTG_VERTICAL_INTERRUPT2_POSITION, 0,
-                       OTG_VERTICAL_INTERRUPT2_LINE_START, start_line);
-}
-
-/**
- * optc1_program_timing() - used by mode timing set Program
- *                          CRTC Timing Registers - OTG_H_*,
- *                          OTG_V_*, Pixel repetition.
- *                          Including SYNC. Call BIOS command table to program Timings.
- *
- * @optc: timing_generator instance.
- * @dc_crtc_timing: Timing parameters used to configure DCN blocks.
- * @vready_offset: Vready's starting position.
- * @vstartup_start: Vstartup period.
- * @vupdate_offset: Vupdate starting position.
- * @vupdate_width: Vupdate duration.
- * @signal: DC signal types.
- * @use_vbios: to program timings from BIOS command table.
- *
- */
-void optc1_program_timing(
-       struct timing_generator *optc,
-       const struct dc_crtc_timing *dc_crtc_timing,
-       int vready_offset,
-       int vstartup_start,
-       int vupdate_offset,
-       int vupdate_width,
-       const enum signal_type signal,
-       bool use_vbios)
-{
-       struct dc_crtc_timing patched_crtc_timing;
-       uint32_t asic_blank_end;
-       uint32_t asic_blank_start;
-       uint32_t v_total;
-       uint32_t v_sync_end;
-       uint32_t h_sync_polarity, v_sync_polarity;
-       uint32_t start_point = 0;
-       uint32_t field_num = 0;
-       enum h_timing_div_mode h_div = H_TIMING_NO_DIV;
-
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       optc1->signal = signal;
-       optc1->vready_offset = vready_offset;
-       optc1->vstartup_start = vstartup_start;
-       optc1->vupdate_offset = vupdate_offset;
-       optc1->vupdate_width = vupdate_width;
-       patched_crtc_timing = *dc_crtc_timing;
-       apply_front_porch_workaround(&patched_crtc_timing);
-       optc1->orginal_patched_timing = patched_crtc_timing;
-
-       /* Load horizontal timing */
-
-       /* CRTC_H_TOTAL = vesa.h_total - 1 */
-       REG_SET(OTG_H_TOTAL, 0,
-                       OTG_H_TOTAL,  patched_crtc_timing.h_total - 1);
-
-       /* h_sync_start = 0, h_sync_end = vesa.h_sync_width */
-       REG_UPDATE_2(OTG_H_SYNC_A,
-                       OTG_H_SYNC_A_START, 0,
-                       OTG_H_SYNC_A_END, patched_crtc_timing.h_sync_width);
-
-       /* blank_start = line end - front porch */
-       asic_blank_start = patched_crtc_timing.h_total -
-                       patched_crtc_timing.h_front_porch;
-
-       /* blank_end = blank_start - active */
-       asic_blank_end = asic_blank_start -
-                       patched_crtc_timing.h_border_right -
-                       patched_crtc_timing.h_addressable -
-                       patched_crtc_timing.h_border_left;
-
-       REG_UPDATE_2(OTG_H_BLANK_START_END,
-                       OTG_H_BLANK_START, asic_blank_start,
-                       OTG_H_BLANK_END, asic_blank_end);
-
-       /* h_sync polarity */
-       h_sync_polarity = patched_crtc_timing.flags.HSYNC_POSITIVE_POLARITY ?
-                       0 : 1;
-
-       REG_UPDATE(OTG_H_SYNC_A_CNTL,
-                       OTG_H_SYNC_A_POL, h_sync_polarity);
-
-       v_total = patched_crtc_timing.v_total - 1;
-
-       REG_SET(OTG_V_TOTAL, 0,
-                       OTG_V_TOTAL, v_total);
-
-       /* In case of V_TOTAL_CONTROL is on, make sure OTG_V_TOTAL_MAX and
-        * OTG_V_TOTAL_MIN are equal to V_TOTAL.
-        */
-       optc->funcs->set_vtotal_min_max(optc, v_total, v_total);
-
-       /* v_sync_start = 0, v_sync_end = v_sync_width */
-       v_sync_end = patched_crtc_timing.v_sync_width;
-
-       REG_UPDATE_2(OTG_V_SYNC_A,
-                       OTG_V_SYNC_A_START, 0,
-                       OTG_V_SYNC_A_END, v_sync_end);
-
-       /* blank_start = frame end - front porch */
-       asic_blank_start = patched_crtc_timing.v_total -
-                       patched_crtc_timing.v_front_porch;
-
-       /* blank_end = blank_start - active */
-       asic_blank_end = asic_blank_start -
-                       patched_crtc_timing.v_border_bottom -
-                       patched_crtc_timing.v_addressable -
-                       patched_crtc_timing.v_border_top;
-
-       REG_UPDATE_2(OTG_V_BLANK_START_END,
-                       OTG_V_BLANK_START, asic_blank_start,
-                       OTG_V_BLANK_END, asic_blank_end);
-
-       /* v_sync polarity */
-       v_sync_polarity = patched_crtc_timing.flags.VSYNC_POSITIVE_POLARITY ?
-                       0 : 1;
-
-       REG_UPDATE(OTG_V_SYNC_A_CNTL,
-               OTG_V_SYNC_A_POL, v_sync_polarity);
-
-       if (optc1->signal == SIGNAL_TYPE_DISPLAY_PORT ||
-                       optc1->signal == SIGNAL_TYPE_DISPLAY_PORT_MST ||
-                       optc1->signal == SIGNAL_TYPE_EDP) {
-               start_point = 1;
-               if (patched_crtc_timing.flags.INTERLACE == 1)
-                       field_num = 1;
-       }
-
-       /* Interlace */
-       if (REG(OTG_INTERLACE_CONTROL)) {
-               if (patched_crtc_timing.flags.INTERLACE == 1)
-                       REG_UPDATE(OTG_INTERLACE_CONTROL,
-                                       OTG_INTERLACE_ENABLE, 1);
-               else
-                       REG_UPDATE(OTG_INTERLACE_CONTROL,
-                                       OTG_INTERLACE_ENABLE, 0);
-       }
-
-       /* VTG enable set to 0 first VInit */
-       REG_UPDATE(CONTROL,
-                       VTG0_ENABLE, 0);
-
-       /* original code is using VTG offset to address OTG reg, seems wrong */
-       REG_UPDATE_2(OTG_CONTROL,
-                       OTG_START_POINT_CNTL, start_point,
-                       OTG_FIELD_NUMBER_CNTL, field_num);
-
-       optc->funcs->program_global_sync(optc,
-                       vready_offset,
-                       vstartup_start,
-                       vupdate_offset,
-                       vupdate_width);
-
-       optc->funcs->set_vtg_params(optc, dc_crtc_timing, true);
-
-       /* TODO
-        * patched_crtc_timing.flags.HORZ_COUNT_BY_TWO == 1
-        * program_horz_count_by_2
-        * for DVI 30bpp mode, 0 otherwise
-        * program_horz_count_by_2(optc, &patched_crtc_timing);
-        */
-
-       /* Enable stereo - only when we need to pack 3D frame. Other types
-        * of stereo handled in explicit call
-        */
-
-       if (optc1_is_two_pixels_per_containter(&patched_crtc_timing) || optc1->opp_count == 2)
-               h_div = H_TIMING_DIV_BY2;
-
-       if (REG(OPTC_DATA_FORMAT_CONTROL) && optc1->tg_mask->OPTC_DATA_FORMAT != 0) {
-               uint32_t data_fmt = 0;
-
-               if (patched_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
-                       data_fmt = 1;
-               else if (patched_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
-                       data_fmt = 2;
-
-               REG_UPDATE(OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, data_fmt);
-       }
-
-       if (optc1->tg_mask->OTG_H_TIMING_DIV_MODE != 0) {
-               if (optc1->opp_count == 4)
-                       h_div = H_TIMING_DIV_BY4;
-
-               REG_UPDATE(OTG_H_TIMING_CNTL,
-               OTG_H_TIMING_DIV_MODE, h_div);
-       } else {
-               REG_UPDATE(OTG_H_TIMING_CNTL,
-               OTG_H_TIMING_DIV_BY2, h_div);
-       }
-}
-
-/**
- * optc1_set_vtg_params - Set Vertical Timing Generator (VTG) parameters
- *
- * @optc: timing_generator struct used to extract the optc parameters
- * @dc_crtc_timing: Timing parameters configured
- * @program_fp2: Boolean value indicating if FP2 will be programmed or not
- *
- * OTG is responsible for generating the global sync signals, including
- * vertical timing information for each HUBP in the dcfclk domain. Each VTG is
- * associated with one OTG that provides HUBP with vertical timing information
- * (i.e., there is 1:1 correspondence between OTG and VTG). This function is
- * responsible for setting the OTG parameters to the VTG during the pipe
- * programming.
- */
-void optc1_set_vtg_params(struct timing_generator *optc,
-               const struct dc_crtc_timing *dc_crtc_timing, bool program_fp2)
-{
-       struct dc_crtc_timing patched_crtc_timing;
-       uint32_t asic_blank_end;
-       uint32_t v_init;
-       uint32_t v_fp2 = 0;
-       int32_t vertical_line_start;
-
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       patched_crtc_timing = *dc_crtc_timing;
-       apply_front_porch_workaround(&patched_crtc_timing);
-
-       /* VCOUNT_INIT is the start of blank */
-       v_init = patched_crtc_timing.v_total - patched_crtc_timing.v_front_porch;
-
-       /* end of blank = v_init - active */
-       asic_blank_end = v_init -
-                       patched_crtc_timing.v_border_bottom -
-                       patched_crtc_timing.v_addressable -
-                       patched_crtc_timing.v_border_top;
-
-       /* if VSTARTUP is before VSYNC, FP2 is the offset, otherwise 0 */
-       vertical_line_start = asic_blank_end - optc1->vstartup_start + 1;
-       if (vertical_line_start < 0)
-               v_fp2 = -vertical_line_start;
-
-       /* Interlace */
-       if (REG(OTG_INTERLACE_CONTROL)) {
-               if (patched_crtc_timing.flags.INTERLACE == 1) {
-                       v_init = v_init / 2;
-                       if ((optc1->vstartup_start/2)*2 > asic_blank_end)
-                               v_fp2 = v_fp2 / 2;
-               }
-       }
-
-       if (program_fp2)
-               REG_UPDATE_2(CONTROL,
-                               VTG0_FP2, v_fp2,
-                               VTG0_VCOUNT_INIT, v_init);
-       else
-               REG_UPDATE(CONTROL, VTG0_VCOUNT_INIT, v_init);
-}
-
-void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       uint32_t blank_data_double_buffer_enable = enable ? 1 : 0;
-
-       REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,
-                       OTG_BLANK_DATA_DOUBLE_BUFFER_EN, blank_data_double_buffer_enable);
-}
-
-/**
- * optc1_set_timing_double_buffer() - DRR double buffering control
- *
- * Sets double buffer point for V_TOTAL, H_TOTAL, VTOTAL_MIN,
- * VTOTAL_MAX, VTOTAL_MIN_SEL and VTOTAL_MAX_SEL registers.
- *
- * @optc: timing_generator instance.
- * @enable: Enable DRR double buffering control if true, disable otherwise.
- *
- * Options: any time,  start of frame, dp start of frame (range timing)
- */
-void optc1_set_timing_double_buffer(struct timing_generator *optc, bool enable)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-       uint32_t mode = enable ? 2 : 0;
-
-       REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,
-                  OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mode);
-}
-
-/**
- * optc1_unblank_crtc() - Call ASIC Control Object to UnBlank CRTC.
- *
- * @optc: timing_generator instance.
- */
-static void optc1_unblank_crtc(struct timing_generator *optc)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       REG_UPDATE_2(OTG_BLANK_CONTROL,
-                       OTG_BLANK_DATA_EN, 0,
-                       OTG_BLANK_DE_MODE, 0);
-
-       /* W/A for automated testing
-        * Automated testing will fail underflow test as there
-        * sporadic underflows which occur during the optc blank
-        * sequence.  As a w/a, clear underflow on unblank.
-        * This prevents the failure, but will not mask actual
-        * underflow that affect real use cases.
-        */
-       optc1_clear_optc_underflow(optc);
-}
-
-/**
- * optc1_blank_crtc() - Call ASIC Control Object to Blank CRTC.
- *
- * @optc: timing_generator instance.
- */
-
-static void optc1_blank_crtc(struct timing_generator *optc)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       REG_UPDATE_2(OTG_BLANK_CONTROL,
-                       OTG_BLANK_DATA_EN, 1,
-                       OTG_BLANK_DE_MODE, 0);
-
-       optc1_set_blank_data_double_buffer(optc, false);
-}
-
-void optc1_set_blank(struct timing_generator *optc,
-               bool enable_blanking)
-{
-       if (enable_blanking)
-               optc1_blank_crtc(optc);
-       else
-               optc1_unblank_crtc(optc);
-}
-
-bool optc1_is_blanked(struct timing_generator *optc)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-       uint32_t blank_en;
-       uint32_t blank_state;
-
-       REG_GET_2(OTG_BLANK_CONTROL,
-                       OTG_BLANK_DATA_EN, &blank_en,
-                       OTG_CURRENT_BLANK_STATE, &blank_state);
-
-       return blank_en && blank_state;
-}
-
-void optc1_enable_optc_clock(struct timing_generator *optc, bool enable)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       if (enable) {
-               REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL,
-                               OPTC_INPUT_CLK_EN, 1,
-                               OPTC_INPUT_CLK_GATE_DIS, 1);
-
-               REG_WAIT(OPTC_INPUT_CLOCK_CONTROL,
-                               OPTC_INPUT_CLK_ON, 1,
-                               1, 1000);
-
-               /* Enable clock */
-               REG_UPDATE_2(OTG_CLOCK_CONTROL,
-                               OTG_CLOCK_EN, 1,
-                               OTG_CLOCK_GATE_DIS, 1);
-               REG_WAIT(OTG_CLOCK_CONTROL,
-                               OTG_CLOCK_ON, 1,
-                               1, 1000);
-       } else  {
-
-               //last chance to clear underflow, otherwise, it will always there due to clock is off.
-               if (optc->funcs->is_optc_underflow_occurred(optc) == true)
-                       optc->funcs->clear_optc_underflow(optc);
-
-               REG_UPDATE_2(OTG_CLOCK_CONTROL,
-                               OTG_CLOCK_GATE_DIS, 0,
-                               OTG_CLOCK_EN, 0);
-
-               REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL,
-                               OPTC_INPUT_CLK_GATE_DIS, 0,
-                               OPTC_INPUT_CLK_EN, 0);
-       }
-}
-
-/**
- * optc1_enable_crtc() - Enable CRTC - call ASIC Control Object to enable Timing generator.
- *
- * @optc: timing_generator instance.
- */
-static bool optc1_enable_crtc(struct timing_generator *optc)
-{
-       /* TODO FPGA wait for answer
-        * OTG_MASTER_UPDATE_MODE != CRTC_MASTER_UPDATE_MODE
-        * OTG_MASTER_UPDATE_LOCK != CRTC_MASTER_UPDATE_LOCK
-        */
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       /* opp instance for OTG. For DCN1.0, ODM is remoed.
-        * OPP and OPTC should 1:1 mapping
-        */
-       REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
-                       OPTC_SRC_SEL, optc->inst);
-
-       /* VTG enable first is for HW workaround */
-       REG_UPDATE(CONTROL,
-                       VTG0_ENABLE, 1);
-
-       REG_SEQ_START();
-
-       /* Enable CRTC */
-       REG_UPDATE_2(OTG_CONTROL,
-                       OTG_DISABLE_POINT_CNTL, 3,
-                       OTG_MASTER_EN, 1);
-
-       REG_SEQ_SUBMIT();
-       REG_SEQ_WAIT_DONE();
-
-       return true;
-}
-
-/* disable_crtc - call ASIC Control Object to disable Timing generator. */
-bool optc1_disable_crtc(struct timing_generator *optc)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       /* disable otg request until end of the first line
-        * in the vertical blank region
-        */
-       REG_UPDATE_2(OTG_CONTROL,
-                       OTG_DISABLE_POINT_CNTL, 3,
-                       OTG_MASTER_EN, 0);
-
-       REG_UPDATE(CONTROL,
-                       VTG0_ENABLE, 0);
-
-       /* CRTC disabled, so disable  clock. */
-       REG_WAIT(OTG_CLOCK_CONTROL,
-                       OTG_BUSY, 0,
-                       1, 100000);
-
-       return true;
-}
-
-
-void optc1_program_blank_color(
-               struct timing_generator *optc,
-               const struct tg_color *black_color)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       REG_SET_3(OTG_BLACK_COLOR, 0,
-                       OTG_BLACK_COLOR_B_CB, black_color->color_b_cb,
-                       OTG_BLACK_COLOR_G_Y, black_color->color_g_y,
-                       OTG_BLACK_COLOR_R_CR, black_color->color_r_cr);
-}
-
-bool optc1_validate_timing(
-       struct timing_generator *optc,
-       const struct dc_crtc_timing *timing)
-{
-       uint32_t v_blank;
-       uint32_t h_blank;
-       uint32_t min_v_blank;
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       ASSERT(timing != NULL);
-
-       v_blank = (timing->v_total - timing->v_addressable -
-                                       timing->v_border_top - timing->v_border_bottom);
-
-       h_blank = (timing->h_total - timing->h_addressable -
-               timing->h_border_right -
-               timing->h_border_left);
-
-       if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE &&
-               timing->timing_3d_format != TIMING_3D_FORMAT_HW_FRAME_PACKING &&
-               timing->timing_3d_format != TIMING_3D_FORMAT_TOP_AND_BOTTOM &&
-               timing->timing_3d_format != TIMING_3D_FORMAT_SIDE_BY_SIDE &&
-               timing->timing_3d_format != TIMING_3D_FORMAT_FRAME_ALTERNATE &&
-               timing->timing_3d_format != TIMING_3D_FORMAT_INBAND_FA)
-               return false;
-
-       /* Temporarily blocking interlacing mode until it's supported */
-       if (timing->flags.INTERLACE == 1)
-               return false;
-
-       /* Check maximum number of pixels supported by Timing Generator
-        * (Currently will never fail, in order to fail needs display which
-        * needs more than 8192 horizontal and
-        * more than 8192 vertical total pixels)
-        */
-       if (timing->h_total > optc1->max_h_total ||
-               timing->v_total > optc1->max_v_total)
-               return false;
-
-
-       if (h_blank < optc1->min_h_blank)
-               return false;
-
-       if (timing->h_sync_width  < optc1->min_h_sync_width ||
-                timing->v_sync_width  < optc1->min_v_sync_width)
-               return false;
-
-       min_v_blank = timing->flags.INTERLACE?optc1->min_v_blank_interlace:optc1->min_v_blank;
-
-       if (v_blank < min_v_blank)
-               return false;
-
-       return true;
-
-}
-
-/*
- * get_vblank_counter
- *
- * @brief
- * Get counter for vertical blanks. use register CRTC_STATUS_FRAME_COUNT which
- * holds the counter of frames.
- *
- * @param
- * struct timing_generator *optc - [in] timing generator which controls the
- * desired CRTC
- *
- * @return
- * Counter of frames, which should equal to number of vblanks.
- */
-uint32_t optc1_get_vblank_counter(struct timing_generator *optc)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-       uint32_t frame_count;
-
-       REG_GET(OTG_STATUS_FRAME_COUNT,
-               OTG_FRAME_COUNT, &frame_count);
-
-       return frame_count;
-}
-
-void optc1_lock(struct timing_generator *optc)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       REG_SET(OTG_GLOBAL_CONTROL0, 0,
-                       OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
-       REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
-                       OTG_MASTER_UPDATE_LOCK, 1);
-
-       REG_WAIT(OTG_MASTER_UPDATE_LOCK,
-                       UPDATE_LOCK_STATUS, 1,
-                       1, 10);
-
-       TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, true);
-}
-
-void optc1_unlock(struct timing_generator *optc)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
-                       OTG_MASTER_UPDATE_LOCK, 0);
-
-       TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, false);
-}
-
-void optc1_get_position(struct timing_generator *optc,
-               struct crtc_position *position)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       REG_GET_2(OTG_STATUS_POSITION,
-                       OTG_HORZ_COUNT, &position->horizontal_count,
-                       OTG_VERT_COUNT, &position->vertical_count);
-
-       REG_GET(OTG_NOM_VERT_POSITION,
-                       OTG_VERT_COUNT_NOM, &position->nominal_vcount);
-}
-
-bool optc1_is_counter_moving(struct timing_generator *optc)
-{
-       struct crtc_position position1, position2;
-
-       optc->funcs->get_position(optc, &position1);
-       optc->funcs->get_position(optc, &position2);
-
-       if (position1.horizontal_count == position2.horizontal_count &&
-               position1.vertical_count == position2.vertical_count)
-               return false;
-       else
-               return true;
-}
-
-bool optc1_did_triggered_reset_occur(
-       struct timing_generator *optc)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-       uint32_t occurred_force, occurred_vsync;
-
-       REG_GET(OTG_FORCE_COUNT_NOW_CNTL,
-               OTG_FORCE_COUNT_NOW_OCCURRED, &occurred_force);
-
-       REG_GET(OTG_VERT_SYNC_CONTROL,
-               OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, &occurred_vsync);
-
-       return occurred_vsync != 0 || occurred_force != 0;
-}
-
-void optc1_disable_reset_trigger(struct timing_generator *optc)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       REG_WRITE(OTG_TRIGA_CNTL, 0);
-
-       REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,
-               OTG_FORCE_COUNT_NOW_CLEAR, 1);
-
-       REG_SET(OTG_VERT_SYNC_CONTROL, 0,
-               OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, 1);
-}
-
-void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-       uint32_t falling_edge;
-
-       REG_GET(OTG_V_SYNC_A_CNTL,
-                       OTG_V_SYNC_A_POL, &falling_edge);
-
-       if (falling_edge)
-               REG_SET_3(OTG_TRIGA_CNTL, 0,
-                               /* vsync signal from selected OTG pipe based
-                                * on OTG_TRIG_SOURCE_PIPE_SELECT setting
-                                */
-                               OTG_TRIGA_SOURCE_SELECT, 20,
-                               OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst,
-                               /* always detect falling edge */
-                               OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 1);
-       else
-               REG_SET_3(OTG_TRIGA_CNTL, 0,
-                               /* vsync signal from selected OTG pipe based
-                                * on OTG_TRIG_SOURCE_PIPE_SELECT setting
-                                */
-                               OTG_TRIGA_SOURCE_SELECT, 20,
-                               OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst,
-                               /* always detect rising edge */
-                               OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1);
-
-       REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,
-                       /* force H count to H_TOTAL and V count to V_TOTAL in
-                        * progressive mode and V_TOTAL-1 in interlaced mode
-                        */
-                       OTG_FORCE_COUNT_NOW_MODE, 2);
-}
-
-void optc1_enable_crtc_reset(
-               struct timing_generator *optc,
-               int source_tg_inst,
-               struct crtc_trigger_info *crtc_tp)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-       uint32_t falling_edge = 0;
-       uint32_t rising_edge = 0;
-
-       switch (crtc_tp->event) {
-
-       case CRTC_EVENT_VSYNC_RISING:
-               rising_edge = 1;
-               break;
-
-       case CRTC_EVENT_VSYNC_FALLING:
-               falling_edge = 1;
-               break;
-       }
-
-       REG_SET_4(OTG_TRIGA_CNTL, 0,
-                /* vsync signal from selected OTG pipe based
-                 * on OTG_TRIG_SOURCE_PIPE_SELECT setting
-                 */
-                 OTG_TRIGA_SOURCE_SELECT, 20,
-                 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst,
-                 /* always detect falling edge */
-                 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, rising_edge,
-                 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, falling_edge);
-
-       switch (crtc_tp->delay) {
-       case TRIGGER_DELAY_NEXT_LINE:
-               REG_SET(OTG_VERT_SYNC_CONTROL, 0,
-                               OTG_AUTO_FORCE_VSYNC_MODE, 1);
-               break;
-       case TRIGGER_DELAY_NEXT_PIXEL:
-               REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,
-                       /* force H count to H_TOTAL and V count to V_TOTAL in
-                        * progressive mode and V_TOTAL-1 in interlaced mode
-                        */
-                       OTG_FORCE_COUNT_NOW_MODE, 2);
-               break;
-       }
-}
-
-void optc1_wait_for_state(struct timing_generator *optc,
-               enum crtc_state state)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       switch (state) {
-       case CRTC_STATE_VBLANK:
-               REG_WAIT(OTG_STATUS,
-                               OTG_V_BLANK, 1,
-                               1, 100000); /* 1 vupdate at 10hz */
-               break;
-
-       case CRTC_STATE_VACTIVE:
-               REG_WAIT(OTG_STATUS,
-                               OTG_V_ACTIVE_DISP, 1,
-                               1, 100000); /* 1 vupdate at 10hz */
-               break;
-
-       default:
-               break;
-       }
-}
-
-void optc1_set_early_control(
-       struct timing_generator *optc,
-       uint32_t early_cntl)
-{
-       /* asic design change, do not need this control
-        * empty for share caller logic
-        */
-}
-
-
-void optc1_set_static_screen_control(
-       struct timing_generator *optc,
-       uint32_t event_triggers,
-       uint32_t num_frames)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       // By register spec, it only takes 8 bit value
-       if (num_frames > 0xFF)
-               num_frames = 0xFF;
-
-       /* Bit 8 is no longer applicable in RV for PSR case,
-        * set bit 8 to 0 if given
-        */
-       if ((event_triggers & STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN)
-                       != 0)
-               event_triggers = event_triggers &
-               ~STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN;
-
-       REG_SET_2(OTG_STATIC_SCREEN_CONTROL, 0,
-                       OTG_STATIC_SCREEN_EVENT_MASK, event_triggers,
-                       OTG_STATIC_SCREEN_FRAME_COUNT, num_frames);
-}
-
-static void optc1_setup_manual_trigger(struct timing_generator *optc)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       REG_SET(OTG_GLOBAL_CONTROL2, 0,
-                       MANUAL_FLOW_CONTROL_SEL, optc->inst);
-
-       REG_SET_8(OTG_TRIGA_CNTL, 0,
-                       OTG_TRIGA_SOURCE_SELECT, 22,
-                       OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst,
-                       OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1,
-                       OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 0,
-                       OTG_TRIGA_POLARITY_SELECT, 0,
-                       OTG_TRIGA_FREQUENCY_SELECT, 0,
-                       OTG_TRIGA_DELAY, 0,
-                       OTG_TRIGA_CLEAR, 1);
-}
-
-static void optc1_program_manual_trigger(struct timing_generator *optc)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       REG_SET(OTG_MANUAL_FLOW_CONTROL, 0,
-                       MANUAL_FLOW_CONTROL, 1);
-
-       REG_SET(OTG_MANUAL_FLOW_CONTROL, 0,
-                       MANUAL_FLOW_CONTROL, 0);
-}
-
-/**
- * optc1_set_drr() - Program dynamic refresh rate registers m_OTGx_OTG_V_TOTAL_*.
- *
- * @optc: timing_generator instance.
- * @params: parameters used for Dynamic Refresh Rate.
- */
-void optc1_set_drr(
-       struct timing_generator *optc,
-       const struct drr_params *params)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       if (params != NULL &&
-               params->vertical_total_max > 0 &&
-               params->vertical_total_min > 0) {
-
-               if (params->vertical_total_mid != 0) {
-
-                       REG_SET(OTG_V_TOTAL_MID, 0,
-                               OTG_V_TOTAL_MID, params->vertical_total_mid - 1);
-
-                       REG_UPDATE_2(OTG_V_TOTAL_CONTROL,
-                                       OTG_VTOTAL_MID_REPLACING_MAX_EN, 1,
-                                       OTG_VTOTAL_MID_FRAME_NUM,
-                                       (uint8_t)params->vertical_total_mid_frame_num);
-
-               }
-
-               optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1);
-
-               REG_UPDATE_5(OTG_V_TOTAL_CONTROL,
-                               OTG_V_TOTAL_MIN_SEL, 1,
-                               OTG_V_TOTAL_MAX_SEL, 1,
-                               OTG_FORCE_LOCK_ON_EVENT, 0,
-                               OTG_SET_V_TOTAL_MIN_MASK_EN, 0,
-                               OTG_SET_V_TOTAL_MIN_MASK, 0);
-       }
-
-       // Setup manual flow control for EOF via TRIG_A
-       optc->funcs->setup_manual_trigger(optc);
-}
-
-void optc1_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       REG_SET(OTG_V_TOTAL_MAX, 0,
-               OTG_V_TOTAL_MAX, vtotal_max);
-
-       REG_SET(OTG_V_TOTAL_MIN, 0,
-               OTG_V_TOTAL_MIN, vtotal_min);
-}
-
-static void optc1_set_test_pattern(
-       struct timing_generator *optc,
-       /* TODO: replace 'controller_dp_test_pattern' by 'test_pattern_mode'
-        * because this is not DP-specific (which is probably somewhere in DP
-        * encoder) */
-       enum controller_dp_test_pattern test_pattern,
-       enum dc_color_depth color_depth)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-       enum test_pattern_color_format bit_depth;
-       enum test_pattern_dyn_range dyn_range;
-       enum test_pattern_mode mode;
-       uint32_t pattern_mask;
-       uint32_t pattern_data;
-       /* color ramp generator mixes 16-bits color */
-       uint32_t src_bpc = 16;
-       /* requested bpc */
-       uint32_t dst_bpc;
-       uint32_t index;
-       /* RGB values of the color bars.
-        * Produce two RGB colors: RGB0 - white (all Fs)
-        * and RGB1 - black (all 0s)
-        * (three RGB components for two colors)
-        */
-       uint16_t src_color[6] = {0xFFFF, 0xFFFF, 0xFFFF, 0x0000,
-                                               0x0000, 0x0000};
-       /* dest color (converted to the specified color format) */
-       uint16_t dst_color[6];
-       uint32_t inc_base;
-
-       /* translate to bit depth */
-       switch (color_depth) {
-       case COLOR_DEPTH_666:
-               bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_6;
-       break;
-       case COLOR_DEPTH_888:
-               bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8;
-       break;
-       case COLOR_DEPTH_101010:
-               bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_10;
-       break;
-       case COLOR_DEPTH_121212:
-               bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_12;
-       break;
-       default:
-               bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8;
-       break;
-       }
-
-       switch (test_pattern) {
-       case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES:
-       case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA:
-       {
-               dyn_range = (test_pattern ==
-                               CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA ?
-                               TEST_PATTERN_DYN_RANGE_CEA :
-                               TEST_PATTERN_DYN_RANGE_VESA);
-               mode = TEST_PATTERN_MODE_COLORSQUARES_RGB;
-
-               REG_UPDATE_2(OTG_TEST_PATTERN_PARAMETERS,
-                               OTG_TEST_PATTERN_VRES, 6,
-                               OTG_TEST_PATTERN_HRES, 6);
-
-               REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL,
-                               OTG_TEST_PATTERN_EN, 1,
-                               OTG_TEST_PATTERN_MODE, mode,
-                               OTG_TEST_PATTERN_DYNAMIC_RANGE, dyn_range,
-                               OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth);
-       }
-       break;
-
-       case CONTROLLER_DP_TEST_PATTERN_VERTICALBARS:
-       case CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS:
-       {
-               mode = (test_pattern ==
-                       CONTROLLER_DP_TEST_PATTERN_VERTICALBARS ?
-                       TEST_PATTERN_MODE_VERTICALBARS :
-                       TEST_PATTERN_MODE_HORIZONTALBARS);
-
-               switch (bit_depth) {
-               case TEST_PATTERN_COLOR_FORMAT_BPC_6:
-                       dst_bpc = 6;
-               break;
-               case TEST_PATTERN_COLOR_FORMAT_BPC_8:
-                       dst_bpc = 8;
-               break;
-               case TEST_PATTERN_COLOR_FORMAT_BPC_10:
-                       dst_bpc = 10;
-               break;
-               default:
-                       dst_bpc = 8;
-               break;
-               }
-
-               /* adjust color to the required colorFormat */
-               for (index = 0; index < 6; index++) {
-                       /* dst = 2^dstBpc * src / 2^srcBpc = src >>
-                        * (srcBpc - dstBpc);
-                        */
-                       dst_color[index] =
-                               src_color[index] >> (src_bpc - dst_bpc);
-               /* CRTC_TEST_PATTERN_DATA has 16 bits,
-                * lowest 6 are hardwired to ZERO
-                * color bits should be left aligned to MSB
-                * XXXXXXXXXX000000 for 10 bit,
-                * XXXXXXXX00000000 for 8 bit and XXXXXX0000000000 for 6
-                */
-                       dst_color[index] <<= (16 - dst_bpc);
-               }
-
-               REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0);
-
-               /* We have to write the mask before data, similar to pipeline.
-                * For example, for 8 bpc, if we want RGB0 to be magenta,
-                * and RGB1 to be cyan,
-                * we need to make 7 writes:
-                * MASK   DATA
-                * 000001 00000000 00000000                     set mask to R0
-                * 000010 11111111 00000000     R0 255, 0xFF00, set mask to G0
-                * 000100 00000000 00000000     G0 0,   0x0000, set mask to B0
-                * 001000 11111111 00000000     B0 255, 0xFF00, set mask to R1
-                * 010000 00000000 00000000     R1 0,   0x0000, set mask to G1
-                * 100000 11111111 00000000     G1 255, 0xFF00, set mask to B1
-                * 100000 11111111 00000000     B1 255, 0xFF00
-                *
-                * we will make a loop of 6 in which we prepare the mask,
-                * then write, then prepare the color for next write.
-                * first iteration will write mask only,
-                * but each next iteration color prepared in
-                * previous iteration will be written within new mask,
-                * the last component will written separately,
-                * mask is not changing between 6th and 7th write
-                * and color will be prepared by last iteration
-                */
-
-               /* write color, color values mask in CRTC_TEST_PATTERN_MASK
-                * is B1, G1, R1, B0, G0, R0
-                */
-               pattern_data = 0;
-               for (index = 0; index < 6; index++) {
-                       /* prepare color mask, first write PATTERN_DATA
-                        * will have all zeros
-                        */
-                       pattern_mask = (1 << index);
-
-                       /* write color component */
-                       REG_SET_2(OTG_TEST_PATTERN_COLOR, 0,
-                                       OTG_TEST_PATTERN_MASK, pattern_mask,
-                                       OTG_TEST_PATTERN_DATA, pattern_data);
-
-                       /* prepare next color component,
-                        * will be written in the next iteration
-                        */
-                       pattern_data = dst_color[index];
-               }
-               /* write last color component,
-                * it's been already prepared in the loop
-                */
-               REG_SET_2(OTG_TEST_PATTERN_COLOR, 0,
-                               OTG_TEST_PATTERN_MASK, pattern_mask,
-                               OTG_TEST_PATTERN_DATA, pattern_data);
-
-               /* enable test pattern */
-               REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL,
-                               OTG_TEST_PATTERN_EN, 1,
-                               OTG_TEST_PATTERN_MODE, mode,
-                               OTG_TEST_PATTERN_DYNAMIC_RANGE, 0,
-                               OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth);
-       }
-       break;
-
-       case CONTROLLER_DP_TEST_PATTERN_COLORRAMP:
-       {
-               mode = (bit_depth ==
-                       TEST_PATTERN_COLOR_FORMAT_BPC_10 ?
-                       TEST_PATTERN_MODE_DUALRAMP_RGB :
-                       TEST_PATTERN_MODE_SINGLERAMP_RGB);
-
-               switch (bit_depth) {
-               case TEST_PATTERN_COLOR_FORMAT_BPC_6:
-                       dst_bpc = 6;
-               break;
-               case TEST_PATTERN_COLOR_FORMAT_BPC_8:
-                       dst_bpc = 8;
-               break;
-               case TEST_PATTERN_COLOR_FORMAT_BPC_10:
-                       dst_bpc = 10;
-               break;
-               default:
-                       dst_bpc = 8;
-               break;
-               }
-
-               /* increment for the first ramp for one color gradation
-                * 1 gradation for 6-bit color is 2^10
-                * gradations in 16-bit color
-                */
-               inc_base = (src_bpc - dst_bpc);
-
-               switch (bit_depth) {
-               case TEST_PATTERN_COLOR_FORMAT_BPC_6:
-               {
-                       REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS,
-                                       OTG_TEST_PATTERN_INC0, inc_base,
-                                       OTG_TEST_PATTERN_INC1, 0,
-                                       OTG_TEST_PATTERN_HRES, 6,
-                                       OTG_TEST_PATTERN_VRES, 6,
-                                       OTG_TEST_PATTERN_RAMP0_OFFSET, 0);
-               }
-               break;
-               case TEST_PATTERN_COLOR_FORMAT_BPC_8:
-               {
-                       REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS,
-                                       OTG_TEST_PATTERN_INC0, inc_base,
-                                       OTG_TEST_PATTERN_INC1, 0,
-                                       OTG_TEST_PATTERN_HRES, 8,
-                                       OTG_TEST_PATTERN_VRES, 6,
-                                       OTG_TEST_PATTERN_RAMP0_OFFSET, 0);
-               }
-               break;
-               case TEST_PATTERN_COLOR_FORMAT_BPC_10:
-               {
-                       REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS,
-                                       OTG_TEST_PATTERN_INC0, inc_base,
-                                       OTG_TEST_PATTERN_INC1, inc_base + 2,
-                                       OTG_TEST_PATTERN_HRES, 8,
-                                       OTG_TEST_PATTERN_VRES, 5,
-                                       OTG_TEST_PATTERN_RAMP0_OFFSET, 384 << 6);
-               }
-               break;
-               default:
-               break;
-               }
-
-               REG_WRITE(OTG_TEST_PATTERN_COLOR, 0);
-
-               /* enable test pattern */
-               REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0);
-
-               REG_SET_4(OTG_TEST_PATTERN_CONTROL, 0,
-                               OTG_TEST_PATTERN_EN, 1,
-                               OTG_TEST_PATTERN_MODE, mode,
-                               OTG_TEST_PATTERN_DYNAMIC_RANGE, 0,
-                               OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth);
-       }
-       break;
-       case CONTROLLER_DP_TEST_PATTERN_VIDEOMODE:
-       {
-               REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0);
-               REG_WRITE(OTG_TEST_PATTERN_COLOR, 0);
-               REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0);
-       }
-       break;
-       default:
-               break;
-
-       }
-}
-
-void optc1_get_crtc_scanoutpos(
-       struct timing_generator *optc,
-       uint32_t *v_blank_start,
-       uint32_t *v_blank_end,
-       uint32_t *h_position,
-       uint32_t *v_position)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-       struct crtc_position position;
-
-       REG_GET_2(OTG_V_BLANK_START_END,
-                       OTG_V_BLANK_START, v_blank_start,
-                       OTG_V_BLANK_END, v_blank_end);
-
-       optc1_get_position(optc, &position);
-
-       *h_position = position.horizontal_count;
-       *v_position = position.vertical_count;
-}
-
-static void optc1_enable_stereo(struct timing_generator *optc,
-       const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       if (flags) {
-               uint32_t stereo_en;
-               stereo_en = flags->FRAME_PACKED == 0 ? 1 : 0;
-
-               if (flags->PROGRAM_STEREO)
-                       REG_UPDATE_3(OTG_STEREO_CONTROL,
-                               OTG_STEREO_EN, stereo_en,
-                               OTG_STEREO_SYNC_OUTPUT_LINE_NUM, 0,
-                               OTG_STEREO_SYNC_OUTPUT_POLARITY, flags->RIGHT_EYE_POLARITY == 0 ? 0 : 1);
-
-               if (flags->PROGRAM_POLARITY)
-                       REG_UPDATE(OTG_STEREO_CONTROL,
-                               OTG_STEREO_EYE_FLAG_POLARITY,
-                               flags->RIGHT_EYE_POLARITY == 0 ? 0 : 1);
-
-               if (flags->DISABLE_STEREO_DP_SYNC)
-                       REG_UPDATE(OTG_STEREO_CONTROL,
-                               OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, 1);
-
-               if (flags->PROGRAM_STEREO)
-                       REG_UPDATE_2(OTG_3D_STRUCTURE_CONTROL,
-                               OTG_3D_STRUCTURE_EN, flags->FRAME_PACKED,
-                               OTG_3D_STRUCTURE_STEREO_SEL_OVR, flags->FRAME_PACKED);
-
-       }
-}
-
-void optc1_program_stereo(struct timing_generator *optc,
-       const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags)
-{
-       if (flags->PROGRAM_STEREO)
-               optc1_enable_stereo(optc, timing, flags);
-       else
-               optc1_disable_stereo(optc);
-}
-
-
-bool optc1_is_stereo_left_eye(struct timing_generator *optc)
-{
-       bool ret = false;
-       uint32_t left_eye = 0;
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       REG_GET(OTG_STEREO_STATUS,
-               OTG_STEREO_CURRENT_EYE, &left_eye);
-       if (left_eye == 1)
-               ret = true;
-       else
-               ret = false;
-
-       return ret;
-}
-
-bool optc1_get_hw_timing(struct timing_generator *tg,
-               struct dc_crtc_timing *hw_crtc_timing)
-{
-       struct dcn_otg_state s = {0};
-
-       if (tg == NULL || hw_crtc_timing == NULL)
-               return false;
-
-       optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s);
-
-       hw_crtc_timing->h_total = s.h_total + 1;
-       hw_crtc_timing->h_addressable = s.h_total - ((s.h_total - s.h_blank_start) + s.h_blank_end);
-       hw_crtc_timing->h_front_porch = s.h_total + 1 - s.h_blank_start;
-       hw_crtc_timing->h_sync_width = s.h_sync_a_end - s.h_sync_a_start;
-
-       hw_crtc_timing->v_total = s.v_total + 1;
-       hw_crtc_timing->v_addressable = s.v_total - ((s.v_total - s.v_blank_start) + s.v_blank_end);
-       hw_crtc_timing->v_front_porch = s.v_total + 1 - s.v_blank_start;
-       hw_crtc_timing->v_sync_width = s.v_sync_a_end - s.v_sync_a_start;
-
-       return true;
-}
-
-
-void optc1_read_otg_state(struct optc *optc1,
-               struct dcn_otg_state *s)
-{
-       REG_GET(OTG_CONTROL,
-                       OTG_MASTER_EN, &s->otg_enabled);
-
-       REG_GET_2(OTG_V_BLANK_START_END,
-                       OTG_V_BLANK_START, &s->v_blank_start,
-                       OTG_V_BLANK_END, &s->v_blank_end);
-
-       REG_GET(OTG_V_SYNC_A_CNTL,
-                       OTG_V_SYNC_A_POL, &s->v_sync_a_pol);
-
-       REG_GET(OTG_V_TOTAL,
-                       OTG_V_TOTAL, &s->v_total);
-
-       REG_GET(OTG_V_TOTAL_MAX,
-                       OTG_V_TOTAL_MAX, &s->v_total_max);
-
-       REG_GET(OTG_V_TOTAL_MIN,
-                       OTG_V_TOTAL_MIN, &s->v_total_min);
-
-       REG_GET(OTG_V_TOTAL_CONTROL,
-                       OTG_V_TOTAL_MAX_SEL, &s->v_total_max_sel);
-
-       REG_GET(OTG_V_TOTAL_CONTROL,
-                       OTG_V_TOTAL_MIN_SEL, &s->v_total_min_sel);
-
-       REG_GET_2(OTG_V_SYNC_A,
-                       OTG_V_SYNC_A_START, &s->v_sync_a_start,
-                       OTG_V_SYNC_A_END, &s->v_sync_a_end);
-
-       REG_GET_2(OTG_H_BLANK_START_END,
-                       OTG_H_BLANK_START, &s->h_blank_start,
-                       OTG_H_BLANK_END, &s->h_blank_end);
-
-       REG_GET_2(OTG_H_SYNC_A,
-                       OTG_H_SYNC_A_START, &s->h_sync_a_start,
-                       OTG_H_SYNC_A_END, &s->h_sync_a_end);
-
-       REG_GET(OTG_H_SYNC_A_CNTL,
-                       OTG_H_SYNC_A_POL, &s->h_sync_a_pol);
-
-       REG_GET(OTG_H_TOTAL,
-                       OTG_H_TOTAL, &s->h_total);
-
-       REG_GET(OPTC_INPUT_GLOBAL_CONTROL,
-                       OPTC_UNDERFLOW_OCCURRED_STATUS, &s->underflow_occurred_status);
-
-       REG_GET(OTG_VERTICAL_INTERRUPT1_CONTROL,
-                       OTG_VERTICAL_INTERRUPT1_INT_ENABLE, &s->vertical_interrupt1_en);
-
-       REG_GET(OTG_VERTICAL_INTERRUPT1_POSITION,
-                               OTG_VERTICAL_INTERRUPT1_LINE_START, &s->vertical_interrupt1_line);
-
-       REG_GET(OTG_VERTICAL_INTERRUPT2_CONTROL,
-                       OTG_VERTICAL_INTERRUPT2_INT_ENABLE, &s->vertical_interrupt2_en);
-
-       REG_GET(OTG_VERTICAL_INTERRUPT2_POSITION,
-                       OTG_VERTICAL_INTERRUPT2_LINE_START, &s->vertical_interrupt2_line);
-}
-
-bool optc1_get_otg_active_size(struct timing_generator *optc,
-               uint32_t *otg_active_width,
-               uint32_t *otg_active_height)
-{
-       uint32_t otg_enabled;
-       uint32_t v_blank_start;
-       uint32_t v_blank_end;
-       uint32_t h_blank_start;
-       uint32_t h_blank_end;
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-
-       REG_GET(OTG_CONTROL,
-                       OTG_MASTER_EN, &otg_enabled);
-
-       if (otg_enabled == 0)
-               return false;
-
-       REG_GET_2(OTG_V_BLANK_START_END,
-                       OTG_V_BLANK_START, &v_blank_start,
-                       OTG_V_BLANK_END, &v_blank_end);
-
-       REG_GET_2(OTG_H_BLANK_START_END,
-                       OTG_H_BLANK_START, &h_blank_start,
-                       OTG_H_BLANK_END, &h_blank_end);
-
-       *otg_active_width = v_blank_start - v_blank_end;
-       *otg_active_height = h_blank_start - h_blank_end;
-       return true;
-}
-
-void optc1_clear_optc_underflow(struct timing_generator *optc)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       REG_UPDATE(OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, 1);
-}
-
-void optc1_tg_init(struct timing_generator *optc)
-{
-       optc1_set_blank_data_double_buffer(optc, true);
-       optc1_set_timing_double_buffer(optc, true);
-       optc1_clear_optc_underflow(optc);
-}
-
-bool optc1_is_tg_enabled(struct timing_generator *optc)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-       uint32_t otg_enabled = 0;
-
-       REG_GET(OTG_CONTROL, OTG_MASTER_EN, &otg_enabled);
-
-       return (otg_enabled != 0);
-
-}
-
-bool optc1_is_optc_underflow_occurred(struct timing_generator *optc)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-       uint32_t underflow_occurred = 0;
-
-       REG_GET(OPTC_INPUT_GLOBAL_CONTROL,
-                       OPTC_UNDERFLOW_OCCURRED_STATUS,
-                       &underflow_occurred);
-
-       return (underflow_occurred == 1);
-}
-
-bool optc1_configure_crc(struct timing_generator *optc,
-                         const struct crc_params *params)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       /* Cannot configure crc on a CRTC that is disabled */
-       if (!optc1_is_tg_enabled(optc))
-               return false;
-
-       REG_WRITE(OTG_CRC_CNTL, 0);
-
-       if (!params->enable)
-               return true;
-
-       /* Program frame boundaries */
-       /* Window A x axis start and end. */
-       REG_UPDATE_2(OTG_CRC0_WINDOWA_X_CONTROL,
-                       OTG_CRC0_WINDOWA_X_START, params->windowa_x_start,
-                       OTG_CRC0_WINDOWA_X_END, params->windowa_x_end);
-
-       /* Window A y axis start and end. */
-       REG_UPDATE_2(OTG_CRC0_WINDOWA_Y_CONTROL,
-                       OTG_CRC0_WINDOWA_Y_START, params->windowa_y_start,
-                       OTG_CRC0_WINDOWA_Y_END, params->windowa_y_end);
-
-       /* Window B x axis start and end. */
-       REG_UPDATE_2(OTG_CRC0_WINDOWB_X_CONTROL,
-                       OTG_CRC0_WINDOWB_X_START, params->windowb_x_start,
-                       OTG_CRC0_WINDOWB_X_END, params->windowb_x_end);
-
-       /* Window B y axis start and end. */
-       REG_UPDATE_2(OTG_CRC0_WINDOWB_Y_CONTROL,
-                       OTG_CRC0_WINDOWB_Y_START, params->windowb_y_start,
-                       OTG_CRC0_WINDOWB_Y_END, params->windowb_y_end);
-
-       /* Set crc mode and selection, and enable. Only using CRC0*/
-       REG_UPDATE_3(OTG_CRC_CNTL,
-                       OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0,
-                       OTG_CRC0_SELECT, params->selection,
-                       OTG_CRC_EN, 1);
-
-       return true;
-}
-
-/**
- * optc1_get_crc - Capture CRC result per component
- *
- * @optc: timing_generator instance.
- * @r_cr: 16-bit primary CRC signature for red data.
- * @g_y: 16-bit primary CRC signature for green data.
- * @b_cb: 16-bit primary CRC signature for blue data.
- *
- * This function reads the CRC signature from the OPTC registers. Notice that
- * we have three registers to keep the CRC result per color component (RGB).
- *
- * Returns:
- * If CRC is disabled, return false; otherwise, return true, and the CRC
- * results in the parameters.
- */
-bool optc1_get_crc(struct timing_generator *optc,
-                  uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)
-{
-       uint32_t field = 0;
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       REG_GET(OTG_CRC_CNTL, OTG_CRC_EN, &field);
-
-       /* Early return if CRC is not enabled for this CRTC */
-       if (!field)
-               return false;
-
-       /* OTG_CRC0_DATA_RG has the CRC16 results for the red and green component */
-       REG_GET_2(OTG_CRC0_DATA_RG,
-                 CRC0_R_CR, r_cr,
-                 CRC0_G_Y, g_y);
-
-       /* OTG_CRC0_DATA_B has the CRC16 results for the blue component */
-       REG_GET(OTG_CRC0_DATA_B,
-               CRC0_B_CB, b_cb);
-
-       return true;
-}
-
-static const struct timing_generator_funcs dcn10_tg_funcs = {
-               .validate_timing = optc1_validate_timing,
-               .program_timing = optc1_program_timing,
-               .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
-               .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
-               .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
-               .program_global_sync = optc1_program_global_sync,
-               .enable_crtc = optc1_enable_crtc,
-               .disable_crtc = optc1_disable_crtc,
-               /* used by enable_timing_synchronization. Not need for FPGA */
-               .is_counter_moving = optc1_is_counter_moving,
-               .get_position = optc1_get_position,
-               .get_frame_count = optc1_get_vblank_counter,
-               .get_scanoutpos = optc1_get_crtc_scanoutpos,
-               .get_otg_active_size = optc1_get_otg_active_size,
-               .set_early_control = optc1_set_early_control,
-               /* used by enable_timing_synchronization. Not need for FPGA */
-               .wait_for_state = optc1_wait_for_state,
-               .set_blank = optc1_set_blank,
-               .is_blanked = optc1_is_blanked,
-               .set_blank_color = optc1_program_blank_color,
-               .did_triggered_reset_occur = optc1_did_triggered_reset_occur,
-               .enable_reset_trigger = optc1_enable_reset_trigger,
-               .enable_crtc_reset = optc1_enable_crtc_reset,
-               .disable_reset_trigger = optc1_disable_reset_trigger,
-               .lock = optc1_lock,
-               .unlock = optc1_unlock,
-               .enable_optc_clock = optc1_enable_optc_clock,
-               .set_drr = optc1_set_drr,
-               .get_last_used_drr_vtotal = NULL,
-               .set_vtotal_min_max = optc1_set_vtotal_min_max,
-               .set_static_screen_control = optc1_set_static_screen_control,
-               .set_test_pattern = optc1_set_test_pattern,
-               .program_stereo = optc1_program_stereo,
-               .is_stereo_left_eye = optc1_is_stereo_left_eye,
-               .set_blank_data_double_buffer = optc1_set_blank_data_double_buffer,
-               .tg_init = optc1_tg_init,
-               .is_tg_enabled = optc1_is_tg_enabled,
-               .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
-               .clear_optc_underflow = optc1_clear_optc_underflow,
-               .get_crc = optc1_get_crc,
-               .configure_crc = optc1_configure_crc,
-               .set_vtg_params = optc1_set_vtg_params,
-               .program_manual_trigger = optc1_program_manual_trigger,
-               .setup_manual_trigger = optc1_setup_manual_trigger,
-               .get_hw_timing = optc1_get_hw_timing,
-};
-
-void dcn10_timing_generator_init(struct optc *optc1)
-{
-       optc1->base.funcs = &dcn10_tg_funcs;
-
-       optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
-       optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
-
-       optc1->min_h_blank = 32;
-       optc1->min_v_blank = 3;
-       optc1->min_v_blank_interlace = 5;
-       optc1->min_h_sync_width = 4;
-       optc1->min_v_sync_width = 1;
-}
-
-/* "Containter" vs. "pixel" is a concept within HW blocks, mostly those closer to the back-end. It works like this:
- *
- * - In most of the formats (RGB or YCbCr 4:4:4, 4:2:2 uncompressed and DSC 4:2:2 Simple) pixel rate is the same as
- *   containter rate.
- *
- * - In 4:2:0 (DSC or uncompressed) there are two pixels per container, hence the target container rate has to be
- *   halved to maintain the correct pixel rate.
- *
- * - Unlike 4:2:2 uncompressed, DSC 4:2:2 Native also has two pixels per container (this happens when DSC is applied
- *   to it) and has to be treated the same as 4:2:0, i.e. target containter rate has to be halved in this case as well.
- *
- */
-bool optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
-{
-       bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;
-
-       two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422
-                       && !timing->dsc_cfg.ycbcr422_simple);
-       return two_pix;
-}
-
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
deleted file mode 100644 (file)
index ab81594..0000000
+++ /dev/null
@@ -1,599 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- *  and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DC_TIMING_GENERATOR_DCN10_H__
-#define __DC_TIMING_GENERATOR_DCN10_H__
-
-#include "optc.h"
-
-#define DCN10TG_FROM_TG(tg)\
-       container_of(tg, struct optc, base)
-
-#define TG_COMMON_REG_LIST_DCN(inst) \
-       SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
-       SRI(OTG_VUPDATE_PARAM, OTG, inst),\
-       SRI(OTG_VREADY_PARAM, OTG, inst),\
-       SRI(OTG_BLANK_CONTROL, OTG, inst),\
-       SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
-       SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
-       SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
-       SRI(OTG_H_TOTAL, OTG, inst),\
-       SRI(OTG_H_BLANK_START_END, OTG, inst),\
-       SRI(OTG_H_SYNC_A, OTG, inst),\
-       SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\
-       SRI(OTG_H_TIMING_CNTL, OTG, inst),\
-       SRI(OTG_V_TOTAL, OTG, inst),\
-       SRI(OTG_V_BLANK_START_END, OTG, inst),\
-       SRI(OTG_V_SYNC_A, OTG, inst),\
-       SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\
-       SRI(OTG_INTERLACE_CONTROL, OTG, inst),\
-       SRI(OTG_CONTROL, OTG, inst),\
-       SRI(OTG_STEREO_CONTROL, OTG, inst),\
-       SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\
-       SRI(OTG_STEREO_STATUS, OTG, inst),\
-       SRI(OTG_V_TOTAL_MAX, OTG, inst),\
-       SRI(OTG_V_TOTAL_MID, OTG, inst),\
-       SRI(OTG_V_TOTAL_MIN, OTG, inst),\
-       SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\
-       SRI(OTG_TRIGA_CNTL, OTG, inst),\
-       SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\
-       SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\
-       SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\
-       SRI(OTG_STATUS, OTG, inst),\
-       SRI(OTG_STATUS_POSITION, OTG, inst),\
-       SRI(OTG_NOM_VERT_POSITION, OTG, inst),\
-       SRI(OTG_BLACK_COLOR, OTG, inst),\
-       SRI(OTG_CLOCK_CONTROL, OTG, inst),\
-       SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\
-       SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\
-       SRI(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\
-       SRI(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\
-       SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\
-       SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\
-       SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\
-       SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\
-       SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\
-       SRI(CONTROL, VTG, inst),\
-       SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\
-       SRI(OTG_MASTER_UPDATE_MODE, OTG, inst),\
-       SRI(OTG_GSL_CONTROL, OTG, inst),\
-       SRI(OTG_CRC_CNTL, OTG, inst),\
-       SRI(OTG_CRC0_DATA_RG, OTG, inst),\
-       SRI(OTG_CRC0_DATA_B, OTG, inst),\
-       SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\
-       SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\
-       SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\
-       SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\
-       SR(GSL_SOURCE_SELECT),\
-       SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
-       SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst)
-
-#define TG_COMMON_REG_LIST_DCN1_0(inst) \
-       TG_COMMON_REG_LIST_DCN(inst),\
-       SRI(OTG_TEST_PATTERN_PARAMETERS, OTG, inst),\
-       SRI(OTG_TEST_PATTERN_CONTROL, OTG, inst),\
-       SRI(OTG_TEST_PATTERN_COLOR, OTG, inst),\
-       SRI(OTG_MANUAL_FLOW_CONTROL, OTG, inst)
-
-
-struct dcn_optc_registers {
-       uint32_t OTG_GLOBAL_CONTROL1;
-       uint32_t OTG_GLOBAL_CONTROL2;
-       uint32_t OTG_VERT_SYNC_CONTROL;
-       uint32_t OTG_MASTER_UPDATE_MODE;
-       uint32_t OTG_GSL_CONTROL;
-       uint32_t OTG_VSTARTUP_PARAM;
-       uint32_t OTG_VUPDATE_PARAM;
-       uint32_t OTG_VREADY_PARAM;
-       uint32_t OTG_BLANK_CONTROL;
-       uint32_t OTG_MASTER_UPDATE_LOCK;
-       uint32_t OTG_GLOBAL_CONTROL0;
-       uint32_t OTG_DOUBLE_BUFFER_CONTROL;
-       uint32_t OTG_H_TOTAL;
-       uint32_t OTG_H_BLANK_START_END;
-       uint32_t OTG_H_SYNC_A;
-       uint32_t OTG_H_SYNC_A_CNTL;
-       uint32_t OTG_H_TIMING_CNTL;
-       uint32_t OTG_V_TOTAL;
-       uint32_t OTG_V_BLANK_START_END;
-       uint32_t OTG_V_SYNC_A;
-       uint32_t OTG_V_SYNC_A_CNTL;
-       uint32_t OTG_INTERLACE_CONTROL;
-       uint32_t OTG_CONTROL;
-       uint32_t OTG_STEREO_CONTROL;
-       uint32_t OTG_3D_STRUCTURE_CONTROL;
-       uint32_t OTG_STEREO_STATUS;
-       uint32_t OTG_V_TOTAL_MAX;
-       uint32_t OTG_V_TOTAL_MID;
-       uint32_t OTG_V_TOTAL_MIN;
-       uint32_t OTG_V_TOTAL_CONTROL;
-       uint32_t OTG_TRIGA_CNTL;
-       uint32_t OTG_TRIGA_MANUAL_TRIG;
-       uint32_t OTG_MANUAL_FLOW_CONTROL;
-       uint32_t OTG_FORCE_COUNT_NOW_CNTL;
-       uint32_t OTG_STATIC_SCREEN_CONTROL;
-       uint32_t OTG_STATUS_FRAME_COUNT;
-       uint32_t OTG_STATUS;
-       uint32_t OTG_STATUS_POSITION;
-       uint32_t OTG_NOM_VERT_POSITION;
-       uint32_t OTG_BLACK_COLOR;
-       uint32_t OTG_TEST_PATTERN_PARAMETERS;
-       uint32_t OTG_TEST_PATTERN_CONTROL;
-       uint32_t OTG_TEST_PATTERN_COLOR;
-       uint32_t OTG_CLOCK_CONTROL;
-       uint32_t OTG_VERTICAL_INTERRUPT0_CONTROL;
-       uint32_t OTG_VERTICAL_INTERRUPT0_POSITION;
-       uint32_t OTG_VERTICAL_INTERRUPT1_CONTROL;
-       uint32_t OTG_VERTICAL_INTERRUPT1_POSITION;
-       uint32_t OTG_VERTICAL_INTERRUPT2_CONTROL;
-       uint32_t OTG_VERTICAL_INTERRUPT2_POSITION;
-       uint32_t OPTC_INPUT_CLOCK_CONTROL;
-       uint32_t OPTC_DATA_SOURCE_SELECT;
-       uint32_t OPTC_MEMORY_CONFIG;
-       uint32_t OPTC_INPUT_GLOBAL_CONTROL;
-       uint32_t CONTROL;
-       uint32_t OTG_GSL_WINDOW_X;
-       uint32_t OTG_GSL_WINDOW_Y;
-       uint32_t OTG_VUPDATE_KEEPOUT;
-       uint32_t OTG_CRC_CNTL;
-       uint32_t OTG_CRC_CNTL2;
-       uint32_t OTG_CRC0_DATA_RG;
-       uint32_t OTG_CRC0_DATA_B;
-       uint32_t OTG_CRC1_DATA_B;
-       uint32_t OTG_CRC2_DATA_B;
-       uint32_t OTG_CRC3_DATA_B;
-       uint32_t OTG_CRC1_DATA_RG;
-       uint32_t OTG_CRC2_DATA_RG;
-       uint32_t OTG_CRC3_DATA_RG;
-       uint32_t OTG_CRC0_WINDOWA_X_CONTROL;
-       uint32_t OTG_CRC0_WINDOWA_Y_CONTROL;
-       uint32_t OTG_CRC0_WINDOWB_X_CONTROL;
-       uint32_t OTG_CRC0_WINDOWB_Y_CONTROL;
-       uint32_t OTG_CRC1_WINDOWA_X_CONTROL;
-       uint32_t OTG_CRC1_WINDOWA_Y_CONTROL;
-       uint32_t OTG_CRC1_WINDOWB_X_CONTROL;
-       uint32_t OTG_CRC1_WINDOWB_Y_CONTROL;
-       uint32_t GSL_SOURCE_SELECT;
-       uint32_t DWB_SOURCE_SELECT;
-       uint32_t OTG_DSC_START_POSITION;
-       uint32_t OPTC_DATA_FORMAT_CONTROL;
-       uint32_t OPTC_BYTES_PER_PIXEL;
-       uint32_t OPTC_WIDTH_CONTROL;
-       uint32_t OTG_DRR_CONTROL;
-       uint32_t OTG_BLANK_DATA_COLOR;
-       uint32_t OTG_BLANK_DATA_COLOR_EXT;
-       uint32_t OTG_DRR_TRIGGER_WINDOW;
-       uint32_t OTG_M_CONST_DTO0;
-       uint32_t OTG_M_CONST_DTO1;
-       uint32_t OTG_DRR_V_TOTAL_CHANGE;
-       uint32_t OTG_GLOBAL_CONTROL4;
-       uint32_t OTG_CRC0_WINDOWA_X_CONTROL_READBACK;
-       uint32_t OTG_CRC0_WINDOWA_Y_CONTROL_READBACK;
-       uint32_t OTG_CRC0_WINDOWB_X_CONTROL_READBACK;
-       uint32_t OTG_CRC0_WINDOWB_Y_CONTROL_READBACK;
-       uint32_t OTG_CRC1_WINDOWA_X_CONTROL_READBACK;
-       uint32_t OTG_CRC1_WINDOWA_Y_CONTROL_READBACK;
-       uint32_t OTG_CRC1_WINDOWB_X_CONTROL_READBACK;
-       uint32_t OTG_CRC1_WINDOWB_Y_CONTROL_READBACK;
-       uint32_t OPTC_CLOCK_CONTROL;
-};
-
-#define TG_COMMON_MASK_SH_LIST_DCN(mask_sh)\
-       SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
-       SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
-       SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
-       SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
-       SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DATA_EN, mask_sh),\
-       SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DE_MODE, mask_sh),\
-       SF(OTG0_OTG_BLANK_CONTROL, OTG_CURRENT_BLANK_STATE, mask_sh),\
-       SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\
-       SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL0, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\
-       SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\
-       SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_BLANK_DATA_DOUBLE_BUFFER_EN, mask_sh),\
-       SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mask_sh),\
-       SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, mask_sh), \
-       SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, mask_sh), \
-       SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, mask_sh), \
-       SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
-       SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_START, mask_sh),\
-       SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_END, mask_sh),\
-       SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_START, mask_sh),\
-       SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_END, mask_sh),\
-       SF(OTG0_OTG_H_SYNC_A_CNTL, OTG_H_SYNC_A_POL, mask_sh),\
-       SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_BY2, mask_sh),\
-       SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
-       SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_START, mask_sh),\
-       SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_END, mask_sh),\
-       SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_START, mask_sh),\
-       SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_END, mask_sh),\
-       SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_A_POL, mask_sh),\
-       SF(OTG0_OTG_INTERLACE_CONTROL, OTG_INTERLACE_ENABLE, mask_sh),\
-       SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
-       SF(OTG0_OTG_CONTROL, OTG_START_POINT_CNTL, mask_sh),\
-       SF(OTG0_OTG_CONTROL, OTG_DISABLE_POINT_CNTL, mask_sh),\
-       SF(OTG0_OTG_CONTROL, OTG_FIELD_NUMBER_CNTL, mask_sh),\
-       SF(OTG0_OTG_CONTROL, OTG_CURRENT_MASTER_EN_STATE, mask_sh),\
-       SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EN, mask_sh),\
-       SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_LINE_NUM, mask_sh),\
-       SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_POLARITY, mask_sh),\
-       SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EYE_FLAG_POLARITY, mask_sh),\
-       SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\
-       SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\
-       SF(OTG0_OTG_STEREO_STATUS, OTG_STEREO_CURRENT_EYE, mask_sh),\
-       SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_EN, mask_sh),\
-       SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\
-       SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\
-       SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\
-       SF(OTG0_OTG_V_TOTAL_MID, OTG_V_TOTAL_MID, mask_sh),\
-       SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\
-       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\
-       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\
-       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\
-       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK_EN, mask_sh),\
-       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\
-       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\
-       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_FRAME_NUM, mask_sh),\
-       SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\
-       SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\
-       SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\
-       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_SELECT, mask_sh),\
-       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_PIPE_SELECT, mask_sh),\
-       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_RISING_EDGE_DETECT_CNTL, mask_sh),\
-       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, mask_sh),\
-       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_POLARITY_SELECT, mask_sh),\
-       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FREQUENCY_SELECT, mask_sh),\
-       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_DELAY, mask_sh),\
-       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_CLEAR, mask_sh),\
-       SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\
-       SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_EVENT_MASK, mask_sh),\
-       SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_FRAME_COUNT, mask_sh),\
-       SF(OTG0_OTG_STATUS_FRAME_COUNT, OTG_FRAME_COUNT, mask_sh),\
-       SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
-       SF(OTG0_OTG_STATUS, OTG_V_ACTIVE_DISP, mask_sh),\
-       SF(OTG0_OTG_STATUS_POSITION, OTG_HORZ_COUNT, mask_sh),\
-       SF(OTG0_OTG_STATUS_POSITION, OTG_VERT_COUNT, mask_sh),\
-       SF(OTG0_OTG_NOM_VERT_POSITION, OTG_VERT_COUNT_NOM, mask_sh),\
-       SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_B_CB, mask_sh),\
-       SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_G_Y, mask_sh),\
-       SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_R_CR, mask_sh),\
-       SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\
-       SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\
-       SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\
-       SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\
-       SF(OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE, mask_sh),\
-       SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_START, mask_sh),\
-       SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_END, mask_sh),\
-       SF(OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_INT_ENABLE, mask_sh),\
-       SF(OTG0_OTG_VERTICAL_INTERRUPT1_POSITION, OTG_VERTICAL_INTERRUPT1_LINE_START, mask_sh),\
-       SF(OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE, mask_sh),\
-       SF(OTG0_OTG_VERTICAL_INTERRUPT2_POSITION, OTG_VERTICAL_INTERRUPT2_LINE_START, mask_sh),\
-       SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\
-       SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\
-       SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\
-       SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\
-       SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\
-       SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
-       SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
-       SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
-       SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, mask_sh),\
-       SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, mask_sh),\
-       SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_AUTO_FORCE_VSYNC_MODE, mask_sh),\
-       SF(OTG0_OTG_MASTER_UPDATE_MODE, MASTER_UPDATE_INTERLACED_MODE, mask_sh),\
-       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL0_EN, mask_sh),\
-       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL1_EN, mask_sh),\
-       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL2_EN, mask_sh),\
-       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_EN, mask_sh),\
-       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_FORCE_DELAY, mask_sh),\
-       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\
-       SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\
-       SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\
-       SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
-       SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\
-       SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\
-       SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\
-       SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_START, mask_sh),\
-       SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_END, mask_sh),\
-       SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_START, mask_sh),\
-       SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_END, mask_sh),\
-       SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_START, mask_sh),\
-       SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\
-       SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\
-       SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\
-       SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\
-       SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\
-       SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh)
-
-
-
-#define TG_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\
-       TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\
-       SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_INC0, mask_sh),\
-       SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_INC1, mask_sh),\
-       SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_VRES, mask_sh),\
-       SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_HRES, mask_sh),\
-       SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_RAMP0_OFFSET, mask_sh),\
-       SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_EN, mask_sh),\
-       SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_MODE, mask_sh),\
-       SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_DYNAMIC_RANGE, mask_sh),\
-       SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_COLOR_FORMAT, mask_sh),\
-       SF(OTG0_OTG_TEST_PATTERN_COLOR, OTG_TEST_PATTERN_MASK, mask_sh),\
-       SF(OTG0_OTG_TEST_PATTERN_COLOR, OTG_TEST_PATTERN_DATA, mask_sh),\
-       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SRC_SEL, mask_sh),\
-       SF(OTG0_OTG_MANUAL_FLOW_CONTROL, MANUAL_FLOW_CONTROL, mask_sh),\
-
-#define TG_REG_FIELD_LIST_DCN1_0(type) \
-       type VSTARTUP_START;\
-       type VUPDATE_OFFSET;\
-       type VUPDATE_WIDTH;\
-       type VREADY_OFFSET;\
-       type OTG_BLANK_DATA_EN;\
-       type OTG_BLANK_DE_MODE;\
-       type OTG_CURRENT_BLANK_STATE;\
-       type OTG_MASTER_UPDATE_LOCK;\
-       type UPDATE_LOCK_STATUS;\
-       type OTG_UPDATE_PENDING;\
-       type OTG_MASTER_UPDATE_LOCK_SEL;\
-       type OTG_BLANK_DATA_DOUBLE_BUFFER_EN;\
-       type OTG_H_TOTAL;\
-       type OTG_H_BLANK_START;\
-       type OTG_H_BLANK_END;\
-       type OTG_H_SYNC_A_START;\
-       type OTG_H_SYNC_A_END;\
-       type OTG_H_SYNC_A_POL;\
-       type OTG_H_TIMING_DIV_BY2;\
-       type OTG_V_TOTAL;\
-       type OTG_V_BLANK_START;\
-       type OTG_V_BLANK_END;\
-       type OTG_V_SYNC_A_START;\
-       type OTG_V_SYNC_A_END;\
-       type OTG_V_SYNC_A_POL;\
-       type OTG_INTERLACE_ENABLE;\
-       type OTG_MASTER_EN;\
-       type OTG_START_POINT_CNTL;\
-       type OTG_DISABLE_POINT_CNTL;\
-       type OTG_FIELD_NUMBER_CNTL;\
-       type OTG_CURRENT_MASTER_EN_STATE;\
-       type OTG_STEREO_EN;\
-       type OTG_STEREO_SYNC_OUTPUT_LINE_NUM;\
-       type OTG_STEREO_SYNC_OUTPUT_POLARITY;\
-       type OTG_STEREO_EYE_FLAG_POLARITY;\
-       type OTG_STEREO_CURRENT_EYE;\
-       type OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP;\
-       type OTG_3D_STRUCTURE_EN;\
-       type OTG_3D_STRUCTURE_V_UPDATE_MODE;\
-       type OTG_3D_STRUCTURE_STEREO_SEL_OVR;\
-       type OTG_V_TOTAL_MAX;\
-       type OTG_V_TOTAL_MID;\
-       type OTG_V_TOTAL_MIN;\
-       type OTG_V_TOTAL_MIN_SEL;\
-       type OTG_V_TOTAL_MAX_SEL;\
-       type OTG_VTOTAL_MID_REPLACING_MAX_EN;\
-       type OTG_VTOTAL_MID_FRAME_NUM;\
-       type OTG_FORCE_LOCK_ON_EVENT;\
-       type OTG_SET_V_TOTAL_MIN_MASK_EN;\
-       type OTG_SET_V_TOTAL_MIN_MASK;\
-       type OTG_FORCE_COUNT_NOW_CLEAR;\
-       type OTG_FORCE_COUNT_NOW_MODE;\
-       type OTG_FORCE_COUNT_NOW_OCCURRED;\
-       type OTG_TRIGA_SOURCE_SELECT;\
-       type OTG_TRIGA_SOURCE_PIPE_SELECT;\
-       type OTG_TRIGA_RISING_EDGE_DETECT_CNTL;\
-       type OTG_TRIGA_FALLING_EDGE_DETECT_CNTL;\
-       type OTG_TRIGA_POLARITY_SELECT;\
-       type OTG_TRIGA_FREQUENCY_SELECT;\
-       type OTG_TRIGA_DELAY;\
-       type OTG_TRIGA_CLEAR;\
-       type OTG_TRIGA_MANUAL_TRIG;\
-       type OTG_STATIC_SCREEN_EVENT_MASK;\
-       type OTG_STATIC_SCREEN_FRAME_COUNT;\
-       type OTG_FRAME_COUNT;\
-       type OTG_V_BLANK;\
-       type OTG_V_ACTIVE_DISP;\
-       type OTG_HORZ_COUNT;\
-       type OTG_VERT_COUNT;\
-       type OTG_VERT_COUNT_NOM;\
-       type OTG_BLACK_COLOR_B_CB;\
-       type OTG_BLACK_COLOR_G_Y;\
-       type OTG_BLACK_COLOR_R_CR;\
-       type OTG_BLANK_DATA_COLOR_BLUE_CB;\
-       type OTG_BLANK_DATA_COLOR_GREEN_Y;\
-       type OTG_BLANK_DATA_COLOR_RED_CR;\
-       type OTG_BLANK_DATA_COLOR_BLUE_CB_EXT;\
-       type OTG_BLANK_DATA_COLOR_GREEN_Y_EXT;\
-       type OTG_BLANK_DATA_COLOR_RED_CR_EXT;\
-       type OTG_VTOTAL_MID_REPLACING_MIN_EN;\
-       type OTG_TEST_PATTERN_INC0;\
-       type OTG_TEST_PATTERN_INC1;\
-       type OTG_TEST_PATTERN_VRES;\
-       type OTG_TEST_PATTERN_HRES;\
-       type OTG_TEST_PATTERN_RAMP0_OFFSET;\
-       type OTG_TEST_PATTERN_EN;\
-       type OTG_TEST_PATTERN_MODE;\
-       type OTG_TEST_PATTERN_DYNAMIC_RANGE;\
-       type OTG_TEST_PATTERN_COLOR_FORMAT;\
-       type OTG_TEST_PATTERN_MASK;\
-       type OTG_TEST_PATTERN_DATA;\
-       type OTG_BUSY;\
-       type OTG_CLOCK_EN;\
-       type OTG_CLOCK_ON;\
-       type OTG_CLOCK_GATE_DIS;\
-       type OTG_VERTICAL_INTERRUPT0_INT_ENABLE;\
-       type OTG_VERTICAL_INTERRUPT0_LINE_START;\
-       type OTG_VERTICAL_INTERRUPT0_LINE_END;\
-       type OTG_VERTICAL_INTERRUPT1_INT_ENABLE;\
-       type OTG_VERTICAL_INTERRUPT1_LINE_START;\
-       type OTG_VERTICAL_INTERRUPT2_INT_ENABLE;\
-       type OTG_VERTICAL_INTERRUPT2_LINE_START;\
-       type OPTC_INPUT_CLK_EN;\
-       type OPTC_INPUT_CLK_ON;\
-       type OPTC_INPUT_CLK_GATE_DIS;\
-       type OPTC_UNDERFLOW_OCCURRED_STATUS;\
-       type OPTC_UNDERFLOW_CLEAR;\
-       type OPTC_SRC_SEL;\
-       type VTG0_ENABLE;\
-       type VTG0_FP2;\
-       type VTG0_VCOUNT_INIT;\
-       type OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED;\
-       type OTG_FORCE_VSYNC_NEXT_LINE_CLEAR;\
-       type OTG_AUTO_FORCE_VSYNC_MODE;\
-       type MASTER_UPDATE_INTERLACED_MODE;\
-       type OTG_GSL0_EN;\
-       type OTG_GSL1_EN;\
-       type OTG_GSL2_EN;\
-       type OTG_GSL_MASTER_EN;\
-       type OTG_GSL_FORCE_DELAY;\
-       type OTG_GSL_CHECK_ALL_FIELDS;\
-       type OTG_GSL_WINDOW_START_X;\
-       type OTG_GSL_WINDOW_END_X;\
-       type OTG_GSL_WINDOW_START_Y;\
-       type OTG_GSL_WINDOW_END_Y;\
-       type OTG_RANGE_TIMING_DBUF_UPDATE_MODE;\
-       type OTG_GSL_MASTER_MODE;\
-       type OTG_MASTER_UPDATE_LOCK_GSL_EN;\
-       type MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET;\
-       type MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET;\
-       type OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN;\
-       type OTG_CRC_CONT_EN;\
-       type OTG_CRC0_SELECT;\
-       type OTG_CRC_EN;\
-       type CRC0_R_CR;\
-       type CRC0_G_Y;\
-       type CRC0_B_CB;\
-       type CRC1_R_CR;\
-       type CRC1_G_Y;\
-       type CRC1_B_CB;\
-       type CRC2_R_CR;\
-       type CRC2_G_Y;\
-       type CRC2_B_CB;\
-       type CRC3_R_CR;\
-       type CRC3_G_Y;\
-       type CRC3_B_CB;\
-       type OTG_CRC0_WINDOWA_X_START;\
-       type OTG_CRC0_WINDOWA_X_END;\
-       type OTG_CRC0_WINDOWA_Y_START;\
-       type OTG_CRC0_WINDOWA_Y_END;\
-       type OTG_CRC0_WINDOWB_X_START;\
-       type OTG_CRC0_WINDOWB_X_END;\
-       type OTG_CRC0_WINDOWB_Y_START;\
-       type OTG_CRC0_WINDOWB_Y_END;\
-       type OTG_CRC_WINDOW_DB_EN;\
-       type OTG_CRC1_WINDOWA_X_START;\
-       type OTG_CRC1_WINDOWA_X_END;\
-       type OTG_CRC1_WINDOWA_Y_START;\
-       type OTG_CRC1_WINDOWA_Y_END;\
-       type OTG_CRC1_WINDOWB_X_START;\
-       type OTG_CRC1_WINDOWB_X_END;\
-       type OTG_CRC1_WINDOWB_Y_START;\
-       type OTG_CRC1_WINDOWB_Y_END;\
-       type GSL0_READY_SOURCE_SEL;\
-       type GSL1_READY_SOURCE_SEL;\
-       type GSL2_READY_SOURCE_SEL;\
-       type MANUAL_FLOW_CONTROL;\
-       type MANUAL_FLOW_CONTROL_SEL;
-
-#define TG_REG_FIELD_LIST(type) \
-       TG_REG_FIELD_LIST_DCN1_0(type)\
-       type OTG_V_SYNC_MODE;\
-       type OTG_DRR_TRIGGER_WINDOW_START_X;\
-       type OTG_DRR_TRIGGER_WINDOW_END_X;\
-       type OTG_DRR_V_TOTAL_CHANGE_LIMIT;\
-       type OTG_OUT_MUX;\
-       type OTG_M_CONST_DTO_PHASE;\
-       type OTG_M_CONST_DTO_MODULO;\
-       type MASTER_UPDATE_LOCK_DB_X;\
-       type MASTER_UPDATE_LOCK_DB_Y;\
-       type MASTER_UPDATE_LOCK_DB_EN;\
-       type GLOBAL_UPDATE_LOCK_EN;\
-       type DIG_UPDATE_LOCATION;\
-       type OTG_DSC_START_POSITION_X;\
-       type OTG_DSC_START_POSITION_LINE_NUM;\
-       type OPTC_NUM_OF_INPUT_SEGMENT;\
-       type OPTC_SEG0_SRC_SEL;\
-       type OPTC_SEG1_SRC_SEL;\
-       type OPTC_SEG2_SRC_SEL;\
-       type OPTC_SEG3_SRC_SEL;\
-       type OPTC_MEM_SEL;\
-       type OPTC_DATA_FORMAT;\
-       type OPTC_DSC_MODE;\
-       type OPTC_DSC_BYTES_PER_PIXEL;\
-       type OPTC_DSC_SLICE_WIDTH;\
-       type OPTC_SEGMENT_WIDTH;\
-       type OPTC_DWB0_SOURCE_SELECT;\
-       type OPTC_DWB1_SOURCE_SELECT;\
-       type MASTER_UPDATE_LOCK_DB_START_X;\
-       type MASTER_UPDATE_LOCK_DB_END_X;\
-       type MASTER_UPDATE_LOCK_DB_START_Y;\
-       type MASTER_UPDATE_LOCK_DB_END_Y;\
-       type DIG_UPDATE_POSITION_X;\
-       type DIG_UPDATE_POSITION_Y;\
-       type OTG_H_TIMING_DIV_MODE;\
-       type OTG_DRR_TIMING_DBUF_UPDATE_MODE;\
-       type OTG_CRC_DSC_MODE;\
-       type OTG_CRC_DATA_STREAM_COMBINE_MODE;\
-       type OTG_CRC_DATA_STREAM_SPLIT_MODE;\
-       type OTG_CRC_DATA_FORMAT;\
-       type OTG_V_TOTAL_LAST_USED_BY_DRR;\
-       type OTG_DRR_TIMING_DBUF_UPDATE_PENDING;
-
-#define TG_REG_FIELD_LIST_DCN3_2(type) \
-       type OTG_H_TIMING_DIV_MODE_MANUAL;
-
-
-#define TG_REG_FIELD_LIST_DCN3_5(type) \
-       type OTG_CRC0_WINDOWA_X_START_READBACK;\
-       type OTG_CRC0_WINDOWA_X_END_READBACK;\
-       type OTG_CRC0_WINDOWA_Y_START_READBACK;\
-       type OTG_CRC0_WINDOWA_Y_END_READBACK;\
-       type OTG_CRC0_WINDOWB_X_START_READBACK;\
-       type OTG_CRC0_WINDOWB_X_END_READBACK;\
-       type OTG_CRC0_WINDOWB_Y_START_READBACK;\
-       type OTG_CRC0_WINDOWB_Y_END_READBACK; \
-       type OTG_CRC1_WINDOWA_X_START_READBACK;\
-       type OTG_CRC1_WINDOWA_X_END_READBACK;\
-       type OTG_CRC1_WINDOWA_Y_START_READBACK;\
-       type OTG_CRC1_WINDOWA_Y_END_READBACK;\
-       type OTG_CRC1_WINDOWB_X_START_READBACK;\
-       type OTG_CRC1_WINDOWB_X_END_READBACK;\
-       type OTG_CRC1_WINDOWB_Y_START_READBACK;\
-       type OTG_CRC1_WINDOWB_Y_END_READBACK;\
-       type OPTC_FGCG_REP_DIS;
-
-struct dcn_optc_shift {
-       TG_REG_FIELD_LIST(uint8_t)
-       TG_REG_FIELD_LIST_DCN3_2(uint8_t)
-       TG_REG_FIELD_LIST_DCN3_5(uint8_t)
-};
-
-struct dcn_optc_mask {
-       TG_REG_FIELD_LIST(uint32_t)
-       TG_REG_FIELD_LIST_DCN3_2(uint32_t)
-       TG_REG_FIELD_LIST_DCN3_5(uint32_t)
-};
-
-void dcn10_timing_generator_init(struct optc *optc);
-
-#endif /* __DC_TIMING_GENERATOR_DCN10_H__ */
index 93ac45802e444e68ba729c54e8c8c9f0176282c3..bd760442ff8935dbb31d8fe69ecf348c34927b42 100644 (file)
@@ -3,7 +3,7 @@
 # Makefile for DCN.
 
 DCN20 = dcn20_init.o dcn20_dpp.o dcn20_dpp_cm.o dcn20_hubp.o \
-               dcn20_mpc.o dcn20_opp.o dcn20_hubbub.o dcn20_optc.o dcn20_mmhubbub.o \
+               dcn20_mpc.o dcn20_opp.o dcn20_hubbub.o dcn20_mmhubbub.o \
                dcn20_stream_encoder.o dcn20_link_encoder.o dcn20_dccg.o \
                dcn20_vmid.o dcn20_dwb.o dcn20_dwb_scl.o
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
deleted file mode 100644 (file)
index 58bdbd8..0000000
+++ /dev/null
@@ -1,587 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "reg_helper.h"
-#include "dcn20_optc.h"
-#include "dc.h"
-
-#define REG(reg)\
-       optc1->tg_regs->reg
-
-#define CTX \
-       optc1->base.ctx
-
-#undef FN
-#define FN(reg_name, field_name) \
-       optc1->tg_shift->field_name, optc1->tg_mask->field_name
-
-/**
- * optc2_enable_crtc() - Enable CRTC - call ASIC Control Object to enable Timing generator.
- *
- * @optc: timing_generator instance.
- *
- * Return: If CRTC is enabled, return true.
- *
- */
-bool optc2_enable_crtc(struct timing_generator *optc)
-{
-       /* TODO FPGA wait for answer
-        * OTG_MASTER_UPDATE_MODE != CRTC_MASTER_UPDATE_MODE
-        * OTG_MASTER_UPDATE_LOCK != CRTC_MASTER_UPDATE_LOCK
-        */
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       /* opp instance for OTG. For DCN1.0, ODM is remoed.
-        * OPP and OPTC should 1:1 mapping
-        */
-       REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
-                       OPTC_SEG0_SRC_SEL, optc->inst);
-
-       /* VTG enable first is for HW workaround */
-       REG_UPDATE(CONTROL,
-                       VTG0_ENABLE, 1);
-
-       REG_SEQ_START();
-
-       /* Enable CRTC */
-       REG_UPDATE_2(OTG_CONTROL,
-                       OTG_DISABLE_POINT_CNTL, 3,
-                       OTG_MASTER_EN, 1);
-
-       REG_SEQ_SUBMIT();
-       REG_SEQ_WAIT_DONE();
-
-       return true;
-}
-
-/**
- * optc2_set_gsl() - Assign OTG to GSL groups,
- *                   set one of the OTGs to be master & rest are slaves
- *
- * @optc: timing_generator instance.
- * @params: pointer to gsl_params
- */
-void optc2_set_gsl(struct timing_generator *optc,
-                  const struct gsl_params *params)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-/*
- * There are (MAX_OPTC+1)/2 gsl groups available for use.
- * In each group (assign an OTG to a group by setting OTG_GSLX_EN = 1,
- * set one of the OTGs to be the master (OTG_GSL_MASTER_EN = 1) and the rest are slaves.
- */
-       REG_UPDATE_5(OTG_GSL_CONTROL,
-               OTG_GSL0_EN, params->gsl0_en,
-               OTG_GSL1_EN, params->gsl1_en,
-               OTG_GSL2_EN, params->gsl2_en,
-               OTG_GSL_MASTER_EN, params->gsl_master_en,
-               OTG_GSL_MASTER_MODE, params->gsl_master_mode);
-}
-
-
-void optc2_set_gsl_source_select(
-               struct timing_generator *optc,
-               int group_idx,
-               uint32_t gsl_ready_signal)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       switch (group_idx) {
-       case 1:
-               REG_UPDATE(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, gsl_ready_signal);
-               break;
-       case 2:
-               REG_UPDATE(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, gsl_ready_signal);
-               break;
-       case 3:
-               REG_UPDATE(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, gsl_ready_signal);
-               break;
-       default:
-               break;
-       }
-}
-
-/* Set DSC-related configuration.
- *   dsc_mode: 0 disables DSC, other values enable DSC in specified format
- *   sc_bytes_per_pixel: Bytes per pixel in u3.28 format
- *   dsc_slice_width: Slice width in pixels
- */
-void optc2_set_dsc_config(struct timing_generator *optc,
-                                       enum optc_dsc_mode dsc_mode,
-                                       uint32_t dsc_bytes_per_pixel,
-                                       uint32_t dsc_slice_width)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       REG_UPDATE(OPTC_DATA_FORMAT_CONTROL,
-               OPTC_DSC_MODE, dsc_mode);
-
-       REG_SET(OPTC_BYTES_PER_PIXEL, 0,
-               OPTC_DSC_BYTES_PER_PIXEL, dsc_bytes_per_pixel);
-
-       REG_UPDATE(OPTC_WIDTH_CONTROL,
-               OPTC_DSC_SLICE_WIDTH, dsc_slice_width);
-}
-
-/* Get DSC-related configuration.
- *   dsc_mode: 0 disables DSC, other values enable DSC in specified format
- */
-void optc2_get_dsc_status(struct timing_generator *optc,
-                                       uint32_t *dsc_mode)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       REG_GET(OPTC_DATA_FORMAT_CONTROL,
-               OPTC_DSC_MODE, dsc_mode);
-}
-
-
-/*TEMP: Need to figure out inheritance model here.*/
-bool optc2_is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
-{
-       return optc1_is_two_pixels_per_containter(timing);
-}
-
-void optc2_set_odm_bypass(struct timing_generator *optc,
-               const struct dc_crtc_timing *dc_crtc_timing)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-       uint32_t h_div_2 = 0;
-
-       REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
-                       OPTC_NUM_OF_INPUT_SEGMENT, 0,
-                       OPTC_SEG0_SRC_SEL, optc->inst,
-                       OPTC_SEG1_SRC_SEL, 0xf);
-       REG_WRITE(OTG_H_TIMING_CNTL, 0);
-
-       h_div_2 = optc2_is_two_pixels_per_containter(dc_crtc_timing);
-       REG_UPDATE(OTG_H_TIMING_CNTL,
-                       OTG_H_TIMING_DIV_BY2, h_div_2);
-       REG_SET(OPTC_MEMORY_CONFIG, 0,
-                       OPTC_MEM_SEL, 0);
-       optc1->opp_count = 1;
-}
-
-void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
-               struct dc_crtc_timing *timing)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-       int mpcc_hactive = (timing->h_addressable + timing->h_border_left + timing->h_border_right)
-                       / opp_cnt;
-       uint32_t memory_mask;
-
-       ASSERT(opp_cnt == 2);
-
-       /* TODO: In pseudocode but does not affect maximus, delete comment if we dont need on asic
-        * REG_SET(OTG_GLOBAL_CONTROL2, 0, GLOBAL_UPDATE_LOCK_EN, 1);
-        * Program OTG register MASTER_UPDATE_LOCK_DB_X/Y to the position before DP frame start
-        * REG_SET_2(OTG_GLOBAL_CONTROL1, 0,
-        *              MASTER_UPDATE_LOCK_DB_X, 160,
-        *              MASTER_UPDATE_LOCK_DB_Y, 240);
-        */
-
-       /* 2 pieces of memory required for up to 5120 displays, 4 for up to 8192,
-        * however, for ODM combine we can simplify by always using 4.
-        * To make sure there's no overlap, each instance "reserves" 2 memories and
-        * they are uniquely combined here.
-        */
-       memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);
-
-       if (REG(OPTC_MEMORY_CONFIG))
-               REG_SET(OPTC_MEMORY_CONFIG, 0,
-                       OPTC_MEM_SEL, memory_mask);
-
-       REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
-                       OPTC_NUM_OF_INPUT_SEGMENT, 1,
-                       OPTC_SEG0_SRC_SEL, opp_id[0],
-                       OPTC_SEG1_SRC_SEL, opp_id[1]);
-
-       REG_UPDATE(OPTC_WIDTH_CONTROL,
-                       OPTC_SEGMENT_WIDTH, mpcc_hactive);
-
-       REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_BY2, 1);
-       optc1->opp_count = opp_cnt;
-}
-
-void optc2_get_optc_source(struct timing_generator *optc,
-               uint32_t *num_of_src_opp,
-               uint32_t *src_opp_id_0,
-               uint32_t *src_opp_id_1)
-{
-       uint32_t num_of_input_segments;
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       REG_GET_3(OPTC_DATA_SOURCE_SELECT,
-                       OPTC_NUM_OF_INPUT_SEGMENT, &num_of_input_segments,
-                       OPTC_SEG0_SRC_SEL, src_opp_id_0,
-                       OPTC_SEG1_SRC_SEL, src_opp_id_1);
-
-       if (num_of_input_segments == 1)
-               *num_of_src_opp = 2;
-       else
-               *num_of_src_opp = 1;
-
-       /* Work around VBIOS not updating OPTC_NUM_OF_INPUT_SEGMENT */
-       if (*src_opp_id_1 == 0xf)
-               *num_of_src_opp = 1;
-}
-
-static void optc2_set_dwb_source(struct timing_generator *optc,
-                                uint32_t dwb_pipe_inst)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       if (dwb_pipe_inst == 0)
-               REG_UPDATE(DWB_SOURCE_SELECT,
-                               OPTC_DWB0_SOURCE_SELECT, optc->inst);
-       else if (dwb_pipe_inst == 1)
-               REG_UPDATE(DWB_SOURCE_SELECT,
-                               OPTC_DWB1_SOURCE_SELECT, optc->inst);
-}
-
-static void optc2_align_vblanks(
-       struct timing_generator *optc_master,
-       struct timing_generator *optc_slave,
-       uint32_t master_pixel_clock_100Hz,
-       uint32_t slave_pixel_clock_100Hz,
-       uint8_t master_clock_divider,
-       uint8_t slave_clock_divider)
-{
-       /* accessing slave OTG registers */
-       struct optc *optc1 = DCN10TG_FROM_TG(optc_slave);
-
-       uint32_t master_v_active = 0;
-       uint32_t master_h_total = 0;
-       uint32_t slave_h_total = 0;
-       uint64_t L, XY;
-       uint32_t X, Y, p = 10000;
-       uint32_t master_update_lock;
-
-       /* disable slave OTG */
-       REG_UPDATE(OTG_CONTROL, OTG_MASTER_EN, 0);
-       /* wait until disabled */
-       REG_WAIT(OTG_CONTROL,
-                        OTG_CURRENT_MASTER_EN_STATE,
-                        0, 10, 5000);
-
-       REG_GET(OTG_H_TOTAL, OTG_H_TOTAL, &slave_h_total);
-
-       /* assign slave OTG to be controlled by master update lock */
-       REG_SET(OTG_GLOBAL_CONTROL0, 0,
-                       OTG_MASTER_UPDATE_LOCK_SEL, optc_master->inst);
-
-       /* accessing master OTG registers */
-       optc1 = DCN10TG_FROM_TG(optc_master);
-
-       /* saving update lock state, not sure if it's needed */
-       REG_GET(OTG_MASTER_UPDATE_LOCK,
-                       OTG_MASTER_UPDATE_LOCK, &master_update_lock);
-       /* unlocking master OTG */
-       REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
-                       OTG_MASTER_UPDATE_LOCK, 0);
-
-       REG_GET(OTG_V_BLANK_START_END,
-                       OTG_V_BLANK_START, &master_v_active);
-       REG_GET(OTG_H_TOTAL, OTG_H_TOTAL, &master_h_total);
-
-       /* calculate when to enable slave OTG */
-       L = (uint64_t)p * slave_h_total * master_pixel_clock_100Hz;
-       L = div_u64(L, master_h_total);
-       L = div_u64(L, slave_pixel_clock_100Hz);
-       XY = div_u64(L, p);
-       Y = master_v_active - XY - 1;
-       X = div_u64(((XY + 1) * p - L) * master_h_total, p * master_clock_divider);
-
-       /*
-        * set master OTG to unlock when V/H
-        * counters reach calculated values
-        */
-       REG_UPDATE(OTG_GLOBAL_CONTROL1,
-                          MASTER_UPDATE_LOCK_DB_EN, 1);
-       REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
-                                MASTER_UPDATE_LOCK_DB_X,
-                                X,
-                                MASTER_UPDATE_LOCK_DB_Y,
-                                Y);
-
-       /* lock master OTG */
-       REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
-                       OTG_MASTER_UPDATE_LOCK, 1);
-       REG_WAIT(OTG_MASTER_UPDATE_LOCK,
-                        UPDATE_LOCK_STATUS, 1, 1, 10);
-
-       /* accessing slave OTG registers */
-       optc1 = DCN10TG_FROM_TG(optc_slave);
-
-       /*
-        * enable slave OTG, the OTG is locked with
-        * master's update lock, so it will not run
-        */
-       REG_UPDATE(OTG_CONTROL,
-                          OTG_MASTER_EN, 1);
-
-       /* accessing master OTG registers */
-       optc1 = DCN10TG_FROM_TG(optc_master);
-
-       /*
-        * unlock master OTG. When master H/V counters reach
-        * DB_XY point, slave OTG will start
-        */
-       REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
-                       OTG_MASTER_UPDATE_LOCK, 0);
-
-       /* accessing slave OTG registers */
-       optc1 = DCN10TG_FROM_TG(optc_slave);
-
-       /* wait for slave OTG to start running*/
-       REG_WAIT(OTG_CONTROL,
-                        OTG_CURRENT_MASTER_EN_STATE,
-                        1, 10, 5000);
-
-       /* accessing master OTG registers */
-       optc1 = DCN10TG_FROM_TG(optc_master);
-
-       /* disable the XY point*/
-       REG_UPDATE(OTG_GLOBAL_CONTROL1,
-                          MASTER_UPDATE_LOCK_DB_EN, 0);
-       REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
-                                MASTER_UPDATE_LOCK_DB_X,
-                                0,
-                                MASTER_UPDATE_LOCK_DB_Y,
-                                0);
-
-       /*restore master update lock*/
-       REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
-                       OTG_MASTER_UPDATE_LOCK, master_update_lock);
-
-       /* accessing slave OTG registers */
-       optc1 = DCN10TG_FROM_TG(optc_slave);
-       /* restore slave to be controlled by it's own */
-       REG_SET(OTG_GLOBAL_CONTROL0, 0,
-                       OTG_MASTER_UPDATE_LOCK_SEL, optc_slave->inst);
-
-}
-
-void optc2_triplebuffer_lock(struct timing_generator *optc)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       REG_SET(OTG_GLOBAL_CONTROL0, 0,
-               OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
-
-       REG_SET(OTG_VUPDATE_KEEPOUT, 0,
-               OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 1);
-
-       REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
-               OTG_MASTER_UPDATE_LOCK, 1);
-
-       REG_WAIT(OTG_MASTER_UPDATE_LOCK,
-                       UPDATE_LOCK_STATUS, 1,
-                       1, 10);
-}
-
-void optc2_triplebuffer_unlock(struct timing_generator *optc)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
-               OTG_MASTER_UPDATE_LOCK, 0);
-
-       REG_SET(OTG_VUPDATE_KEEPOUT, 0,
-               OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 0);
-
-}
-
-void optc2_lock_doublebuffer_enable(struct timing_generator *optc)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-       uint32_t v_blank_start = 0;
-       uint32_t h_blank_start = 0;
-
-       REG_UPDATE(OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, 1);
-
-       REG_UPDATE_2(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 1,
-                       DIG_UPDATE_LOCATION, 20);
-
-       REG_GET(OTG_V_BLANK_START_END, OTG_V_BLANK_START, &v_blank_start);
-
-       REG_GET(OTG_H_BLANK_START_END, OTG_H_BLANK_START, &h_blank_start);
-
-       REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
-                       MASTER_UPDATE_LOCK_DB_X,
-                       (h_blank_start - 200 - 1) / optc1->opp_count,
-                       MASTER_UPDATE_LOCK_DB_Y,
-                       v_blank_start - 1);
-
-       REG_SET_3(OTG_VUPDATE_KEEPOUT, 0,
-               MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, 0,
-               MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, 100,
-               OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 1);
-}
-
-void optc2_lock_doublebuffer_disable(struct timing_generator *optc)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
-                               MASTER_UPDATE_LOCK_DB_X,
-                               0,
-                               MASTER_UPDATE_LOCK_DB_Y,
-                               0);
-
-       REG_UPDATE_2(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 0,
-                               DIG_UPDATE_LOCATION, 0);
-
-       REG_UPDATE(OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, 0);
-}
-
-void optc2_setup_manual_trigger(struct timing_generator *optc)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       /* Set the min/max selectors unconditionally so that
-        * DMCUB fw may change OTG timings when necessary
-        * TODO: Remove the w/a after fixing the issue in DMCUB firmware
-        */
-       REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
-                                OTG_V_TOTAL_MIN_SEL, 1,
-                                OTG_V_TOTAL_MAX_SEL, 1,
-                                OTG_FORCE_LOCK_ON_EVENT, 0,
-                                OTG_SET_V_TOTAL_MIN_MASK, (1 << 1)); /* TRIGA */
-
-       REG_SET_8(OTG_TRIGA_CNTL, 0,
-                       OTG_TRIGA_SOURCE_SELECT, 21,
-                       OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst,
-                       OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1,
-                       OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 0,
-                       OTG_TRIGA_POLARITY_SELECT, 0,
-                       OTG_TRIGA_FREQUENCY_SELECT, 0,
-                       OTG_TRIGA_DELAY, 0,
-                       OTG_TRIGA_CLEAR, 1);
-}
-
-void optc2_program_manual_trigger(struct timing_generator *optc)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       REG_SET(OTG_TRIGA_MANUAL_TRIG, 0,
-                       OTG_TRIGA_MANUAL_TRIG, 1);
-}
-
-bool optc2_configure_crc(struct timing_generator *optc,
-                         const struct crc_params *params)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       REG_SET_2(OTG_CRC_CNTL2, 0,
-                       OTG_CRC_DSC_MODE, params->dsc_mode,
-                       OTG_CRC_DATA_STREAM_COMBINE_MODE, params->odm_mode);
-
-       return optc1_configure_crc(optc, params);
-}
-
-
-void optc2_get_last_used_drr_vtotal(struct timing_generator *optc, uint32_t *refresh_rate)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       REG_GET(OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, refresh_rate);
-}
-
-static struct timing_generator_funcs dcn20_tg_funcs = {
-               .validate_timing = optc1_validate_timing,
-               .program_timing = optc1_program_timing,
-               .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
-               .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
-               .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
-               .program_global_sync = optc1_program_global_sync,
-               .enable_crtc = optc2_enable_crtc,
-               .disable_crtc = optc1_disable_crtc,
-               /* used by enable_timing_synchronization. Not need for FPGA */
-               .is_counter_moving = optc1_is_counter_moving,
-               .get_position = optc1_get_position,
-               .get_frame_count = optc1_get_vblank_counter,
-               .get_scanoutpos = optc1_get_crtc_scanoutpos,
-               .get_otg_active_size = optc1_get_otg_active_size,
-               .set_early_control = optc1_set_early_control,
-               /* used by enable_timing_synchronization. Not need for FPGA */
-               .wait_for_state = optc1_wait_for_state,
-               .set_blank = optc1_set_blank,
-               .is_blanked = optc1_is_blanked,
-               .set_blank_color = optc1_program_blank_color,
-               .enable_reset_trigger = optc1_enable_reset_trigger,
-               .enable_crtc_reset = optc1_enable_crtc_reset,
-               .did_triggered_reset_occur = optc1_did_triggered_reset_occur,
-               .triplebuffer_lock = optc2_triplebuffer_lock,
-               .triplebuffer_unlock = optc2_triplebuffer_unlock,
-               .disable_reset_trigger = optc1_disable_reset_trigger,
-               .lock = optc1_lock,
-               .unlock = optc1_unlock,
-               .lock_doublebuffer_enable = optc2_lock_doublebuffer_enable,
-               .lock_doublebuffer_disable = optc2_lock_doublebuffer_disable,
-               .enable_optc_clock = optc1_enable_optc_clock,
-               .set_drr = optc1_set_drr,
-               .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
-               .set_vtotal_min_max = optc1_set_vtotal_min_max,
-               .set_static_screen_control = optc1_set_static_screen_control,
-               .program_stereo = optc1_program_stereo,
-               .is_stereo_left_eye = optc1_is_stereo_left_eye,
-               .set_blank_data_double_buffer = optc1_set_blank_data_double_buffer,
-               .tg_init = optc1_tg_init,
-               .is_tg_enabled = optc1_is_tg_enabled,
-               .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
-               .clear_optc_underflow = optc1_clear_optc_underflow,
-               .setup_global_swap_lock = NULL,
-               .get_crc = optc1_get_crc,
-               .configure_crc = optc2_configure_crc,
-               .set_dsc_config = optc2_set_dsc_config,
-               .get_dsc_status = optc2_get_dsc_status,
-               .set_dwb_source = optc2_set_dwb_source,
-               .set_odm_bypass = optc2_set_odm_bypass,
-               .set_odm_combine = optc2_set_odm_combine,
-               .get_optc_source = optc2_get_optc_source,
-               .set_gsl = optc2_set_gsl,
-               .set_gsl_source_select = optc2_set_gsl_source_select,
-               .set_vtg_params = optc1_set_vtg_params,
-               .program_manual_trigger = optc2_program_manual_trigger,
-               .setup_manual_trigger = optc2_setup_manual_trigger,
-               .get_hw_timing = optc1_get_hw_timing,
-               .align_vblanks = optc2_align_vblanks,
-};
-
-void dcn20_timing_generator_init(struct optc *optc1)
-{
-       optc1->base.funcs = &dcn20_tg_funcs;
-
-       optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
-       optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
-
-       optc1->min_h_blank = 32;
-       optc1->min_v_blank = 3;
-       optc1->min_v_blank_interlace = 5;
-       optc1->min_h_sync_width = 4;//  Minimum HSYNC = 8 pixels asked By HW in the first place for no actual reason. Oculus Rift S will not light up with 8 as it's hsyncWidth is 6. Changing it to 4 to fix that issue.
-       optc1->min_v_sync_width = 1;
-}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
deleted file mode 100644 (file)
index f7968b9..0000000
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DC_OPTC_DCN20_H__
-#define __DC_OPTC_DCN20_H__
-
-#include "../dcn10/dcn10_optc.h"
-
-#define TG_COMMON_REG_LIST_DCN2_0(inst) \
-       TG_COMMON_REG_LIST_DCN(inst),\
-       SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
-       SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
-       SRI(OTG_GSL_WINDOW_X, OTG, inst),\
-       SRI(OTG_GSL_WINDOW_Y, OTG, inst),\
-       SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\
-       SRI(OTG_DSC_START_POSITION, OTG, inst),\
-       SRI(OTG_CRC_CNTL2, OTG, inst),\
-       SRI(OPTC_DATA_FORMAT_CONTROL, ODM, inst),\
-       SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\
-       SRI(OPTC_WIDTH_CONTROL, ODM, inst),\
-       SRI(OPTC_MEMORY_CONFIG, ODM, inst),\
-       SR(DWB_SOURCE_SELECT),\
-       SRI(OTG_MANUAL_FLOW_CONTROL, OTG, inst), \
-       SRI(OTG_DRR_CONTROL, OTG, inst)
-
-#define TG_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\
-       TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_X, mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_Y, mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL2, DIG_UPDATE_LOCATION, mask_sh),\
-       SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mask_sh),\
-       SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\
-       SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \
-       SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\
-       SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\
-       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_MODE, mask_sh), \
-       SF(OTG0_OTG_GSL_CONTROL, OTG_MASTER_UPDATE_LOCK_GSL_EN, mask_sh), \
-       SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_X, mask_sh), \
-       SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_LINE_NUM, mask_sh),\
-       SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DSC_MODE, mask_sh),\
-       SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_COMBINE_MODE, mask_sh),\
-       SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_SPLIT_MODE, mask_sh),\
-       SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_FORMAT, mask_sh),\
-       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG0_SRC_SEL, mask_sh),\
-       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG1_SRC_SEL, mask_sh),\
-       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, mask_sh),\
-       SF(ODM0_OPTC_MEMORY_CONFIG, OPTC_MEM_SEL, mask_sh),\
-       SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, mask_sh),\
-       SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\
-       SF(ODM0_OPTC_BYTES_PER_PIXEL, OPTC_DSC_BYTES_PER_PIXEL, mask_sh),\
-       SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, mask_sh),\
-       SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_SEGMENT_WIDTH, mask_sh),\
-       SF(DWB_SOURCE_SELECT, OPTC_DWB0_SOURCE_SELECT, mask_sh),\
-       SF(DWB_SOURCE_SELECT, OPTC_DWB1_SOURCE_SELECT, mask_sh),\
-       SF(OTG0_OTG_MANUAL_FLOW_CONTROL, MANUAL_FLOW_CONTROL, mask_sh), \
-       SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh)
-
-void dcn20_timing_generator_init(struct optc *optc);
-
-void optc2_get_last_used_drr_vtotal(struct timing_generator *optc,
-               uint32_t *refresh_rate);
-
-bool optc2_enable_crtc(struct timing_generator *optc);
-
-void optc2_set_gsl(struct timing_generator *optc,
-               const struct gsl_params *params);
-
-void optc2_set_gsl_source_select(struct timing_generator *optc,
-               int group_idx,
-               uint32_t gsl_ready_signal);
-
-void optc2_set_dsc_config(struct timing_generator *optc,
-                                       enum optc_dsc_mode dsc_mode,
-                                       uint32_t dsc_bytes_per_pixel,
-                                       uint32_t dsc_slice_width);
-
-void optc2_get_dsc_status(struct timing_generator *optc,
-                                       uint32_t *dsc_mode);
-
-void optc2_set_odm_bypass(struct timing_generator *optc,
-               const struct dc_crtc_timing *dc_crtc_timing);
-
-void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
-               struct dc_crtc_timing *timing);
-
-void optc2_get_optc_source(struct timing_generator *optc,
-               uint32_t *num_of_src_opp,
-               uint32_t *src_opp_id_0,
-               uint32_t *src_opp_id_1);
-
-void optc2_triplebuffer_lock(struct timing_generator *optc);
-void optc2_triplebuffer_unlock(struct timing_generator *optc);
-void optc2_lock_doublebuffer_disable(struct timing_generator *optc);
-void optc2_lock_doublebuffer_enable(struct timing_generator *optc);
-void optc2_setup_manual_trigger(struct timing_generator *optc);
-void optc2_program_manual_trigger(struct timing_generator *optc);
-bool optc2_is_two_pixels_per_containter(const struct dc_crtc_timing *timing);
-bool optc2_configure_crc(struct timing_generator *optc,
-                         const struct crc_params *params);
-#endif /* __DC_OPTC_DCN20_H__ */
index c069a894db925b0909d8e2331c217d620253ef2d..a101e651155500a977c4138f7050f6d83f65520b 100644 (file)
@@ -3,7 +3,7 @@
 # Makefile for DCN.
 DCN201 = dcn201_init.o \
        dcn201_hubbub.o\
-       dcn201_mpc.o dcn201_hubp.o dcn201_opp.o dcn201_optc.o dcn201_dpp.o \
+       dcn201_mpc.o dcn201_hubp.o dcn201_opp.o dcn201_dpp.o \
        dcn201_dccg.o dcn201_link_encoder.o
 
 AMD_DAL_DCN201 = $(addprefix $(AMDDALPATH)/dc/dcn201/,$(DCN201))
diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_optc.c b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_optc.c
deleted file mode 100644 (file)
index 70fcbec..0000000
+++ /dev/null
@@ -1,202 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "reg_helper.h"
-#include "dcn201_optc.h"
-#include "dcn10/dcn10_optc.h"
-#include "dc.h"
-
-#define REG(reg)\
-       optc1->tg_regs->reg
-
-#define CTX \
-       optc1->base.ctx
-
-#undef FN
-#define FN(reg_name, field_name) \
-       optc1->tg_shift->field_name, optc1->tg_mask->field_name
-
-/*TEMP: Need to figure out inheritance model here.*/
-bool optc201_is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
-{
-       return optc1_is_two_pixels_per_containter(timing);
-}
-
-static void optc201_triplebuffer_lock(struct timing_generator *optc)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       REG_SET(OTG_GLOBAL_CONTROL0, 0,
-               OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
-       REG_SET(OTG_VUPDATE_KEEPOUT, 0,
-               OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 1);
-       REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
-               OTG_MASTER_UPDATE_LOCK, 1);
-
-       REG_WAIT(OTG_MASTER_UPDATE_LOCK,
-                       UPDATE_LOCK_STATUS, 1,
-                       1, 10);
-}
-
-static void optc201_triplebuffer_unlock(struct timing_generator *optc)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
-               OTG_MASTER_UPDATE_LOCK, 0);
-       REG_SET(OTG_VUPDATE_KEEPOUT, 0,
-               OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 0);
-
-}
-
-static bool optc201_validate_timing(
-       struct timing_generator *optc,
-       const struct dc_crtc_timing *timing)
-{
-       uint32_t v_blank;
-       uint32_t h_blank;
-       uint32_t min_v_blank;
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       ASSERT(timing != NULL);
-
-       v_blank = (timing->v_total - timing->v_addressable -
-                                       timing->v_border_top - timing->v_border_bottom);
-
-       h_blank = (timing->h_total - timing->h_addressable -
-               timing->h_border_right -
-               timing->h_border_left);
-
-       if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE &&
-               timing->timing_3d_format != TIMING_3D_FORMAT_HW_FRAME_PACKING &&
-               timing->timing_3d_format != TIMING_3D_FORMAT_TOP_AND_BOTTOM &&
-               timing->timing_3d_format != TIMING_3D_FORMAT_SIDE_BY_SIDE &&
-               timing->timing_3d_format != TIMING_3D_FORMAT_FRAME_ALTERNATE &&
-               timing->timing_3d_format != TIMING_3D_FORMAT_INBAND_FA)
-               return false;
-
-       /* Check maximum number of pixels supported by Timing Generator
-        * (Currently will never fail, in order to fail needs display which
-        * needs more than 8192 horizontal and
-        * more than 8192 vertical total pixels)
-        */
-       if (timing->h_total > optc1->max_h_total ||
-               timing->v_total > optc1->max_v_total)
-               return false;
-
-       if (h_blank < optc1->min_h_blank)
-               return false;
-
-       if (timing->h_sync_width  < optc1->min_h_sync_width ||
-                timing->v_sync_width  < optc1->min_v_sync_width)
-               return false;
-
-       min_v_blank = timing->flags.INTERLACE?optc1->min_v_blank_interlace:optc1->min_v_blank;
-
-       if (v_blank < min_v_blank)
-               return false;
-
-       return true;
-
-}
-
-static void optc201_get_optc_source(struct timing_generator *optc,
-               uint32_t *num_of_src_opp,
-               uint32_t *src_opp_id_0,
-               uint32_t *src_opp_id_1)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       REG_GET(OPTC_DATA_SOURCE_SELECT,
-                       OPTC_SEG0_SRC_SEL, src_opp_id_0);
-
-       *num_of_src_opp = 1;
-}
-
-static struct timing_generator_funcs dcn201_tg_funcs = {
-               .validate_timing = optc201_validate_timing,
-               .program_timing = optc1_program_timing,
-               .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
-               .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
-               .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
-               .program_global_sync = optc1_program_global_sync,
-               .enable_crtc = optc2_enable_crtc,
-               .disable_crtc = optc1_disable_crtc,
-               /* used by enable_timing_synchronization. Not need for FPGA */
-               .is_counter_moving = optc1_is_counter_moving,
-               .get_position = optc1_get_position,
-               .get_frame_count = optc1_get_vblank_counter,
-               .get_scanoutpos = optc1_get_crtc_scanoutpos,
-               .get_otg_active_size = optc1_get_otg_active_size,
-               .set_early_control = optc1_set_early_control,
-               /* used by enable_timing_synchronization. Not need for FPGA */
-               .wait_for_state = optc1_wait_for_state,
-               .set_blank = optc1_set_blank,
-               .is_blanked = optc1_is_blanked,
-               .set_blank_color = optc1_program_blank_color,
-               .did_triggered_reset_occur = optc1_did_triggered_reset_occur,
-               .enable_reset_trigger = optc1_enable_reset_trigger,
-               .enable_crtc_reset = optc1_enable_crtc_reset,
-               .disable_reset_trigger = optc1_disable_reset_trigger,
-               .triplebuffer_lock = optc201_triplebuffer_lock,
-               .triplebuffer_unlock = optc201_triplebuffer_unlock,
-               .lock = optc1_lock,
-               .unlock = optc1_unlock,
-               .enable_optc_clock = optc1_enable_optc_clock,
-               .set_drr = optc1_set_drr,
-               .get_last_used_drr_vtotal = NULL,
-               .set_vtotal_min_max = optc1_set_vtotal_min_max,
-               .set_static_screen_control = optc1_set_static_screen_control,
-               .program_stereo = optc1_program_stereo,
-               .is_stereo_left_eye = optc1_is_stereo_left_eye,
-               .set_blank_data_double_buffer = optc1_set_blank_data_double_buffer,
-               .tg_init = optc1_tg_init,
-               .is_tg_enabled = optc1_is_tg_enabled,
-               .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
-               .clear_optc_underflow = optc1_clear_optc_underflow,
-               .get_crc = optc1_get_crc,
-               .configure_crc = optc2_configure_crc,
-               .set_dsc_config = optc2_set_dsc_config,
-               .set_dwb_source = NULL,
-               .get_optc_source = optc201_get_optc_source,
-               .set_vtg_params = optc1_set_vtg_params,
-               .program_manual_trigger = optc2_program_manual_trigger,
-               .setup_manual_trigger = optc2_setup_manual_trigger,
-               .get_hw_timing = optc1_get_hw_timing,
-};
-
-void dcn201_timing_generator_init(struct optc *optc1)
-{
-       optc1->base.funcs = &dcn201_tg_funcs;
-
-       optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
-       optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
-
-       optc1->min_h_blank = 32;
-       optc1->min_v_blank = 3;
-       optc1->min_v_blank_interlace = 5;
-       optc1->min_h_sync_width = 8;
-       optc1->min_v_sync_width = 1;
-}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_optc.h b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_optc.h
deleted file mode 100644 (file)
index e9545b7..0000000
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DC_OPTC_DCN201_H__
-#define __DC_OPTC_DCN201_H__
-
-#include "dcn20/dcn20_optc.h"
-
-#define TG_COMMON_REG_LIST_DCN201(inst) \
-       TG_COMMON_REG_LIST_DCN(inst),\
-       SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
-       SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
-       SRI(OTG_GSL_WINDOW_X, OTG, inst),\
-       SRI(OTG_GSL_WINDOW_Y, OTG, inst),\
-       SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\
-       SRI(OTG_DSC_START_POSITION, OTG, inst),\
-       SRI(OPTC_DATA_FORMAT_CONTROL, ODM, inst),\
-       SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\
-       SRI(OPTC_WIDTH_CONTROL, ODM, inst),\
-       SR(DWB_SOURCE_SELECT)
-
-#define TG_COMMON_MASK_SH_LIST_DCN201(mask_sh)\
-       TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_X, mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_Y, mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\
-       SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mask_sh),\
-       SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\
-       SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \
-       SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\
-       SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\
-       SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, mask_sh), \
-       SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, mask_sh), \
-       SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, mask_sh), \
-       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_MODE, mask_sh), \
-       SF(OTG0_OTG_GSL_CONTROL, OTG_MASTER_UPDATE_LOCK_GSL_EN, mask_sh), \
-       SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_X, mask_sh), \
-       SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_LINE_NUM, mask_sh),\
-       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG0_SRC_SEL, mask_sh),\
-       SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\
-       SF(ODM0_OPTC_BYTES_PER_PIXEL, OPTC_DSC_BYTES_PER_PIXEL, mask_sh),\
-       SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, mask_sh),\
-       SF(DWB_SOURCE_SELECT, OPTC_DWB0_SOURCE_SELECT, mask_sh),\
-       SF(DWB_SOURCE_SELECT, OPTC_DWB1_SOURCE_SELECT, mask_sh),\
-       SF(DWB_SOURCE_SELECT, OPTC_DWB1_SOURCE_SELECT, mask_sh)
-
-void dcn201_timing_generator_init(struct optc *optc);
-
-bool optc201_is_two_pixels_per_containter(const struct dc_crtc_timing *timing);
-
-#endif
index 9dcf06c0954d59b715a72c80a0c2ee04fcf1e60c..cd95f322235e9e47ce2d55dec3fdd6a1d9f52d37 100644 (file)
@@ -28,7 +28,6 @@ DCN30 := \
        dcn30_hubbub.o \
        dcn30_hubp.o \
        dcn30_dpp.o \
-       dcn30_optc.o \
        dcn30_dccg.o \
        dcn30_mpc.o dcn30_vpg.o \
        dcn30_afmt.o \
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
deleted file mode 100644 (file)
index b97bdb8..0000000
+++ /dev/null
@@ -1,393 +0,0 @@
-/*
- * Copyright 2020 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "reg_helper.h"
-#include "dcn30_optc.h"
-#include "dc.h"
-#include "dcn_calc_math.h"
-#include "dc_dmub_srv.h"
-
-#include "dml/dcn30/dcn30_fpu.h"
-#include "dc_trace.h"
-
-#define REG(reg)\
-       optc1->tg_regs->reg
-
-#define CTX \
-       optc1->base.ctx
-
-#undef FN
-#define FN(reg_name, field_name) \
-       optc1->tg_shift->field_name, optc1->tg_mask->field_name
-
-void optc3_triplebuffer_lock(struct timing_generator *optc)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       REG_UPDATE(OTG_GLOBAL_CONTROL2,
-               OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
-
-       REG_SET(OTG_VUPDATE_KEEPOUT, 0,
-               OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 1);
-
-       REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
-               OTG_MASTER_UPDATE_LOCK, 1);
-
-       REG_WAIT(OTG_MASTER_UPDATE_LOCK,
-                       UPDATE_LOCK_STATUS, 1,
-                       1, 10);
-
-       TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, true);
-}
-
-void optc3_lock_doublebuffer_enable(struct timing_generator *optc)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-       uint32_t v_blank_start = 0;
-       uint32_t v_blank_end = 0;
-       uint32_t h_blank_start = 0;
-       uint32_t h_blank_end = 0;
-
-       REG_GET_2(OTG_V_BLANK_START_END,
-               OTG_V_BLANK_START, &v_blank_start,
-               OTG_V_BLANK_END, &v_blank_end);
-       REG_GET_2(OTG_H_BLANK_START_END,
-               OTG_H_BLANK_START, &h_blank_start,
-               OTG_H_BLANK_END, &h_blank_end);
-
-       REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
-               MASTER_UPDATE_LOCK_DB_START_Y, v_blank_start - 1,
-               MASTER_UPDATE_LOCK_DB_END_Y, v_blank_start);
-       REG_UPDATE_2(OTG_GLOBAL_CONTROL4,
-               DIG_UPDATE_POSITION_X, h_blank_start - 180 - 1,
-               DIG_UPDATE_POSITION_Y, v_blank_start - 1);
-       // there is a DIG_UPDATE_VCOUNT_MODE and it is 0.
-
-       REG_UPDATE_3(OTG_GLOBAL_CONTROL0,
-               MASTER_UPDATE_LOCK_DB_START_X, h_blank_start - 200 - 1,
-               MASTER_UPDATE_LOCK_DB_END_X, h_blank_start - 180,
-               MASTER_UPDATE_LOCK_DB_EN, 1);
-       REG_UPDATE(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 1);
-
-       REG_SET_3(OTG_VUPDATE_KEEPOUT, 0,
-               MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, 0,
-               MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, 100,
-               OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 1);
-
-       TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, true);
-}
-
-void optc3_lock_doublebuffer_disable(struct timing_generator *optc)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       REG_UPDATE_2(OTG_GLOBAL_CONTROL0,
-               MASTER_UPDATE_LOCK_DB_START_X, 0,
-               MASTER_UPDATE_LOCK_DB_END_X, 0);
-       REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
-               MASTER_UPDATE_LOCK_DB_START_Y, 0,
-               MASTER_UPDATE_LOCK_DB_END_Y, 0);
-
-       REG_UPDATE(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 0);
-       REG_UPDATE(OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, 0);
-
-       TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, true);
-}
-
-void optc3_lock(struct timing_generator *optc)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       REG_UPDATE(OTG_GLOBAL_CONTROL2,
-               OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
-       REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
-               OTG_MASTER_UPDATE_LOCK, 1);
-
-       REG_WAIT(OTG_MASTER_UPDATE_LOCK,
-                       UPDATE_LOCK_STATUS, 1,
-                       1, 10);
-
-       TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, true);
-}
-
-void optc3_set_out_mux(struct timing_generator *optc, enum otg_out_mux_dest dest)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       REG_UPDATE(OTG_CONTROL, OTG_OUT_MUX, dest);
-}
-
-void optc3_program_blank_color(struct timing_generator *optc,
-               const struct tg_color *blank_color)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       REG_SET_3(OTG_BLANK_DATA_COLOR, 0,
-               OTG_BLANK_DATA_COLOR_BLUE_CB, blank_color->color_b_cb,
-               OTG_BLANK_DATA_COLOR_GREEN_Y, blank_color->color_g_y,
-               OTG_BLANK_DATA_COLOR_RED_CR, blank_color->color_r_cr);
-
-       REG_SET_3(OTG_BLANK_DATA_COLOR_EXT, 0,
-               OTG_BLANK_DATA_COLOR_BLUE_CB_EXT, blank_color->color_b_cb >> 10,
-               OTG_BLANK_DATA_COLOR_GREEN_Y_EXT, blank_color->color_g_y >> 10,
-               OTG_BLANK_DATA_COLOR_RED_CR_EXT, blank_color->color_r_cr >> 10);
-}
-
-void optc3_set_drr_trigger_window(struct timing_generator *optc,
-               uint32_t window_start, uint32_t window_end)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       REG_SET_2(OTG_DRR_TRIGGER_WINDOW, 0,
-               OTG_DRR_TRIGGER_WINDOW_START_X, window_start,
-               OTG_DRR_TRIGGER_WINDOW_END_X, window_end);
-}
-
-void optc3_set_vtotal_change_limit(struct timing_generator *optc,
-               uint32_t limit)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-
-       REG_SET(OTG_DRR_V_TOTAL_CHANGE, 0,
-               OTG_DRR_V_TOTAL_CHANGE_LIMIT, limit);
-}
-
-
-/* Set DSC-related configuration.
- *   dsc_mode: 0 disables DSC, other values enable DSC in specified format
- *   sc_bytes_per_pixel: Bytes per pixel in u3.28 format
- *   dsc_slice_width: Slice width in pixels
- */
-void optc3_set_dsc_config(struct timing_generator *optc,
-               enum optc_dsc_mode dsc_mode,
-               uint32_t dsc_bytes_per_pixel,
-               uint32_t dsc_slice_width)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       optc2_set_dsc_config(optc, dsc_mode, dsc_bytes_per_pixel, dsc_slice_width);
-       REG_UPDATE(OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, 0);
-}
-
-void optc3_set_odm_bypass(struct timing_generator *optc,
-               const struct dc_crtc_timing *dc_crtc_timing)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-       enum h_timing_div_mode h_div = H_TIMING_NO_DIV;
-
-       REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
-                       OPTC_NUM_OF_INPUT_SEGMENT, 0,
-                       OPTC_SEG0_SRC_SEL, optc->inst,
-                       OPTC_SEG1_SRC_SEL, 0xf,
-                       OPTC_SEG2_SRC_SEL, 0xf,
-                       OPTC_SEG3_SRC_SEL, 0xf
-                       );
-
-       h_div = optc1_is_two_pixels_per_containter(dc_crtc_timing);
-       REG_UPDATE(OTG_H_TIMING_CNTL,
-                       OTG_H_TIMING_DIV_MODE, h_div);
-
-       REG_SET(OPTC_MEMORY_CONFIG, 0,
-                       OPTC_MEM_SEL, 0);
-       optc1->opp_count = 1;
-}
-
-void optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
-               struct dc_crtc_timing *timing)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-       int mpcc_hactive = (timing->h_addressable + timing->h_border_left + timing->h_border_right)
-                       / opp_cnt;
-       uint32_t memory_mask = 0;
-
-       /* TODO: In pseudocode but does not affect maximus, delete comment if we dont need on asic
-        * REG_SET(OTG_GLOBAL_CONTROL2, 0, GLOBAL_UPDATE_LOCK_EN, 1);
-        * Program OTG register MASTER_UPDATE_LOCK_DB_X/Y to the position before DP frame start
-        * REG_SET_2(OTG_GLOBAL_CONTROL1, 0,
-        *              MASTER_UPDATE_LOCK_DB_X, 160,
-        *              MASTER_UPDATE_LOCK_DB_Y, 240);
-        */
-
-       ASSERT(opp_cnt == 2 || opp_cnt == 4);
-
-       /* 2 pieces of memory required for up to 5120 displays, 4 for up to 8192,
-        * however, for ODM combine we can simplify by always using 4.
-        */
-       if (opp_cnt == 2) {
-               /* To make sure there's no memory overlap, each instance "reserves" 2
-                * memories and they are uniquely combined here.
-                */
-               memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);
-       } else if (opp_cnt == 4) {
-               /* To make sure there's no memory overlap, each instance "reserves" 1
-                * memory and they are uniquely combined here.
-                */
-               memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2) | 0x1 << (opp_id[2] * 2) | 0x1 << (opp_id[3] * 2);
-       }
-
-       if (REG(OPTC_MEMORY_CONFIG))
-               REG_SET(OPTC_MEMORY_CONFIG, 0,
-                       OPTC_MEM_SEL, memory_mask);
-
-       if (opp_cnt == 2) {
-               REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
-                               OPTC_NUM_OF_INPUT_SEGMENT, 1,
-                               OPTC_SEG0_SRC_SEL, opp_id[0],
-                               OPTC_SEG1_SRC_SEL, opp_id[1]);
-       } else if (opp_cnt == 4) {
-               REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
-                               OPTC_NUM_OF_INPUT_SEGMENT, 3,
-                               OPTC_SEG0_SRC_SEL, opp_id[0],
-                               OPTC_SEG1_SRC_SEL, opp_id[1],
-                               OPTC_SEG2_SRC_SEL, opp_id[2],
-                               OPTC_SEG3_SRC_SEL, opp_id[3]);
-       }
-
-       REG_UPDATE(OPTC_WIDTH_CONTROL,
-                       OPTC_SEGMENT_WIDTH, mpcc_hactive);
-
-       REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1);
-       optc1->opp_count = opp_cnt;
-}
-
-/**
- * optc3_set_timing_double_buffer() - DRR double buffering control
- *
- * Sets double buffer point for V_TOTAL, H_TOTAL, VTOTAL_MIN,
- * VTOTAL_MAX, VTOTAL_MIN_SEL and VTOTAL_MAX_SEL registers.
- *
- * @optc: timing_generator instance.
- * @enable: Enable DRR double buffering control if true, disable otherwise.
- *
- * Options: any time,  start of frame, dp start of frame (range timing)
- */
-static void optc3_set_timing_double_buffer(struct timing_generator *optc, bool enable)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-       uint32_t mode = enable ? 2 : 0;
-
-       REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,
-                  OTG_DRR_TIMING_DBUF_UPDATE_MODE, mode);
-}
-
-void optc3_wait_drr_doublebuffer_pending_clear(struct timing_generator *optc)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       REG_WAIT(OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_PENDING, 0, 2, 100000); /* 1 vupdate at 5hz */
-
-}
-
-void optc3_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max)
-{
-       struct dc *dc = optc->ctx->dc;
-
-       if (dc->caps.dmub_caps.mclk_sw && !dc->debug.disable_fams)
-               dc_dmub_srv_drr_update_cmd(dc, optc->inst, vtotal_min, vtotal_max);
-       else
-               optc1_set_vtotal_min_max(optc, vtotal_min, vtotal_max);
-}
-
-void optc3_tg_init(struct timing_generator *optc)
-{
-       optc3_set_timing_double_buffer(optc, true);
-       optc1_clear_optc_underflow(optc);
-}
-
-static struct timing_generator_funcs dcn30_tg_funcs = {
-               .validate_timing = optc1_validate_timing,
-               .program_timing = optc1_program_timing,
-               .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
-               .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
-               .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
-               .program_global_sync = optc1_program_global_sync,
-               .enable_crtc = optc2_enable_crtc,
-               .disable_crtc = optc1_disable_crtc,
-               /* used by enable_timing_synchronization. Not need for FPGA */
-               .is_counter_moving = optc1_is_counter_moving,
-               .get_position = optc1_get_position,
-               .get_frame_count = optc1_get_vblank_counter,
-               .get_scanoutpos = optc1_get_crtc_scanoutpos,
-               .get_otg_active_size = optc1_get_otg_active_size,
-               .set_early_control = optc1_set_early_control,
-               /* used by enable_timing_synchronization. Not need for FPGA */
-               .wait_for_state = optc1_wait_for_state,
-               .set_blank_color = optc3_program_blank_color,
-               .did_triggered_reset_occur = optc1_did_triggered_reset_occur,
-               .triplebuffer_lock = optc3_triplebuffer_lock,
-               .triplebuffer_unlock = optc2_triplebuffer_unlock,
-               .enable_reset_trigger = optc1_enable_reset_trigger,
-               .enable_crtc_reset = optc1_enable_crtc_reset,
-               .disable_reset_trigger = optc1_disable_reset_trigger,
-               .lock = optc3_lock,
-               .unlock = optc1_unlock,
-               .lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,
-               .lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
-               .enable_optc_clock = optc1_enable_optc_clock,
-               .set_drr = optc1_set_drr,
-               .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
-               .set_vtotal_min_max = optc3_set_vtotal_min_max,
-               .set_static_screen_control = optc1_set_static_screen_control,
-               .program_stereo = optc1_program_stereo,
-               .is_stereo_left_eye = optc1_is_stereo_left_eye,
-               .tg_init = optc3_tg_init,
-               .is_tg_enabled = optc1_is_tg_enabled,
-               .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
-               .clear_optc_underflow = optc1_clear_optc_underflow,
-               .setup_global_swap_lock = NULL,
-               .get_crc = optc1_get_crc,
-               .configure_crc = optc2_configure_crc,
-               .set_dsc_config = optc3_set_dsc_config,
-               .get_dsc_status = optc2_get_dsc_status,
-               .set_dwb_source = NULL,
-               .set_odm_bypass = optc3_set_odm_bypass,
-               .set_odm_combine = optc3_set_odm_combine,
-               .get_optc_source = optc2_get_optc_source,
-               .set_out_mux = optc3_set_out_mux,
-               .set_drr_trigger_window = optc3_set_drr_trigger_window,
-               .set_vtotal_change_limit = optc3_set_vtotal_change_limit,
-               .set_gsl = optc2_set_gsl,
-               .set_gsl_source_select = optc2_set_gsl_source_select,
-               .set_vtg_params = optc1_set_vtg_params,
-               .program_manual_trigger = optc2_program_manual_trigger,
-               .setup_manual_trigger = optc2_setup_manual_trigger,
-               .get_hw_timing = optc1_get_hw_timing,
-               .wait_drr_doublebuffer_pending_clear = optc3_wait_drr_doublebuffer_pending_clear,
-};
-
-void dcn30_timing_generator_init(struct optc *optc1)
-{
-       optc1->base.funcs = &dcn30_tg_funcs;
-
-       optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
-       optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
-
-       optc1->min_h_blank = 32;
-       optc1->min_v_blank = 3;
-       optc1->min_v_blank_interlace = 5;
-       optc1->min_h_sync_width = 4;
-       optc1->min_v_sync_width = 1;
-}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h
deleted file mode 100644 (file)
index d3a056c..0000000
+++ /dev/null
@@ -1,359 +0,0 @@
-/*
- * Copyright 2020 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DC_OPTC_DCN30_H__
-#define __DC_OPTC_DCN30_H__
-
-#include "dcn20/dcn20_optc.h"
-
-#define V_TOTAL_REGS_DCN30_SRI(inst)
-
-#define OPTC_COMMON_REG_LIST_DCN3_BASE(inst) \
-       SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
-       SRI(OTG_VUPDATE_PARAM, OTG, inst),\
-       SRI(OTG_VREADY_PARAM, OTG, inst),\
-       SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
-       SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
-       SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
-       SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
-       SRI(OTG_GLOBAL_CONTROL4, OTG, inst),\
-       SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
-       SRI(OTG_H_TOTAL, OTG, inst),\
-       SRI(OTG_H_BLANK_START_END, OTG, inst),\
-       SRI(OTG_H_SYNC_A, OTG, inst),\
-       SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\
-       SRI(OTG_H_TIMING_CNTL, OTG, inst),\
-       SRI(OTG_V_TOTAL, OTG, inst),\
-       SRI(OTG_V_BLANK_START_END, OTG, inst),\
-       SRI(OTG_V_SYNC_A, OTG, inst),\
-       SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\
-       SRI(OTG_CONTROL, OTG, inst),\
-       SRI(OTG_STEREO_CONTROL, OTG, inst),\
-       SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\
-       SRI(OTG_STEREO_STATUS, OTG, inst),\
-       SRI(OTG_V_TOTAL_MAX, OTG, inst),\
-       SRI(OTG_V_TOTAL_MIN, OTG, inst),\
-       SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\
-       V_TOTAL_REGS_DCN30_SRI(inst)\
-       SRI(OTG_TRIGA_CNTL, OTG, inst),\
-       SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\
-       SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\
-       SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\
-       SRI(OTG_STATUS, OTG, inst),\
-       SRI(OTG_STATUS_POSITION, OTG, inst),\
-       SRI(OTG_NOM_VERT_POSITION, OTG, inst),\
-       SRI(OTG_BLANK_DATA_COLOR, OTG, inst),\
-       SRI(OTG_BLANK_DATA_COLOR_EXT, OTG, inst),\
-       SRI(OTG_M_CONST_DTO0, OTG, inst),\
-       SRI(OTG_M_CONST_DTO1, OTG, inst),\
-       SRI(OTG_CLOCK_CONTROL, OTG, inst),\
-       SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\
-       SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\
-       SRI(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\
-       SRI(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\
-       SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\
-       SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\
-       SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\
-       SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\
-       SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\
-       SRI(CONTROL, VTG, inst),\
-       SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\
-       SRI(OTG_GSL_CONTROL, OTG, inst),\
-       SRI(OTG_CRC_CNTL, OTG, inst),\
-       SRI(OTG_CRC_CNTL2, OTG, inst),\
-       SRI(OTG_CRC0_DATA_RG, OTG, inst),\
-       SRI(OTG_CRC0_DATA_B, OTG, inst),\
-       SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\
-       SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\
-       SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\
-       SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\
-       SR(GSL_SOURCE_SELECT),\
-       SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst),\
-       SRI(OTG_DRR_CONTROL, OTG, inst)
-
-
-#define OPTC_COMMON_REG_LIST_DCN3_0(inst) \
-       OPTC_COMMON_REG_LIST_DCN3_BASE(inst),\
-       SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
-       SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
-       SRI(OTG_GSL_WINDOW_X, OTG, inst),\
-       SRI(OTG_GSL_WINDOW_Y, OTG, inst),\
-       SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\
-       SRI(OTG_DSC_START_POSITION, OTG, inst),\
-       SRI(OTG_CRC_CNTL2, OTG, inst),\
-       SRI(OTG_DRR_TRIGGER_WINDOW, OTG, inst),\
-       SRI(OTG_DRR_V_TOTAL_CHANGE, OTG, inst),\
-       SRI(OPTC_DATA_FORMAT_CONTROL, ODM, inst),\
-       SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\
-       SRI(OPTC_WIDTH_CONTROL, ODM, inst),\
-       SRI(OPTC_MEMORY_CONFIG, ODM, inst),\
-       SR(DWB_SOURCE_SELECT)
-
-#define DCN30_VTOTAL_REGS_SF(mask_sh)
-
-#define OPTC_COMMON_MASK_SH_LIST_DCN3_BASE(mask_sh)\
-       SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
-       SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
-       SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
-       SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
-       SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\
-       SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_START_X, mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_END_X, mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_START_Y, mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_END_Y, mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL2, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_X, mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_Y, mask_sh),\
-       SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\
-       SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
-       SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_START, mask_sh),\
-       SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_END, mask_sh),\
-       SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_START, mask_sh),\
-       SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_END, mask_sh),\
-       SF(OTG0_OTG_H_SYNC_A_CNTL, OTG_H_SYNC_A_POL, mask_sh),\
-       SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
-       SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_START, mask_sh),\
-       SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_END, mask_sh),\
-       SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_START, mask_sh),\
-       SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_END, mask_sh),\
-       SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_A_POL, mask_sh),\
-       SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, mask_sh),\
-       SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
-       SF(OTG0_OTG_CONTROL, OTG_START_POINT_CNTL, mask_sh),\
-       SF(OTG0_OTG_CONTROL, OTG_DISABLE_POINT_CNTL, mask_sh),\
-       SF(OTG0_OTG_CONTROL, OTG_FIELD_NUMBER_CNTL, mask_sh),\
-       SF(OTG0_OTG_CONTROL, OTG_OUT_MUX, mask_sh),\
-       SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EN, mask_sh),\
-       SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_LINE_NUM, mask_sh),\
-       SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_POLARITY, mask_sh),\
-       SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EYE_FLAG_POLARITY, mask_sh),\
-       SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\
-       SF(OTG0_OTG_STEREO_STATUS, OTG_STEREO_CURRENT_EYE, mask_sh),\
-       SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_EN, mask_sh),\
-       SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\
-       SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\
-       SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\
-       SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\
-       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\
-       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\
-       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\
-       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK_EN, mask_sh),\
-       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\
-       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MIN_EN, mask_sh),\
-       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\
-       DCN30_VTOTAL_REGS_SF(mask_sh)\
-       SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\
-       SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\
-       SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\
-       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_SELECT, mask_sh),\
-       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_PIPE_SELECT, mask_sh),\
-       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_RISING_EDGE_DETECT_CNTL, mask_sh),\
-       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, mask_sh),\
-       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_POLARITY_SELECT, mask_sh),\
-       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FREQUENCY_SELECT, mask_sh),\
-       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_DELAY, mask_sh),\
-       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_CLEAR, mask_sh),\
-       SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_EVENT_MASK, mask_sh),\
-       SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_FRAME_COUNT, mask_sh),\
-       SF(OTG0_OTG_STATUS_FRAME_COUNT, OTG_FRAME_COUNT, mask_sh),\
-       SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
-       SF(OTG0_OTG_STATUS, OTG_V_ACTIVE_DISP, mask_sh),\
-       SF(OTG0_OTG_STATUS_POSITION, OTG_HORZ_COUNT, mask_sh),\
-       SF(OTG0_OTG_STATUS_POSITION, OTG_VERT_COUNT, mask_sh),\
-       SF(OTG0_OTG_NOM_VERT_POSITION, OTG_VERT_COUNT_NOM, mask_sh),\
-       SF(OTG0_OTG_BLANK_DATA_COLOR, OTG_BLANK_DATA_COLOR_BLUE_CB, mask_sh),\
-       SF(OTG0_OTG_BLANK_DATA_COLOR, OTG_BLANK_DATA_COLOR_GREEN_Y, mask_sh),\
-       SF(OTG0_OTG_BLANK_DATA_COLOR, OTG_BLANK_DATA_COLOR_RED_CR, mask_sh),\
-       SF(OTG0_OTG_BLANK_DATA_COLOR_EXT, OTG_BLANK_DATA_COLOR_BLUE_CB_EXT, mask_sh),\
-       SF(OTG0_OTG_BLANK_DATA_COLOR_EXT, OTG_BLANK_DATA_COLOR_GREEN_Y_EXT, mask_sh),\
-       SF(OTG0_OTG_BLANK_DATA_COLOR_EXT, OTG_BLANK_DATA_COLOR_RED_CR_EXT, mask_sh),\
-       SF(OTG0_OTG_M_CONST_DTO0, OTG_M_CONST_DTO_PHASE, mask_sh),\
-       SF(OTG0_OTG_M_CONST_DTO1, OTG_M_CONST_DTO_MODULO, mask_sh),\
-       SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\
-       SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\
-       SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\
-       SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\
-       SF(OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE, mask_sh),\
-       SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_START, mask_sh),\
-       SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_END, mask_sh),\
-       SF(OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_INT_ENABLE, mask_sh),\
-       SF(OTG0_OTG_VERTICAL_INTERRUPT1_POSITION, OTG_VERTICAL_INTERRUPT1_LINE_START, mask_sh),\
-       SF(OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE, mask_sh),\
-       SF(OTG0_OTG_VERTICAL_INTERRUPT2_POSITION, OTG_VERTICAL_INTERRUPT2_LINE_START, mask_sh),\
-       SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\
-       SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\
-       SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\
-       SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\
-       SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\
-       SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
-       SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
-       SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
-       SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, mask_sh),\
-       SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, mask_sh),\
-       SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_AUTO_FORCE_VSYNC_MODE, mask_sh),\
-       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL0_EN, mask_sh),\
-       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL1_EN, mask_sh),\
-       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL2_EN, mask_sh),\
-       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_EN, mask_sh),\
-       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_FORCE_DELAY, mask_sh),\
-       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\
-       SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\
-       SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\
-       SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
-       SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DSC_MODE, mask_sh),\
-       SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_COMBINE_MODE, mask_sh),\
-       SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_SPLIT_MODE, mask_sh),\
-       SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_FORMAT, mask_sh),\
-       SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\
-       SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\
-       SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\
-       SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_START, mask_sh),\
-       SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_END, mask_sh),\
-       SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_START, mask_sh),\
-       SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_END, mask_sh),\
-       SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_START, mask_sh),\
-       SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\
-       SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\
-       SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\
-       SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\
-       SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\
-       SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\
-       SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh),\
-       SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh)
-
-#define OPTC_COMMON_MASK_SH_LIST_DCN3_0(mask_sh)\
-       OPTC_COMMON_MASK_SH_LIST_DCN3_BASE(mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\
-       SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\
-       SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \
-       SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\
-       SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\
-       SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, mask_sh), \
-       SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, mask_sh), \
-       SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, mask_sh), \
-       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_MODE, mask_sh), \
-       SF(OTG0_OTG_GSL_CONTROL, OTG_MASTER_UPDATE_LOCK_GSL_EN, mask_sh), \
-       SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_X, mask_sh), \
-       SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_LINE_NUM, mask_sh),\
-       SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DSC_MODE, mask_sh),\
-       SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_COMBINE_MODE, mask_sh),\
-       SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_SPLIT_MODE, mask_sh),\
-       SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_FORMAT, mask_sh),\
-       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG0_SRC_SEL, mask_sh),\
-       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG1_SRC_SEL, mask_sh),\
-       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, mask_sh),\
-       SF(ODM0_OPTC_MEMORY_CONFIG, OPTC_MEM_SEL, mask_sh),\
-       SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, mask_sh),\
-       SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\
-       SF(ODM0_OPTC_BYTES_PER_PIXEL, OPTC_DSC_BYTES_PER_PIXEL, mask_sh),\
-       SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, mask_sh),\
-       SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_SEGMENT_WIDTH, mask_sh),\
-       SF(DWB_SOURCE_SELECT, OPTC_DWB0_SOURCE_SELECT, mask_sh),\
-       SF(DWB_SOURCE_SELECT, OPTC_DWB1_SOURCE_SELECT, mask_sh),\
-       SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_START_X, mask_sh),\
-       SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_END_X, mask_sh),\
-       SF(OTG0_OTG_DRR_V_TOTAL_CHANGE, OTG_DRR_V_TOTAL_CHANGE_LIMIT, mask_sh),\
-       SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_BY2, mask_sh),\
-       SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_PENDING, mask_sh),\
-       SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh),\
-       SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_BLANK_DATA_DOUBLE_BUFFER_EN, mask_sh)
-
-#define OPTC_COMMON_MASK_SH_LIST_DCN30(mask_sh)\
-       OPTC_COMMON_MASK_SH_LIST_DCN3_BASE(mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\
-       SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\
-       SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \
-       SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\
-       SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\
-       SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, mask_sh), \
-       SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, mask_sh), \
-       SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, mask_sh), \
-       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_MODE, mask_sh), \
-       SF(OTG0_OTG_GSL_CONTROL, OTG_MASTER_UPDATE_LOCK_GSL_EN, mask_sh), \
-       SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_X, mask_sh), \
-       SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_LINE_NUM, mask_sh),\
-       SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DSC_MODE, mask_sh),\
-       SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_COMBINE_MODE, mask_sh),\
-       SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_SPLIT_MODE, mask_sh),\
-       SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_FORMAT, mask_sh),\
-       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG0_SRC_SEL, mask_sh),\
-       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG1_SRC_SEL, mask_sh),\
-       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG2_SRC_SEL, mask_sh),\
-       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG3_SRC_SEL, mask_sh),\
-       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, mask_sh),\
-       SF(ODM0_OPTC_MEMORY_CONFIG, OPTC_MEM_SEL, mask_sh),\
-       SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, mask_sh),\
-       SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\
-       SF(ODM0_OPTC_BYTES_PER_PIXEL, OPTC_DSC_BYTES_PER_PIXEL, mask_sh),\
-       SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, mask_sh),\
-       SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_SEGMENT_WIDTH, mask_sh),\
-       SF(DWB_SOURCE_SELECT, OPTC_DWB0_SOURCE_SELECT, mask_sh),\
-       SF(DWB_SOURCE_SELECT, OPTC_DWB1_SOURCE_SELECT, mask_sh),\
-       SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_START_X, mask_sh),\
-       SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_END_X, mask_sh),\
-       SF(OTG0_OTG_DRR_V_TOTAL_CHANGE, OTG_DRR_V_TOTAL_CHANGE_LIMIT, mask_sh),\
-       SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\
-       SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_PENDING, mask_sh),\
-       SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh)
-
-void dcn30_timing_generator_init(struct optc *optc1);
-
-void optc3_set_out_mux(struct timing_generator *optc, enum otg_out_mux_dest dest);
-
-void optc3_lock(struct timing_generator *optc);
-
-void optc3_lock_doublebuffer_enable(struct timing_generator *optc);
-
-void optc3_lock_doublebuffer_disable(struct timing_generator *optc);
-
-void optc3_set_drr_trigger_window(struct timing_generator *optc,
-               uint32_t window_start, uint32_t window_end);
-
-void optc3_triplebuffer_lock(struct timing_generator *optc);
-
-void optc3_program_blank_color(struct timing_generator *optc,
-               const struct tg_color *blank_color);
-
-void optc3_set_vtotal_change_limit(struct timing_generator *optc,
-               uint32_t limit);
-
-void optc3_set_dsc_config(struct timing_generator *optc,
-               enum optc_dsc_mode dsc_mode,
-               uint32_t dsc_bytes_per_pixel,
-               uint32_t dsc_slice_width);
-
-void optc3_set_timing_db_mode(struct timing_generator *optc, bool enable);
-
-void optc3_set_odm_bypass(struct timing_generator *optc,
-               const struct dc_crtc_timing *dc_crtc_timing);
-void optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
-               struct dc_crtc_timing *timing);
-void optc3_wait_drr_doublebuffer_pending_clear(struct timing_generator *optc);
-void optc3_tg_init(struct timing_generator *optc);
-void optc3_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max);
-#endif /* __DC_OPTC_DCN30_H__ */
index cbf59d7e78c4fd934e21413f4028e032b11a09a1..090011300dcdb02a3395baae22b1760021469269 100644 (file)
@@ -11,8 +11,7 @@
 # Makefile for dcn30.
 
 DCN301 = dcn301_init.o dcn301_dccg.o \
-               dcn301_dio_link_encoder.o dcn301_panel_cntl.o dcn301_hubbub.o \
-               dcn301_optc.o
+               dcn301_dio_link_encoder.o dcn301_panel_cntl.o dcn301_hubbub.o
 
 AMD_DAL_DCN301 = $(addprefix $(AMDDALPATH)/dc/dcn301/,$(DCN301))
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_optc.c b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_optc.c
deleted file mode 100644 (file)
index b3cfcb8..0000000
+++ /dev/null
@@ -1,185 +0,0 @@
-/*
- * Copyright 2020 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "reg_helper.h"
-#include "dcn301_optc.h"
-#include "dc.h"
-#include "dcn_calc_math.h"
-#include "dc_dmub_srv.h"
-
-#include "dml/dcn30/dcn30_fpu.h"
-#include "dc_trace.h"
-
-#define REG(reg)\
-       optc1->tg_regs->reg
-
-#define CTX \
-       optc1->base.ctx
-
-#undef FN
-#define FN(reg_name, field_name) \
-       optc1->tg_shift->field_name, optc1->tg_mask->field_name
-
-
-/**
- * optc301_set_drr() - Program dynamic refresh rate registers m_OTGx_OTG_V_TOTAL_*.
- *
- * @optc: timing_generator instance.
- * @params: parameters used for Dynamic Refresh Rate.
- */
-void optc301_set_drr(
-       struct timing_generator *optc,
-       const struct drr_params *params)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       if (params != NULL &&
-               params->vertical_total_max > 0 &&
-               params->vertical_total_min > 0) {
-
-               if (params->vertical_total_mid != 0) {
-
-                       REG_SET(OTG_V_TOTAL_MID, 0,
-                               OTG_V_TOTAL_MID, params->vertical_total_mid - 1);
-
-                       REG_UPDATE_2(OTG_V_TOTAL_CONTROL,
-                                       OTG_VTOTAL_MID_REPLACING_MAX_EN, 1,
-                                       OTG_VTOTAL_MID_FRAME_NUM,
-                                       (uint8_t)params->vertical_total_mid_frame_num);
-
-               }
-
-               optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1);
-
-               REG_UPDATE_5(OTG_V_TOTAL_CONTROL,
-                               OTG_V_TOTAL_MIN_SEL, 1,
-                               OTG_V_TOTAL_MAX_SEL, 1,
-                               OTG_FORCE_LOCK_ON_EVENT, 0,
-                               OTG_SET_V_TOTAL_MIN_MASK_EN, 0,
-                               OTG_SET_V_TOTAL_MIN_MASK, 0);
-               // Setup manual flow control for EOF via TRIG_A
-               optc->funcs->setup_manual_trigger(optc);
-
-       } else {
-               REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
-                               OTG_SET_V_TOTAL_MIN_MASK, 0,
-                               OTG_V_TOTAL_MIN_SEL, 0,
-                               OTG_V_TOTAL_MAX_SEL, 0,
-                               OTG_FORCE_LOCK_ON_EVENT, 0);
-
-               optc->funcs->set_vtotal_min_max(optc, 0, 0);
-       }
-}
-
-
-void optc301_setup_manual_trigger(struct timing_generator *optc)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       REG_SET_8(OTG_TRIGA_CNTL, 0,
-                       OTG_TRIGA_SOURCE_SELECT, 21,
-                       OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst,
-                       OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1,
-                       OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 0,
-                       OTG_TRIGA_POLARITY_SELECT, 0,
-                       OTG_TRIGA_FREQUENCY_SELECT, 0,
-                       OTG_TRIGA_DELAY, 0,
-                       OTG_TRIGA_CLEAR, 1);
-}
-
-static struct timing_generator_funcs dcn30_tg_funcs = {
-               .validate_timing = optc1_validate_timing,
-               .program_timing = optc1_program_timing,
-               .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
-               .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
-               .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
-               .program_global_sync = optc1_program_global_sync,
-               .enable_crtc = optc2_enable_crtc,
-               .disable_crtc = optc1_disable_crtc,
-               /* used by enable_timing_synchronization. Not need for FPGA */
-               .is_counter_moving = optc1_is_counter_moving,
-               .get_position = optc1_get_position,
-               .get_frame_count = optc1_get_vblank_counter,
-               .get_scanoutpos = optc1_get_crtc_scanoutpos,
-               .get_otg_active_size = optc1_get_otg_active_size,
-               .set_early_control = optc1_set_early_control,
-               /* used by enable_timing_synchronization. Not need for FPGA */
-               .wait_for_state = optc1_wait_for_state,
-               .set_blank_color = optc3_program_blank_color,
-               .did_triggered_reset_occur = optc1_did_triggered_reset_occur,
-               .triplebuffer_lock = optc3_triplebuffer_lock,
-               .triplebuffer_unlock = optc2_triplebuffer_unlock,
-               .enable_reset_trigger = optc1_enable_reset_trigger,
-               .enable_crtc_reset = optc1_enable_crtc_reset,
-               .disable_reset_trigger = optc1_disable_reset_trigger,
-               .lock = optc3_lock,
-               .unlock = optc1_unlock,
-               .lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,
-               .lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
-               .enable_optc_clock = optc1_enable_optc_clock,
-               .set_drr = optc301_set_drr,
-               .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
-               .set_vtotal_min_max = optc3_set_vtotal_min_max,
-               .set_static_screen_control = optc1_set_static_screen_control,
-               .program_stereo = optc1_program_stereo,
-               .is_stereo_left_eye = optc1_is_stereo_left_eye,
-               .tg_init = optc3_tg_init,
-               .is_tg_enabled = optc1_is_tg_enabled,
-               .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
-               .clear_optc_underflow = optc1_clear_optc_underflow,
-               .setup_global_swap_lock = NULL,
-               .get_crc = optc1_get_crc,
-               .configure_crc = optc2_configure_crc,
-               .set_dsc_config = optc3_set_dsc_config,
-               .get_dsc_status = optc2_get_dsc_status,
-               .set_dwb_source = NULL,
-               .set_odm_bypass = optc3_set_odm_bypass,
-               .set_odm_combine = optc3_set_odm_combine,
-               .get_optc_source = optc2_get_optc_source,
-               .set_out_mux = optc3_set_out_mux,
-               .set_drr_trigger_window = optc3_set_drr_trigger_window,
-               .set_vtotal_change_limit = optc3_set_vtotal_change_limit,
-               .set_gsl = optc2_set_gsl,
-               .set_gsl_source_select = optc2_set_gsl_source_select,
-               .set_vtg_params = optc1_set_vtg_params,
-               .program_manual_trigger = optc2_program_manual_trigger,
-               .setup_manual_trigger = optc301_setup_manual_trigger,
-               .get_hw_timing = optc1_get_hw_timing,
-               .wait_drr_doublebuffer_pending_clear = optc3_wait_drr_doublebuffer_pending_clear,
-};
-
-void dcn301_timing_generator_init(struct optc *optc1)
-{
-       optc1->base.funcs = &dcn30_tg_funcs;
-
-       optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
-       optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
-
-       optc1->min_h_blank = 32;
-       optc1->min_v_blank = 3;
-       optc1->min_v_blank_interlace = 5;
-       optc1->min_h_sync_width = 4;
-       optc1->min_v_sync_width = 1;
-}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_optc.h b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_optc.h
deleted file mode 100644 (file)
index b495856..0000000
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Copyright 2020 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DC_OPTC_DCN301_H__
-#define __DC_OPTC_DCN301_H__
-
-#include "dcn20/dcn20_optc.h"
-#include "dcn30/dcn30_optc.h"
-
-void dcn301_timing_generator_init(struct optc *optc1);
-void optc301_setup_manual_trigger(struct timing_generator *optc);
-void optc301_set_drr(struct timing_generator *optc, const struct drr_params *params);
-
-#endif /* __DC_OPTC_DCN301_H__ */
index 212287008c0a65e20ea4607e841210ee48ad3a18..11a2662e58ef344a1764583ffe32d73dd902444e 100644 (file)
@@ -11,7 +11,7 @@
 # Makefile for dcn31.
 
 DCN31 = dcn31_hubbub.o dcn31_init.o dcn31_hubp.o \
-       dcn31_dccg.o dcn31_optc.o dcn31_dio_link_encoder.o dcn31_panel_cntl.o \
+       dcn31_dccg.o dcn31_dio_link_encoder.o dcn31_panel_cntl.o \
        dcn31_apg.o dcn31_hpo_dp_stream_encoder.o dcn31_hpo_dp_link_encoder.o \
        dcn31_afmt.o dcn31_vpg.o
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c
deleted file mode 100644 (file)
index 63a677c..0000000
+++ /dev/null
@@ -1,310 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dcn31_optc.h"
-
-#include "dcn30/dcn30_optc.h"
-#include "reg_helper.h"
-#include "dc.h"
-#include "dcn_calc_math.h"
-
-#define REG(reg)\
-       optc1->tg_regs->reg
-
-#define CTX \
-       optc1->base.ctx
-
-#undef FN
-#define FN(reg_name, field_name) \
-       optc1->tg_shift->field_name, optc1->tg_mask->field_name
-
-static void optc31_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
-               struct dc_crtc_timing *timing)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-       int mpcc_hactive = (timing->h_addressable + timing->h_border_left + timing->h_border_right)
-                       / opp_cnt;
-       uint32_t memory_mask = 0;
-       int mem_count_per_opp = (mpcc_hactive + 2559) / 2560;
-
-       /* Assume less than 6 pipes */
-       if (opp_cnt == 4) {
-               if (mem_count_per_opp == 1)
-                       memory_mask = 0xf;
-               else {
-                       ASSERT(mem_count_per_opp == 2);
-                       memory_mask = 0xff;
-               }
-       } else if (mem_count_per_opp == 1)
-               memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2);
-       else if (mem_count_per_opp == 2)
-               memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);
-       else if (mem_count_per_opp == 3)
-               memory_mask = 0x77;
-       else if (mem_count_per_opp == 4)
-               memory_mask = 0xff;
-
-       if (REG(OPTC_MEMORY_CONFIG))
-               REG_SET(OPTC_MEMORY_CONFIG, 0,
-                       OPTC_MEM_SEL, memory_mask);
-
-       if (opp_cnt == 2) {
-               REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
-                               OPTC_NUM_OF_INPUT_SEGMENT, 1,
-                               OPTC_SEG0_SRC_SEL, opp_id[0],
-                               OPTC_SEG1_SRC_SEL, opp_id[1]);
-       } else if (opp_cnt == 4) {
-               REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
-                               OPTC_NUM_OF_INPUT_SEGMENT, 3,
-                               OPTC_SEG0_SRC_SEL, opp_id[0],
-                               OPTC_SEG1_SRC_SEL, opp_id[1],
-                               OPTC_SEG2_SRC_SEL, opp_id[2],
-                               OPTC_SEG3_SRC_SEL, opp_id[3]);
-       }
-
-       REG_UPDATE(OPTC_WIDTH_CONTROL,
-                       OPTC_SEGMENT_WIDTH, mpcc_hactive);
-
-       REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1);
-       optc1->opp_count = opp_cnt;
-}
-
-/*
- * Enable CRTC - call ASIC Control Object to enable Timing generator.
- */
-static bool optc31_enable_crtc(struct timing_generator *optc)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       /* opp instance for OTG, 1 to 1 mapping and odm will adjust */
-       REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
-                       OPTC_SEG0_SRC_SEL, optc->inst);
-
-       /* VTG enable first is for HW workaround */
-       REG_UPDATE(CONTROL,
-                       VTG0_ENABLE, 1);
-
-       REG_SEQ_START();
-
-       /* Enable CRTC */
-       REG_UPDATE_2(OTG_CONTROL,
-                       OTG_DISABLE_POINT_CNTL, 2,
-                       OTG_MASTER_EN, 1);
-
-       REG_SEQ_SUBMIT();
-       REG_SEQ_WAIT_DONE();
-
-       return true;
-}
-
-/* disable_crtc - call ASIC Control Object to disable Timing generator. */
-static bool optc31_disable_crtc(struct timing_generator *optc)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-       /* disable otg request until end of the first line
-        * in the vertical blank region
-        */
-       REG_UPDATE(OTG_CONTROL,
-                       OTG_MASTER_EN, 0);
-
-       REG_UPDATE(CONTROL,
-                       VTG0_ENABLE, 0);
-
-       /* CRTC disabled, so disable  clock. */
-       REG_WAIT(OTG_CLOCK_CONTROL,
-                       OTG_BUSY, 0,
-                       1, 100000);
-       optc1_clear_optc_underflow(optc);
-
-       return true;
-}
-
-bool optc31_immediate_disable_crtc(struct timing_generator *optc)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       REG_UPDATE_2(OTG_CONTROL,
-                       OTG_DISABLE_POINT_CNTL, 0,
-                       OTG_MASTER_EN, 0);
-
-       REG_UPDATE(CONTROL,
-                       VTG0_ENABLE, 0);
-
-       /* CRTC disabled, so disable  clock. */
-       REG_WAIT(OTG_CLOCK_CONTROL,
-                       OTG_BUSY, 0,
-                       1, 100000);
-
-       /* clear the false state */
-       optc1_clear_optc_underflow(optc);
-
-       return true;
-}
-
-void optc31_set_drr(
-       struct timing_generator *optc,
-       const struct drr_params *params)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       if (params != NULL &&
-               params->vertical_total_max > 0 &&
-               params->vertical_total_min > 0) {
-
-               if (params->vertical_total_mid != 0) {
-
-                       REG_SET(OTG_V_TOTAL_MID, 0,
-                               OTG_V_TOTAL_MID, params->vertical_total_mid - 1);
-
-                       REG_UPDATE_2(OTG_V_TOTAL_CONTROL,
-                                       OTG_VTOTAL_MID_REPLACING_MAX_EN, 1,
-                                       OTG_VTOTAL_MID_FRAME_NUM,
-                                       (uint8_t)params->vertical_total_mid_frame_num);
-
-               }
-
-               optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1);
-
-               /*
-                * MIN_MASK_EN is gone and MASK is now always enabled.
-                *
-                * To get it to it work with manual trigger we need to make sure
-                * we program the correct bit.
-                */
-               REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
-                               OTG_V_TOTAL_MIN_SEL, 1,
-                               OTG_V_TOTAL_MAX_SEL, 1,
-                               OTG_FORCE_LOCK_ON_EVENT, 0,
-                               OTG_SET_V_TOTAL_MIN_MASK, (1 << 1)); /* TRIGA */
-
-               // Setup manual flow control for EOF via TRIG_A
-               optc->funcs->setup_manual_trigger(optc);
-       } else {
-               REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
-                               OTG_SET_V_TOTAL_MIN_MASK, 0,
-                               OTG_V_TOTAL_MIN_SEL, 0,
-                               OTG_V_TOTAL_MAX_SEL, 0,
-                               OTG_FORCE_LOCK_ON_EVENT, 0);
-
-               optc->funcs->set_vtotal_min_max(optc, 0, 0);
-       }
-}
-
-void optc3_init_odm(struct timing_generator *optc)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
-                       OPTC_NUM_OF_INPUT_SEGMENT, 0,
-                       OPTC_SEG0_SRC_SEL, optc->inst,
-                       OPTC_SEG1_SRC_SEL, 0xf,
-                       OPTC_SEG2_SRC_SEL, 0xf,
-                       OPTC_SEG3_SRC_SEL, 0xf
-                       );
-
-       REG_SET(OTG_H_TIMING_CNTL, 0,
-                       OTG_H_TIMING_DIV_MODE, 0);
-
-       REG_SET(OPTC_MEMORY_CONFIG, 0,
-                       OPTC_MEM_SEL, 0);
-       optc1->opp_count = 1;
-}
-
-static struct timing_generator_funcs dcn31_tg_funcs = {
-               .validate_timing = optc1_validate_timing,
-               .program_timing = optc1_program_timing,
-               .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
-               .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
-               .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
-               .program_global_sync = optc1_program_global_sync,
-               .enable_crtc = optc31_enable_crtc,
-               .disable_crtc = optc31_disable_crtc,
-               .immediate_disable_crtc = optc31_immediate_disable_crtc,
-               /* used by enable_timing_synchronization. Not need for FPGA */
-               .is_counter_moving = optc1_is_counter_moving,
-               .get_position = optc1_get_position,
-               .get_frame_count = optc1_get_vblank_counter,
-               .get_scanoutpos = optc1_get_crtc_scanoutpos,
-               .get_otg_active_size = optc1_get_otg_active_size,
-               .set_early_control = optc1_set_early_control,
-               /* used by enable_timing_synchronization. Not need for FPGA */
-               .wait_for_state = optc1_wait_for_state,
-               .set_blank_color = optc3_program_blank_color,
-               .did_triggered_reset_occur = optc1_did_triggered_reset_occur,
-               .triplebuffer_lock = optc3_triplebuffer_lock,
-               .triplebuffer_unlock = optc2_triplebuffer_unlock,
-               .enable_reset_trigger = optc1_enable_reset_trigger,
-               .enable_crtc_reset = optc1_enable_crtc_reset,
-               .disable_reset_trigger = optc1_disable_reset_trigger,
-               .lock = optc3_lock,
-               .unlock = optc1_unlock,
-               .lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,
-               .lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
-               .enable_optc_clock = optc1_enable_optc_clock,
-               .set_drr = optc31_set_drr,
-               .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
-               .set_vtotal_min_max = optc1_set_vtotal_min_max,
-               .set_static_screen_control = optc1_set_static_screen_control,
-               .program_stereo = optc1_program_stereo,
-               .is_stereo_left_eye = optc1_is_stereo_left_eye,
-               .tg_init = optc3_tg_init,
-               .is_tg_enabled = optc1_is_tg_enabled,
-               .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
-               .clear_optc_underflow = optc1_clear_optc_underflow,
-               .setup_global_swap_lock = NULL,
-               .get_crc = optc1_get_crc,
-               .configure_crc = optc2_configure_crc,
-               .set_dsc_config = optc3_set_dsc_config,
-               .get_dsc_status = optc2_get_dsc_status,
-               .set_dwb_source = NULL,
-               .set_odm_bypass = optc3_set_odm_bypass,
-               .set_odm_combine = optc31_set_odm_combine,
-               .get_optc_source = optc2_get_optc_source,
-               .set_out_mux = optc3_set_out_mux,
-               .set_drr_trigger_window = optc3_set_drr_trigger_window,
-               .set_vtotal_change_limit = optc3_set_vtotal_change_limit,
-               .set_gsl = optc2_set_gsl,
-               .set_gsl_source_select = optc2_set_gsl_source_select,
-               .set_vtg_params = optc1_set_vtg_params,
-               .program_manual_trigger = optc2_program_manual_trigger,
-               .setup_manual_trigger = optc2_setup_manual_trigger,
-               .get_hw_timing = optc1_get_hw_timing,
-               .init_odm = optc3_init_odm,
-};
-
-void dcn31_timing_generator_init(struct optc *optc1)
-{
-       optc1->base.funcs = &dcn31_tg_funcs;
-
-       optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
-       optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
-
-       optc1->min_h_blank = 32;
-       optc1->min_v_blank = 3;
-       optc1->min_v_blank_interlace = 5;
-       optc1->min_h_sync_width = 4;
-       optc1->min_v_sync_width = 1;
-}
-
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h
deleted file mode 100644 (file)
index 30b81a4..0000000
+++ /dev/null
@@ -1,267 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DC_OPTC_DCN31_H__
-#define __DC_OPTC_DCN31_H__
-
-#include "dcn10/dcn10_optc.h"
-
-#define OPTC_COMMON_REG_LIST_DCN3_1(inst) \
-       SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
-       SRI(OTG_VUPDATE_PARAM, OTG, inst),\
-       SRI(OTG_VREADY_PARAM, OTG, inst),\
-       SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
-       SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
-       SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
-       SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
-       SRI(OTG_GLOBAL_CONTROL4, OTG, inst),\
-       SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
-       SRI(OTG_H_TOTAL, OTG, inst),\
-       SRI(OTG_H_BLANK_START_END, OTG, inst),\
-       SRI(OTG_H_SYNC_A, OTG, inst),\
-       SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\
-       SRI(OTG_H_TIMING_CNTL, OTG, inst),\
-       SRI(OTG_V_TOTAL, OTG, inst),\
-       SRI(OTG_V_BLANK_START_END, OTG, inst),\
-       SRI(OTG_V_SYNC_A, OTG, inst),\
-       SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\
-       SRI(OTG_CONTROL, OTG, inst),\
-       SRI(OTG_STEREO_CONTROL, OTG, inst),\
-       SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\
-       SRI(OTG_STEREO_STATUS, OTG, inst),\
-       SRI(OTG_V_TOTAL_MAX, OTG, inst),\
-       SRI(OTG_V_TOTAL_MIN, OTG, inst),\
-       SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\
-       SRI(OTG_TRIGA_CNTL, OTG, inst),\
-       SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\
-       SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\
-       SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\
-       SRI(OTG_STATUS, OTG, inst),\
-       SRI(OTG_STATUS_POSITION, OTG, inst),\
-       SRI(OTG_NOM_VERT_POSITION, OTG, inst),\
-       SRI(OTG_M_CONST_DTO0, OTG, inst),\
-       SRI(OTG_M_CONST_DTO1, OTG, inst),\
-       SRI(OTG_CLOCK_CONTROL, OTG, inst),\
-       SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\
-       SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\
-       SRI(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\
-       SRI(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\
-       SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\
-       SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\
-       SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\
-       SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\
-       SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\
-       SRI(CONTROL, VTG, inst),\
-       SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\
-       SRI(OTG_GSL_CONTROL, OTG, inst),\
-       SRI(OTG_CRC_CNTL, OTG, inst),\
-       SRI(OTG_CRC0_DATA_RG, OTG, inst),\
-       SRI(OTG_CRC0_DATA_B, OTG, inst),\
-       SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\
-       SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\
-       SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\
-       SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\
-       SR(GSL_SOURCE_SELECT),\
-       SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst),\
-       SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
-       SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
-       SRI(OTG_GSL_WINDOW_X, OTG, inst),\
-       SRI(OTG_GSL_WINDOW_Y, OTG, inst),\
-       SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\
-       SRI(OTG_DSC_START_POSITION, OTG, inst),\
-       SRI(OTG_DRR_TRIGGER_WINDOW, OTG, inst),\
-       SRI(OTG_DRR_V_TOTAL_CHANGE, OTG, inst),\
-       SRI(OPTC_DATA_FORMAT_CONTROL, ODM, inst),\
-       SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\
-       SRI(OPTC_WIDTH_CONTROL, ODM, inst),\
-       SRI(OPTC_MEMORY_CONFIG, ODM, inst),\
-       SRI(OTG_CRC_CNTL2, OTG, inst),\
-       SR(DWB_SOURCE_SELECT),\
-       SRI(OTG_DRR_CONTROL, OTG, inst)
-
-#define OPTC_COMMON_MASK_SH_LIST_DCN3_1(mask_sh)\
-       SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
-       SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
-       SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
-       SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
-       SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\
-       SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_START_X, mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_END_X, mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_START_Y, mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_END_Y, mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL2, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_X, mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_Y, mask_sh),\
-       SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\
-       SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
-       SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_START, mask_sh),\
-       SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_END, mask_sh),\
-       SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_START, mask_sh),\
-       SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_END, mask_sh),\
-       SF(OTG0_OTG_H_SYNC_A_CNTL, OTG_H_SYNC_A_POL, mask_sh),\
-       SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
-       SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_START, mask_sh),\
-       SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_END, mask_sh),\
-       SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_START, mask_sh),\
-       SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_END, mask_sh),\
-       SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_A_POL, mask_sh),\
-       SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, mask_sh),\
-       SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
-       SF(OTG0_OTG_CONTROL, OTG_START_POINT_CNTL, mask_sh),\
-       SF(OTG0_OTG_CONTROL, OTG_DISABLE_POINT_CNTL, mask_sh),\
-       SF(OTG0_OTG_CONTROL, OTG_FIELD_NUMBER_CNTL, mask_sh),\
-       SF(OTG0_OTG_CONTROL, OTG_OUT_MUX, mask_sh),\
-       SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EN, mask_sh),\
-       SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_LINE_NUM, mask_sh),\
-       SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_POLARITY, mask_sh),\
-       SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EYE_FLAG_POLARITY, mask_sh),\
-       SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\
-       SF(OTG0_OTG_STEREO_STATUS, OTG_STEREO_CURRENT_EYE, mask_sh),\
-       SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_EN, mask_sh),\
-       SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\
-       SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\
-       SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\
-       SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\
-       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\
-       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\
-       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\
-       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\
-       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MIN_EN, mask_sh),\
-       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\
-       SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\
-       SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\
-       SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\
-       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_SELECT, mask_sh),\
-       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_PIPE_SELECT, mask_sh),\
-       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_RISING_EDGE_DETECT_CNTL, mask_sh),\
-       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, mask_sh),\
-       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_POLARITY_SELECT, mask_sh),\
-       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FREQUENCY_SELECT, mask_sh),\
-       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_DELAY, mask_sh),\
-       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_CLEAR, mask_sh),\
-       SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_EVENT_MASK, mask_sh),\
-       SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_FRAME_COUNT, mask_sh),\
-       SF(OTG0_OTG_STATUS_FRAME_COUNT, OTG_FRAME_COUNT, mask_sh),\
-       SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
-       SF(OTG0_OTG_STATUS, OTG_V_ACTIVE_DISP, mask_sh),\
-       SF(OTG0_OTG_STATUS_POSITION, OTG_HORZ_COUNT, mask_sh),\
-       SF(OTG0_OTG_STATUS_POSITION, OTG_VERT_COUNT, mask_sh),\
-       SF(OTG0_OTG_NOM_VERT_POSITION, OTG_VERT_COUNT_NOM, mask_sh),\
-       SF(OTG0_OTG_M_CONST_DTO0, OTG_M_CONST_DTO_PHASE, mask_sh),\
-       SF(OTG0_OTG_M_CONST_DTO1, OTG_M_CONST_DTO_MODULO, mask_sh),\
-       SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\
-       SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\
-       SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\
-       SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\
-       SF(OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE, mask_sh),\
-       SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_START, mask_sh),\
-       SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_END, mask_sh),\
-       SF(OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_INT_ENABLE, mask_sh),\
-       SF(OTG0_OTG_VERTICAL_INTERRUPT1_POSITION, OTG_VERTICAL_INTERRUPT1_LINE_START, mask_sh),\
-       SF(OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE, mask_sh),\
-       SF(OTG0_OTG_VERTICAL_INTERRUPT2_POSITION, OTG_VERTICAL_INTERRUPT2_LINE_START, mask_sh),\
-       SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\
-       SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\
-       SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\
-       SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\
-       SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\
-       SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
-       SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
-       SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
-       SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, mask_sh),\
-       SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, mask_sh),\
-       SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_AUTO_FORCE_VSYNC_MODE, mask_sh),\
-       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL0_EN, mask_sh),\
-       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL1_EN, mask_sh),\
-       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL2_EN, mask_sh),\
-       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_EN, mask_sh),\
-       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_FORCE_DELAY, mask_sh),\
-       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\
-       SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\
-       SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\
-       SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
-       SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\
-       SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\
-       SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\
-       SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_START, mask_sh),\
-       SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_END, mask_sh),\
-       SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_START, mask_sh),\
-       SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_END, mask_sh),\
-       SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_START, mask_sh),\
-       SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\
-       SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\
-       SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\
-       SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\
-       SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\
-       SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\
-       SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\
-       SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\
-       SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \
-       SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\
-       SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\
-       SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, mask_sh), \
-       SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, mask_sh), \
-       SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, mask_sh), \
-       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_MODE, mask_sh), \
-       SF(OTG0_OTG_GSL_CONTROL, OTG_MASTER_UPDATE_LOCK_GSL_EN, mask_sh), \
-       SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_X, mask_sh), \
-       SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_LINE_NUM, mask_sh),\
-       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG0_SRC_SEL, mask_sh),\
-       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG1_SRC_SEL, mask_sh),\
-       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG2_SRC_SEL, mask_sh),\
-       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG3_SRC_SEL, mask_sh),\
-       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, mask_sh),\
-       SF(ODM0_OPTC_MEMORY_CONFIG, OPTC_MEM_SEL, mask_sh),\
-       SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, mask_sh),\
-       SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\
-       SF(ODM0_OPTC_BYTES_PER_PIXEL, OPTC_DSC_BYTES_PER_PIXEL, mask_sh),\
-       SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, mask_sh),\
-       SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_SEGMENT_WIDTH, mask_sh),\
-       SF(DWB_SOURCE_SELECT, OPTC_DWB0_SOURCE_SELECT, mask_sh),\
-       SF(DWB_SOURCE_SELECT, OPTC_DWB1_SOURCE_SELECT, mask_sh),\
-       SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_START_X, mask_sh),\
-       SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_END_X, mask_sh),\
-       SF(OTG0_OTG_DRR_V_TOTAL_CHANGE, OTG_DRR_V_TOTAL_CHANGE_LIMIT, mask_sh),\
-       SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\
-       SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh),\
-       SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DSC_MODE, mask_sh),\
-       SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_COMBINE_MODE, mask_sh),\
-       SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_SPLIT_MODE, mask_sh),\
-       SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_FORMAT, mask_sh),\
-       SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh)
-
-void dcn31_timing_generator_init(struct optc *optc1);
-
-bool optc31_immediate_disable_crtc(struct timing_generator *optc);
-
-void optc31_set_drr(struct timing_generator *optc, const struct drr_params *params);
-
-void optc3_init_odm(struct timing_generator *optc);
-
-#endif /* __DC_OPTC_DCN31_H__ */
index 6ea47e00d62d43ced6e586855958890c2dc45873..d5c177346a3bfb1533c7c1d052bebe903da97fe8 100644 (file)
@@ -11,7 +11,7 @@
 # Makefile for dcn314.
 
 DCN314 = dcn314_init.o \
-               dcn314_dio_stream_encoder.o dcn314_dccg.o dcn314_optc.o
+               dcn314_dio_stream_encoder.o dcn314_dccg.o
 
 AMD_DAL_DCN314 = $(addprefix $(AMDDALPATH)/dc/dcn314/,$(DCN314))
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.c b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.c
deleted file mode 100644 (file)
index 0086caf..0000000
+++ /dev/null
@@ -1,273 +0,0 @@
-// SPDX-License-Identifier: MIT
-/*
- * Copyright 2022 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dcn314_optc.h"
-
-#include "dcn30/dcn30_optc.h"
-#include "dcn31/dcn31_optc.h"
-#include "reg_helper.h"
-#include "dc.h"
-#include "dcn_calc_math.h"
-
-#define REG(reg)\
-       optc1->tg_regs->reg
-
-#define CTX \
-       optc1->base.ctx
-
-#undef FN
-#define FN(reg_name, field_name) \
-       optc1->tg_shift->field_name, optc1->tg_mask->field_name
-
-/*
- * Enable CRTC
- * Enable CRTC - call ASIC Control Object to enable Timing generator.
- */
-
-static void optc314_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
-               struct dc_crtc_timing *timing)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-       uint32_t memory_mask = 0;
-       int h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right;
-       int mpcc_hactive = h_active / opp_cnt;
-       /* Each memory instance is 2048x(314x2) bits to support half line of 4096 */
-       int odm_mem_count = (h_active + 2047) / 2048;
-
-       /*
-        * display <= 4k : 2 memories + 2 pipes
-        * 4k < display <= 8k : 4 memories + 2 pipes
-        * 8k < display <= 12k : 6 memories + 4 pipes
-        */
-       if (opp_cnt == 4) {
-               if (odm_mem_count <= 2)
-                       memory_mask = 0x3;
-               else if (odm_mem_count <= 4)
-                       memory_mask = 0xf;
-               else
-                       memory_mask = 0x3f;
-       } else {
-               if (odm_mem_count <= 2)
-                       memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2);
-               else if (odm_mem_count <= 4)
-                       memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);
-               else
-                       memory_mask = 0x77;
-       }
-
-       REG_SET(OPTC_MEMORY_CONFIG, 0,
-               OPTC_MEM_SEL, memory_mask);
-
-       if (opp_cnt == 2) {
-               REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
-                               OPTC_NUM_OF_INPUT_SEGMENT, 1,
-                               OPTC_SEG0_SRC_SEL, opp_id[0],
-                               OPTC_SEG1_SRC_SEL, opp_id[1]);
-       } else if (opp_cnt == 4) {
-               REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
-                               OPTC_NUM_OF_INPUT_SEGMENT, 3,
-                               OPTC_SEG0_SRC_SEL, opp_id[0],
-                               OPTC_SEG1_SRC_SEL, opp_id[1],
-                               OPTC_SEG2_SRC_SEL, opp_id[2],
-                               OPTC_SEG3_SRC_SEL, opp_id[3]);
-       }
-
-       REG_UPDATE(OPTC_WIDTH_CONTROL,
-                       OPTC_SEGMENT_WIDTH, mpcc_hactive);
-
-       REG_UPDATE(OTG_H_TIMING_CNTL,
-                       OTG_H_TIMING_DIV_MODE, opp_cnt - 1);
-       optc1->opp_count = opp_cnt;
-}
-
-static bool optc314_enable_crtc(struct timing_generator *optc)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       /* opp instance for OTG, 1 to 1 mapping and odm will adjust */
-       REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
-                       OPTC_SEG0_SRC_SEL, optc->inst);
-
-       /* VTG enable first is for HW workaround */
-       REG_UPDATE(CONTROL,
-                       VTG0_ENABLE, 1);
-
-       REG_SEQ_START();
-
-       /* Enable CRTC */
-       REG_UPDATE_2(OTG_CONTROL,
-                       OTG_DISABLE_POINT_CNTL, 2,
-                       OTG_MASTER_EN, 1);
-
-       REG_SEQ_SUBMIT();
-       REG_SEQ_WAIT_DONE();
-
-       return true;
-}
-
-/* disable_crtc */
-static bool optc314_disable_crtc(struct timing_generator *optc)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       /* disable otg request until end of the first line
-        * in the vertical blank region
-        */
-       REG_UPDATE(OTG_CONTROL,
-                       OTG_MASTER_EN, 0);
-
-       REG_UPDATE(CONTROL,
-                       VTG0_ENABLE, 0);
-
-       /* CRTC disabled, so disable  clock. */
-       REG_WAIT(OTG_CLOCK_CONTROL,
-                       OTG_BUSY, 0,
-                       1, 100000);
-
-       return true;
-}
-
-static void optc314_phantom_crtc_post_enable(struct timing_generator *optc)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       /* Disable immediately. */
-       REG_UPDATE_2(OTG_CONTROL, OTG_DISABLE_POINT_CNTL, 0, OTG_MASTER_EN, 0);
-
-       /* CRTC disabled, so disable  clock. */
-       REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 100000);
-}
-
-static void optc314_set_odm_bypass(struct timing_generator *optc,
-               const struct dc_crtc_timing *dc_crtc_timing)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-       enum h_timing_div_mode h_div = H_TIMING_NO_DIV;
-
-       REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
-                       OPTC_NUM_OF_INPUT_SEGMENT, 0,
-                       OPTC_SEG0_SRC_SEL, optc->inst,
-                       OPTC_SEG1_SRC_SEL, 0xf,
-                       OPTC_SEG2_SRC_SEL, 0xf,
-                       OPTC_SEG3_SRC_SEL, 0xf
-                       );
-
-       h_div = optc1_is_two_pixels_per_containter(dc_crtc_timing);
-       REG_UPDATE(OTG_H_TIMING_CNTL,
-                       OTG_H_TIMING_DIV_MODE, h_div);
-
-       REG_SET(OPTC_MEMORY_CONFIG, 0,
-                       OPTC_MEM_SEL, 0);
-       optc1->opp_count = 1;
-}
-
-static void optc314_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       REG_UPDATE(OTG_H_TIMING_CNTL,
-                       OTG_H_TIMING_DIV_MODE_MANUAL, manual_mode ? 1 : 0);
-}
-
-
-static struct timing_generator_funcs dcn314_tg_funcs = {
-               .validate_timing = optc1_validate_timing,
-               .program_timing = optc1_program_timing,
-               .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
-               .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
-               .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
-               .program_global_sync = optc1_program_global_sync,
-               .enable_crtc = optc314_enable_crtc,
-               .disable_crtc = optc314_disable_crtc,
-               .immediate_disable_crtc = optc31_immediate_disable_crtc,
-               .phantom_crtc_post_enable = optc314_phantom_crtc_post_enable,
-               /* used by enable_timing_synchronization. Not need for FPGA */
-               .is_counter_moving = optc1_is_counter_moving,
-               .get_position = optc1_get_position,
-               .get_frame_count = optc1_get_vblank_counter,
-               .get_scanoutpos = optc1_get_crtc_scanoutpos,
-               .get_otg_active_size = optc1_get_otg_active_size,
-               .set_early_control = optc1_set_early_control,
-               /* used by enable_timing_synchronization. Not need for FPGA */
-               .wait_for_state = optc1_wait_for_state,
-               .set_blank_color = optc3_program_blank_color,
-               .did_triggered_reset_occur = optc1_did_triggered_reset_occur,
-               .triplebuffer_lock = optc3_triplebuffer_lock,
-               .triplebuffer_unlock = optc2_triplebuffer_unlock,
-               .enable_reset_trigger = optc1_enable_reset_trigger,
-               .enable_crtc_reset = optc1_enable_crtc_reset,
-               .disable_reset_trigger = optc1_disable_reset_trigger,
-               .lock = optc3_lock,
-               .unlock = optc1_unlock,
-               .lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,
-               .lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
-               .enable_optc_clock = optc1_enable_optc_clock,
-               .set_drr = optc31_set_drr,
-               .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
-               .set_vtotal_min_max = optc1_set_vtotal_min_max,
-               .set_static_screen_control = optc1_set_static_screen_control,
-               .program_stereo = optc1_program_stereo,
-               .is_stereo_left_eye = optc1_is_stereo_left_eye,
-               .tg_init = optc3_tg_init,
-               .is_tg_enabled = optc1_is_tg_enabled,
-               .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
-               .clear_optc_underflow = optc1_clear_optc_underflow,
-               .setup_global_swap_lock = NULL,
-               .get_crc = optc1_get_crc,
-               .configure_crc = optc1_configure_crc,
-               .set_dsc_config = optc3_set_dsc_config,
-               .get_dsc_status = optc2_get_dsc_status,
-               .set_dwb_source = NULL,
-               .get_optc_source = optc2_get_optc_source,
-               .set_out_mux = optc3_set_out_mux,
-               .set_drr_trigger_window = optc3_set_drr_trigger_window,
-               .set_vtotal_change_limit = optc3_set_vtotal_change_limit,
-               .set_gsl = optc2_set_gsl,
-               .set_gsl_source_select = optc2_set_gsl_source_select,
-               .set_vtg_params = optc1_set_vtg_params,
-               .program_manual_trigger = optc2_program_manual_trigger,
-               .setup_manual_trigger = optc2_setup_manual_trigger,
-               .get_hw_timing = optc1_get_hw_timing,
-               .init_odm = optc3_init_odm,
-               .set_odm_bypass = optc314_set_odm_bypass,
-               .set_odm_combine = optc314_set_odm_combine,
-               .set_h_timing_div_manual_mode = optc314_set_h_timing_div_manual_mode,
-};
-
-void dcn314_timing_generator_init(struct optc *optc1)
-{
-       optc1->base.funcs = &dcn314_tg_funcs;
-
-       optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
-       optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
-
-       optc1->min_h_blank = 32;
-       optc1->min_v_blank = 3;
-       optc1->min_v_blank_interlace = 5;
-       optc1->min_h_sync_width = 4;
-       optc1->min_v_sync_width = 1;
-}
-
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.h b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.h
deleted file mode 100644 (file)
index 99c098e..0000000
+++ /dev/null
@@ -1,255 +0,0 @@
-/* SPDX-License-Identifier: MIT */
-/*
- * Copyright 2022 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DC_OPTC_DCN314_H__
-#define __DC_OPTC_DCN314_H__
-
-#include "dcn10/dcn10_optc.h"
-
-#define OPTC_COMMON_REG_LIST_DCN3_14(inst) \
-       SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
-       SRI(OTG_VUPDATE_PARAM, OTG, inst),\
-       SRI(OTG_VREADY_PARAM, OTG, inst),\
-       SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
-       SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
-       SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
-       SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
-       SRI(OTG_GLOBAL_CONTROL4, OTG, inst),\
-       SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
-       SRI(OTG_H_TOTAL, OTG, inst),\
-       SRI(OTG_H_BLANK_START_END, OTG, inst),\
-       SRI(OTG_H_SYNC_A, OTG, inst),\
-       SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\
-       SRI(OTG_H_TIMING_CNTL, OTG, inst),\
-       SRI(OTG_V_TOTAL, OTG, inst),\
-       SRI(OTG_V_BLANK_START_END, OTG, inst),\
-       SRI(OTG_V_SYNC_A, OTG, inst),\
-       SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\
-       SRI(OTG_CONTROL, OTG, inst),\
-       SRI(OTG_STEREO_CONTROL, OTG, inst),\
-       SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\
-       SRI(OTG_STEREO_STATUS, OTG, inst),\
-       SRI(OTG_V_TOTAL_MAX, OTG, inst),\
-       SRI(OTG_V_TOTAL_MIN, OTG, inst),\
-       SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\
-       SRI(OTG_TRIGA_CNTL, OTG, inst),\
-       SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\
-       SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\
-       SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\
-       SRI(OTG_STATUS, OTG, inst),\
-       SRI(OTG_STATUS_POSITION, OTG, inst),\
-       SRI(OTG_NOM_VERT_POSITION, OTG, inst),\
-       SRI(OTG_M_CONST_DTO0, OTG, inst),\
-       SRI(OTG_M_CONST_DTO1, OTG, inst),\
-       SRI(OTG_CLOCK_CONTROL, OTG, inst),\
-       SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\
-       SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\
-       SRI(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\
-       SRI(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\
-       SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\
-       SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\
-       SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\
-       SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\
-       SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\
-       SRI(CONTROL, VTG, inst),\
-       SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\
-       SRI(OTG_GSL_CONTROL, OTG, inst),\
-       SRI(OTG_CRC_CNTL, OTG, inst),\
-       SRI(OTG_CRC0_DATA_RG, OTG, inst),\
-       SRI(OTG_CRC0_DATA_B, OTG, inst),\
-       SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\
-       SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\
-       SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\
-       SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\
-       SR(GSL_SOURCE_SELECT),\
-       SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst),\
-       SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
-       SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
-       SRI(OTG_GSL_WINDOW_X, OTG, inst),\
-       SRI(OTG_GSL_WINDOW_Y, OTG, inst),\
-       SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\
-       SRI(OTG_DSC_START_POSITION, OTG, inst),\
-       SRI(OTG_DRR_TRIGGER_WINDOW, OTG, inst),\
-       SRI(OTG_DRR_V_TOTAL_CHANGE, OTG, inst),\
-       SRI(OPTC_DATA_FORMAT_CONTROL, ODM, inst),\
-       SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\
-       SRI(OPTC_WIDTH_CONTROL, ODM, inst),\
-       SRI(OPTC_MEMORY_CONFIG, ODM, inst),\
-       SRI(OTG_DRR_CONTROL, OTG, inst)
-
-#define OPTC_COMMON_MASK_SH_LIST_DCN3_14(mask_sh)\
-       SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
-       SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
-       SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
-       SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
-       SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\
-       SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_START_X, mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_END_X, mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_START_Y, mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_END_Y, mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL2, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_X, mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_Y, mask_sh),\
-       SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\
-       SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
-       SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_START, mask_sh),\
-       SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_END, mask_sh),\
-       SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_START, mask_sh),\
-       SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_END, mask_sh),\
-       SF(OTG0_OTG_H_SYNC_A_CNTL, OTG_H_SYNC_A_POL, mask_sh),\
-       SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
-       SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_START, mask_sh),\
-       SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_END, mask_sh),\
-       SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_START, mask_sh),\
-       SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_END, mask_sh),\
-       SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_A_POL, mask_sh),\
-       SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, mask_sh),\
-       SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
-       SF(OTG0_OTG_CONTROL, OTG_START_POINT_CNTL, mask_sh),\
-       SF(OTG0_OTG_CONTROL, OTG_DISABLE_POINT_CNTL, mask_sh),\
-       SF(OTG0_OTG_CONTROL, OTG_FIELD_NUMBER_CNTL, mask_sh),\
-       SF(OTG0_OTG_CONTROL, OTG_OUT_MUX, mask_sh),\
-       SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EN, mask_sh),\
-       SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_LINE_NUM, mask_sh),\
-       SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_POLARITY, mask_sh),\
-       SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EYE_FLAG_POLARITY, mask_sh),\
-       SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\
-       SF(OTG0_OTG_STEREO_STATUS, OTG_STEREO_CURRENT_EYE, mask_sh),\
-       SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_EN, mask_sh),\
-       SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\
-       SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\
-       SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\
-       SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\
-       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\
-       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\
-       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\
-       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\
-       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MIN_EN, mask_sh),\
-       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\
-       SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\
-       SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\
-       SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\
-       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_SELECT, mask_sh),\
-       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_PIPE_SELECT, mask_sh),\
-       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_RISING_EDGE_DETECT_CNTL, mask_sh),\
-       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, mask_sh),\
-       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_POLARITY_SELECT, mask_sh),\
-       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FREQUENCY_SELECT, mask_sh),\
-       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_DELAY, mask_sh),\
-       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_CLEAR, mask_sh),\
-       SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_EVENT_MASK, mask_sh),\
-       SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_FRAME_COUNT, mask_sh),\
-       SF(OTG0_OTG_STATUS_FRAME_COUNT, OTG_FRAME_COUNT, mask_sh),\
-       SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
-       SF(OTG0_OTG_STATUS, OTG_V_ACTIVE_DISP, mask_sh),\
-       SF(OTG0_OTG_STATUS_POSITION, OTG_HORZ_COUNT, mask_sh),\
-       SF(OTG0_OTG_STATUS_POSITION, OTG_VERT_COUNT, mask_sh),\
-       SF(OTG0_OTG_NOM_VERT_POSITION, OTG_VERT_COUNT_NOM, mask_sh),\
-       SF(OTG0_OTG_M_CONST_DTO0, OTG_M_CONST_DTO_PHASE, mask_sh),\
-       SF(OTG0_OTG_M_CONST_DTO1, OTG_M_CONST_DTO_MODULO, mask_sh),\
-       SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\
-       SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\
-       SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\
-       SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\
-       SF(OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE, mask_sh),\
-       SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_START, mask_sh),\
-       SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_END, mask_sh),\
-       SF(OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_INT_ENABLE, mask_sh),\
-       SF(OTG0_OTG_VERTICAL_INTERRUPT1_POSITION, OTG_VERTICAL_INTERRUPT1_LINE_START, mask_sh),\
-       SF(OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE, mask_sh),\
-       SF(OTG0_OTG_VERTICAL_INTERRUPT2_POSITION, OTG_VERTICAL_INTERRUPT2_LINE_START, mask_sh),\
-       SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\
-       SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\
-       SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\
-       SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\
-       SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\
-       SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
-       SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
-       SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
-       SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, mask_sh),\
-       SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, mask_sh),\
-       SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_AUTO_FORCE_VSYNC_MODE, mask_sh),\
-       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL0_EN, mask_sh),\
-       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL1_EN, mask_sh),\
-       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL2_EN, mask_sh),\
-       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_EN, mask_sh),\
-       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_FORCE_DELAY, mask_sh),\
-       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\
-       SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\
-       SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\
-       SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
-       SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\
-       SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\
-       SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\
-       SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_START, mask_sh),\
-       SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_END, mask_sh),\
-       SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_START, mask_sh),\
-       SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_END, mask_sh),\
-       SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_START, mask_sh),\
-       SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\
-       SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\
-       SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\
-       SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\
-       SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\
-       SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\
-       SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\
-       SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\
-       SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \
-       SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\
-       SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\
-       SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, mask_sh), \
-       SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, mask_sh), \
-       SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, mask_sh), \
-       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_MODE, mask_sh), \
-       SF(OTG0_OTG_GSL_CONTROL, OTG_MASTER_UPDATE_LOCK_GSL_EN, mask_sh), \
-       SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_X, mask_sh), \
-       SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_LINE_NUM, mask_sh),\
-       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG0_SRC_SEL, mask_sh),\
-       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG1_SRC_SEL, mask_sh),\
-       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG2_SRC_SEL, mask_sh),\
-       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG3_SRC_SEL, mask_sh),\
-       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, mask_sh),\
-       SF(ODM0_OPTC_MEMORY_CONFIG, OPTC_MEM_SEL, mask_sh),\
-       SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, mask_sh),\
-       SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\
-       SF(ODM0_OPTC_BYTES_PER_PIXEL, OPTC_DSC_BYTES_PER_PIXEL, mask_sh),\
-       SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, mask_sh),\
-       SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_SEGMENT_WIDTH, mask_sh),\
-       SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_START_X, mask_sh),\
-       SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_END_X, mask_sh),\
-       SF(OTG0_OTG_DRR_V_TOTAL_CHANGE, OTG_DRR_V_TOTAL_CHANGE_LIMIT, mask_sh),\
-       SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\
-       SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE_MANUAL, mask_sh),\
-       SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh),\
-       SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh)
-
-void dcn314_timing_generator_init(struct optc *optc1);
-
-#endif /* __DC_OPTC_DCN314_H__ */
index 3bb17dd01e4ce3d6cb8d4e5bb8d2dd9d6ec4ab27..905b74b5309201e5bf34c7d280e6afc83413167f 100644 (file)
@@ -11,9 +11,9 @@
 # Makefile for dcn32.
 
 DCN32 = dcn32_hubbub.o dcn32_init.o dcn32_dccg.o \
-               dcn32_dccg.o dcn32_optc.o dcn32_mmhubbub.o dcn32_hubp.o dcn32_dpp.o \
-               dcn32_dio_stream_encoder.o dcn32_dio_link_encoder.o dcn32_hpo_dp_link_encoder.o \
-               dcn32_resource_helpers.o dcn32_mpc.o
+               dcn32_mmhubbub.o dcn32_dpp.o dcn32_hubp.o dcn32_mpc.o \
+               dcn32_dio_stream_encoder.o dcn32_dio_link_encoder.o dcn32_resource_helpers.o \
+               dcn32_hpo_dp_link_encoder.o
 
 AMD_DAL_DCN32 = $(addprefix $(AMDDALPATH)/dc/dcn32/,$(DCN32))
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
deleted file mode 100644 (file)
index a2c4db2..0000000
+++ /dev/null
@@ -1,357 +0,0 @@
-/*
- * Copyright 2022 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dcn32_optc.h"
-
-#include "dcn30/dcn30_optc.h"
-#include "dcn31/dcn31_optc.h"
-#include "reg_helper.h"
-#include "dc.h"
-#include "dcn_calc_math.h"
-#include "dc_dmub_srv.h"
-
-#define REG(reg)\
-       optc1->tg_regs->reg
-
-#define CTX \
-       optc1->base.ctx
-
-#undef FN
-#define FN(reg_name, field_name) \
-       optc1->tg_shift->field_name, optc1->tg_mask->field_name
-
-static void optc32_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
-               struct dc_crtc_timing *timing)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-       uint32_t memory_mask = 0;
-       int h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right;
-       int mpcc_hactive = h_active / opp_cnt;
-       /* Each memory instance is 2048x(32x2) bits to support half line of 4096 */
-       int odm_mem_count = (h_active + 2047) / 2048;
-
-       /*
-        * display <= 4k : 2 memories + 2 pipes
-        * 4k < display <= 8k : 4 memories + 2 pipes
-        * 8k < display <= 12k : 6 memories + 4 pipes
-        */
-       if (opp_cnt == 4) {
-               if (odm_mem_count <= 2)
-                       memory_mask = 0x3;
-               else if (odm_mem_count <= 4)
-                       memory_mask = 0xf;
-               else
-                       memory_mask = 0x3f;
-       } else {
-               if (odm_mem_count <= 2)
-                       memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2);
-               else if (odm_mem_count <= 4)
-                       memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);
-               else
-                       memory_mask = 0x77;
-       }
-
-       REG_SET(OPTC_MEMORY_CONFIG, 0,
-               OPTC_MEM_SEL, memory_mask);
-
-       if (opp_cnt == 2) {
-               REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
-                               OPTC_NUM_OF_INPUT_SEGMENT, 1,
-                               OPTC_SEG0_SRC_SEL, opp_id[0],
-                               OPTC_SEG1_SRC_SEL, opp_id[1]);
-       } else if (opp_cnt == 4) {
-               REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
-                               OPTC_NUM_OF_INPUT_SEGMENT, 3,
-                               OPTC_SEG0_SRC_SEL, opp_id[0],
-                               OPTC_SEG1_SRC_SEL, opp_id[1],
-                               OPTC_SEG2_SRC_SEL, opp_id[2],
-                               OPTC_SEG3_SRC_SEL, opp_id[3]);
-       }
-
-       REG_UPDATE(OPTC_WIDTH_CONTROL,
-                       OPTC_SEGMENT_WIDTH, mpcc_hactive);
-
-       REG_UPDATE(OTG_H_TIMING_CNTL,
-                       OTG_H_TIMING_DIV_MODE, opp_cnt - 1);
-       optc1->opp_count = opp_cnt;
-}
-
-void optc32_get_odm_combine_segments(struct timing_generator *tg, int *odm_combine_segments)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(tg);
-       int segments;
-
-       REG_GET(OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, &segments);
-
-       switch (segments) {
-       case 0:
-               *odm_combine_segments = 1;
-               break;
-       case 1:
-               *odm_combine_segments = 2;
-               break;
-       case 3:
-               *odm_combine_segments = 4;
-               break;
-       /* 2 is reserved */
-       case 2:
-       default:
-               *odm_combine_segments = -1;
-       }
-}
-
-void optc32_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       REG_UPDATE(OTG_H_TIMING_CNTL,
-                       OTG_H_TIMING_DIV_MODE_MANUAL, manual_mode ? 1 : 0);
-}
-/**
- * optc32_enable_crtc() - Enable CRTC - call ASIC Control Object to enable Timing generator.
- *
- * @optc: timing_generator instance.
- *
- * Return: If CRTC is enabled, return true.
- */
-static bool optc32_enable_crtc(struct timing_generator *optc)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       /* opp instance for OTG, 1 to 1 mapping and odm will adjust */
-       REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
-                       OPTC_SEG0_SRC_SEL, optc->inst);
-
-       /* VTG enable first is for HW workaround */
-       REG_UPDATE(CONTROL,
-                       VTG0_ENABLE, 1);
-
-       REG_SEQ_START();
-
-       /* Enable CRTC */
-       REG_UPDATE_2(OTG_CONTROL,
-                       OTG_DISABLE_POINT_CNTL, 2,
-                       OTG_MASTER_EN, 1);
-
-       REG_SEQ_SUBMIT();
-       REG_SEQ_WAIT_DONE();
-
-       return true;
-}
-
-/* disable_crtc */
-static bool optc32_disable_crtc(struct timing_generator *optc)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       /* disable otg request until end of the first line
-        * in the vertical blank region
-        */
-       REG_UPDATE(OTG_CONTROL,
-                       OTG_MASTER_EN, 0);
-
-       REG_UPDATE(CONTROL,
-                       VTG0_ENABLE, 0);
-
-       /* CRTC disabled, so disable  clock. */
-       REG_WAIT(OTG_CLOCK_CONTROL,
-                       OTG_BUSY, 0,
-                       1, 150000);
-
-       return true;
-}
-
-static void optc32_phantom_crtc_post_enable(struct timing_generator *optc)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       /* Disable immediately. */
-       REG_UPDATE_2(OTG_CONTROL, OTG_DISABLE_POINT_CNTL, 0, OTG_MASTER_EN, 0);
-
-       /* CRTC disabled, so disable  clock. */
-       REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 100000);
-}
-
-static void optc32_disable_phantom_otg(struct timing_generator *optc)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       REG_UPDATE(OTG_CONTROL, OTG_MASTER_EN, 0);
-}
-
-void optc32_set_odm_bypass(struct timing_generator *optc,
-               const struct dc_crtc_timing *dc_crtc_timing)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-       enum h_timing_div_mode h_div = H_TIMING_NO_DIV;
-
-       REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
-                       OPTC_NUM_OF_INPUT_SEGMENT, 0,
-                       OPTC_SEG0_SRC_SEL, optc->inst,
-                       OPTC_SEG1_SRC_SEL, 0xf,
-                       OPTC_SEG2_SRC_SEL, 0xf,
-                       OPTC_SEG3_SRC_SEL, 0xf
-                       );
-
-       h_div = optc1_is_two_pixels_per_containter(dc_crtc_timing);
-       REG_UPDATE(OTG_H_TIMING_CNTL,
-                       OTG_H_TIMING_DIV_MODE, h_div);
-
-       REG_SET(OPTC_MEMORY_CONFIG, 0,
-                       OPTC_MEM_SEL, 0);
-       optc1->opp_count = 1;
-}
-
-static void optc32_setup_manual_trigger(struct timing_generator *optc)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-       struct dc *dc = optc->ctx->dc;
-
-       if (dc->caps.dmub_caps.mclk_sw && !dc->debug.disable_fams)
-               dc_dmub_srv_set_drr_manual_trigger_cmd(dc, optc->inst);
-       else {
-               /*
-                * MIN_MASK_EN is gone and MASK is now always enabled.
-                *
-                * To get it to it work with manual trigger we need to make sure
-                * we program the correct bit.
-                */
-               REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
-                               OTG_V_TOTAL_MIN_SEL, 1,
-                               OTG_V_TOTAL_MAX_SEL, 1,
-                               OTG_FORCE_LOCK_ON_EVENT, 0,
-                               OTG_SET_V_TOTAL_MIN_MASK, (1 << 1)); /* TRIGA */
-
-               // Setup manual flow control for EOF via TRIG_A
-               optc->funcs->setup_manual_trigger(optc);
-       }
-}
-
-static void optc32_set_drr(
-       struct timing_generator *optc,
-       const struct drr_params *params)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       if (params != NULL &&
-               params->vertical_total_max > 0 &&
-               params->vertical_total_min > 0) {
-
-               if (params->vertical_total_mid != 0) {
-
-                       REG_SET(OTG_V_TOTAL_MID, 0,
-                               OTG_V_TOTAL_MID, params->vertical_total_mid - 1);
-
-                       REG_UPDATE_2(OTG_V_TOTAL_CONTROL,
-                                       OTG_VTOTAL_MID_REPLACING_MAX_EN, 1,
-                                       OTG_VTOTAL_MID_FRAME_NUM,
-                                       (uint8_t)params->vertical_total_mid_frame_num);
-
-               }
-
-               optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1);
-       }
-
-       optc32_setup_manual_trigger(optc);
-}
-
-static struct timing_generator_funcs dcn32_tg_funcs = {
-               .validate_timing = optc1_validate_timing,
-               .program_timing = optc1_program_timing,
-               .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
-               .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
-               .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
-               .program_global_sync = optc1_program_global_sync,
-               .enable_crtc = optc32_enable_crtc,
-               .disable_crtc = optc32_disable_crtc,
-               .phantom_crtc_post_enable = optc32_phantom_crtc_post_enable,
-               .disable_phantom_crtc = optc32_disable_phantom_otg,
-               /* used by enable_timing_synchronization. Not need for FPGA */
-               .is_counter_moving = optc1_is_counter_moving,
-               .get_position = optc1_get_position,
-               .get_frame_count = optc1_get_vblank_counter,
-               .get_scanoutpos = optc1_get_crtc_scanoutpos,
-               .get_otg_active_size = optc1_get_otg_active_size,
-               .set_early_control = optc1_set_early_control,
-               /* used by enable_timing_synchronization. Not need for FPGA */
-               .wait_for_state = optc1_wait_for_state,
-               .set_blank_color = optc3_program_blank_color,
-               .did_triggered_reset_occur = optc1_did_triggered_reset_occur,
-               .triplebuffer_lock = optc3_triplebuffer_lock,
-               .triplebuffer_unlock = optc2_triplebuffer_unlock,
-               .enable_reset_trigger = optc1_enable_reset_trigger,
-               .enable_crtc_reset = optc1_enable_crtc_reset,
-               .disable_reset_trigger = optc1_disable_reset_trigger,
-               .lock = optc3_lock,
-               .unlock = optc1_unlock,
-               .lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,
-               .lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
-               .enable_optc_clock = optc1_enable_optc_clock,
-               .set_drr = optc32_set_drr,
-               .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
-               .set_vtotal_min_max = optc3_set_vtotal_min_max,
-               .set_static_screen_control = optc1_set_static_screen_control,
-               .program_stereo = optc1_program_stereo,
-               .is_stereo_left_eye = optc1_is_stereo_left_eye,
-               .tg_init = optc3_tg_init,
-               .is_tg_enabled = optc1_is_tg_enabled,
-               .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
-               .clear_optc_underflow = optc1_clear_optc_underflow,
-               .setup_global_swap_lock = NULL,
-               .get_crc = optc1_get_crc,
-               .configure_crc = optc1_configure_crc,
-               .set_dsc_config = optc3_set_dsc_config,
-               .get_dsc_status = optc2_get_dsc_status,
-               .set_dwb_source = NULL,
-               .set_odm_bypass = optc32_set_odm_bypass,
-               .set_odm_combine = optc32_set_odm_combine,
-               .get_odm_combine_segments = optc32_get_odm_combine_segments,
-               .set_h_timing_div_manual_mode = optc32_set_h_timing_div_manual_mode,
-               .get_optc_source = optc2_get_optc_source,
-               .set_out_mux = optc3_set_out_mux,
-               .set_drr_trigger_window = optc3_set_drr_trigger_window,
-               .set_vtotal_change_limit = optc3_set_vtotal_change_limit,
-               .set_gsl = optc2_set_gsl,
-               .set_gsl_source_select = optc2_set_gsl_source_select,
-               .set_vtg_params = optc1_set_vtg_params,
-               .program_manual_trigger = optc2_program_manual_trigger,
-               .setup_manual_trigger = optc2_setup_manual_trigger,
-               .get_hw_timing = optc1_get_hw_timing,
-};
-
-void dcn32_timing_generator_init(struct optc *optc1)
-{
-       optc1->base.funcs = &dcn32_tg_funcs;
-
-       optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
-       optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
-
-       optc1->min_h_blank = 32;
-       optc1->min_v_blank = 3;
-       optc1->min_v_blank_interlace = 5;
-       optc1->min_h_sync_width = 4;
-       optc1->min_v_sync_width = 1;
-}
-
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h
deleted file mode 100644 (file)
index 8ce3b17..0000000
+++ /dev/null
@@ -1,187 +0,0 @@
-/*
- * Copyright 2021 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DC_OPTC_DCN32_H__
-#define __DC_OPTC_DCN32_H__
-
-#include "dcn10/dcn10_optc.h"
-
-#define OPTC_COMMON_MASK_SH_LIST_DCN3_2(mask_sh)\
-       SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
-       SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
-       SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
-       SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
-       SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\
-       SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_START_X, mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_END_X, mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_START_Y, mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_END_Y, mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL2, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_X, mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_Y, mask_sh),\
-       SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\
-       SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
-       SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_START, mask_sh),\
-       SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_END, mask_sh),\
-       SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_START, mask_sh),\
-       SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_END, mask_sh),\
-       SF(OTG0_OTG_H_SYNC_A_CNTL, OTG_H_SYNC_A_POL, mask_sh),\
-       SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
-       SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_START, mask_sh),\
-       SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_END, mask_sh),\
-       SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_START, mask_sh),\
-       SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_END, mask_sh),\
-       SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_A_POL, mask_sh),\
-       SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, mask_sh),\
-       SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
-       SF(OTG0_OTG_CONTROL, OTG_START_POINT_CNTL, mask_sh),\
-       SF(OTG0_OTG_CONTROL, OTG_DISABLE_POINT_CNTL, mask_sh),\
-       SF(OTG0_OTG_CONTROL, OTG_FIELD_NUMBER_CNTL, mask_sh),\
-       SF(OTG0_OTG_CONTROL, OTG_OUT_MUX, mask_sh),\
-       SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EN, mask_sh),\
-       SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_LINE_NUM, mask_sh),\
-       SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_POLARITY, mask_sh),\
-       SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EYE_FLAG_POLARITY, mask_sh),\
-       SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\
-       SF(OTG0_OTG_STEREO_STATUS, OTG_STEREO_CURRENT_EYE, mask_sh),\
-       SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_EN, mask_sh),\
-       SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\
-       SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\
-       SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\
-       SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\
-       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\
-       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\
-       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\
-       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\
-       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MIN_EN, mask_sh),\
-       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\
-       SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\
-       SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\
-       SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\
-       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_SELECT, mask_sh),\
-       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_PIPE_SELECT, mask_sh),\
-       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_RISING_EDGE_DETECT_CNTL, mask_sh),\
-       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, mask_sh),\
-       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_POLARITY_SELECT, mask_sh),\
-       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FREQUENCY_SELECT, mask_sh),\
-       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_DELAY, mask_sh),\
-       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_CLEAR, mask_sh),\
-       SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_EVENT_MASK, mask_sh),\
-       SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_FRAME_COUNT, mask_sh),\
-       SF(OTG0_OTG_STATUS_FRAME_COUNT, OTG_FRAME_COUNT, mask_sh),\
-       SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
-       SF(OTG0_OTG_STATUS, OTG_V_ACTIVE_DISP, mask_sh),\
-       SF(OTG0_OTG_STATUS_POSITION, OTG_HORZ_COUNT, mask_sh),\
-       SF(OTG0_OTG_STATUS_POSITION, OTG_VERT_COUNT, mask_sh),\
-       SF(OTG0_OTG_NOM_VERT_POSITION, OTG_VERT_COUNT_NOM, mask_sh),\
-       SF(OTG0_OTG_M_CONST_DTO0, OTG_M_CONST_DTO_PHASE, mask_sh),\
-       SF(OTG0_OTG_M_CONST_DTO1, OTG_M_CONST_DTO_MODULO, mask_sh),\
-       SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\
-       SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\
-       SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\
-       SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\
-       SF(OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE, mask_sh),\
-       SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_START, mask_sh),\
-       SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_END, mask_sh),\
-       SF(OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_INT_ENABLE, mask_sh),\
-       SF(OTG0_OTG_VERTICAL_INTERRUPT1_POSITION, OTG_VERTICAL_INTERRUPT1_LINE_START, mask_sh),\
-       SF(OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE, mask_sh),\
-       SF(OTG0_OTG_VERTICAL_INTERRUPT2_POSITION, OTG_VERTICAL_INTERRUPT2_LINE_START, mask_sh),\
-       SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\
-       SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\
-       SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\
-       SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\
-       SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\
-       SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
-       SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
-       SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
-       SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, mask_sh),\
-       SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, mask_sh),\
-       SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_AUTO_FORCE_VSYNC_MODE, mask_sh),\
-       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL0_EN, mask_sh),\
-       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL1_EN, mask_sh),\
-       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL2_EN, mask_sh),\
-       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_EN, mask_sh),\
-       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_FORCE_DELAY, mask_sh),\
-       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\
-       SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\
-       SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\
-       SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
-       SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\
-       SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\
-       SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\
-       SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_START, mask_sh),\
-       SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_END, mask_sh),\
-       SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_START, mask_sh),\
-       SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_END, mask_sh),\
-       SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_START, mask_sh),\
-       SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\
-       SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\
-       SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\
-       SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\
-       SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\
-       SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\
-       SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh),\
-       SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\
-       SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\
-       SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \
-       SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\
-       SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\
-       SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, mask_sh), \
-       SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, mask_sh), \
-       SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, mask_sh), \
-       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_MODE, mask_sh), \
-       SF(OTG0_OTG_GSL_CONTROL, OTG_MASTER_UPDATE_LOCK_GSL_EN, mask_sh), \
-       SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_X, mask_sh), \
-       SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_LINE_NUM, mask_sh),\
-       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG0_SRC_SEL, mask_sh),\
-       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG1_SRC_SEL, mask_sh),\
-       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG2_SRC_SEL, mask_sh),\
-       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG3_SRC_SEL, mask_sh),\
-       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, mask_sh),\
-       SF(ODM0_OPTC_MEMORY_CONFIG, OPTC_MEM_SEL, mask_sh),\
-       SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, mask_sh),\
-       SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\
-       SF(ODM0_OPTC_BYTES_PER_PIXEL, OPTC_DSC_BYTES_PER_PIXEL, mask_sh),\
-       SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, mask_sh),\
-       SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_SEGMENT_WIDTH, mask_sh),\
-       SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_START_X, mask_sh),\
-       SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_END_X, mask_sh),\
-       SF(OTG0_OTG_DRR_V_TOTAL_CHANGE, OTG_DRR_V_TOTAL_CHANGE_LIMIT, mask_sh),\
-       SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\
-       SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE_MANUAL, mask_sh),\
-       SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh),\
-       SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh)
-
-void dcn32_timing_generator_init(struct optc *optc1);
-void optc32_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode);
-void optc32_get_odm_combine_segments(struct timing_generator *tg, int *odm_combine_segments);
-void optc32_set_odm_bypass(struct timing_generator *optc,
-               const struct dc_crtc_timing *dc_crtc_timing);
-
-#endif /* __DC_OPTC_DCN32_H__ */
index 85a307babab9e2f9ad631dc311ae69ced5de238f..fa7ec82ae5f58bc2d5ff2476e3c305467073c131 100644 (file)
@@ -11,7 +11,7 @@
 # Makefile for DCN35.
 
 DCN35 = dcn35_init.o dcn35_dio_stream_encoder.o \
-       dcn35_dio_link_encoder.o dcn35_dccg.o dcn35_optc.o \
+       dcn35_dio_link_encoder.o dcn35_dccg.o \
        dcn35_hubp.o dcn35_hubbub.o \
        dcn35_mmhubbub.o dcn35_opp.o dcn35_dpp.o dcn35_pg_cntl.o dcn35_dwb.o
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c
deleted file mode 100644 (file)
index a4a39f1..0000000
+++ /dev/null
@@ -1,290 +0,0 @@
-/* SPDX-License-Identifier: MIT */
-/*
- * Copyright 2023 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dcn35_optc.h"
-
-#include "dcn30/dcn30_optc.h"
-#include "dcn31/dcn31_optc.h"
-#include "dcn32/dcn32_optc.h"
-#include "reg_helper.h"
-#include "dc.h"
-#include "dcn_calc_math.h"
-
-#define REG(reg)\
-       optc1->tg_regs->reg
-
-#define CTX \
-       optc1->base.ctx
-
-#undef FN
-#define FN(reg_name, field_name) \
-       optc1->tg_shift->field_name, optc1->tg_mask->field_name
-
-/**
- * optc35_set_odm_combine() - Enable CRTC - call ASIC Control Object to enable Timing generator.
- *
- * @optc: Output Pipe Timing Combine instance reference.
- * @opp_id: Output Plane Processor instance ID.
- * @opp_cnt: Output Plane Processor count.
- * @timing: Timing parameters used to configure DCN blocks.
- *
- * Return: void.
- */
-static void optc35_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
-               struct dc_crtc_timing *timing)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-       uint32_t memory_mask = 0;
-       int h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right;
-       int mpcc_hactive = h_active / opp_cnt;
-       /* Each memory instance is 2048x(314x2) bits to support half line of 4096 */
-       int odm_mem_count = (h_active + 2047) / 2048;
-
-       /*
-        * display <= 4k : 2 memories + 2 pipes
-        * 4k < display <= 8k : 4 memories + 2 pipes
-        * 8k < display <= 12k : 6 memories + 4 pipes
-        */
-       if (opp_cnt == 4) {
-               if (odm_mem_count <= 2)
-                       memory_mask = 0x3;
-               else if (odm_mem_count <= 4)
-                       memory_mask = 0xf;
-               else
-                       memory_mask = 0x3f;
-       } else {
-               if (odm_mem_count <= 2)
-                       memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2);
-               else if (odm_mem_count <= 4)
-                       memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);
-               else
-                       memory_mask = 0x77;
-       }
-
-       REG_SET(OPTC_MEMORY_CONFIG, 0,
-               OPTC_MEM_SEL, memory_mask);
-
-       if (opp_cnt == 2) {
-               REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
-                               OPTC_NUM_OF_INPUT_SEGMENT, 1,
-                               OPTC_SEG0_SRC_SEL, opp_id[0],
-                               OPTC_SEG1_SRC_SEL, opp_id[1]);
-       } else if (opp_cnt == 4) {
-               REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
-                               OPTC_NUM_OF_INPUT_SEGMENT, 3,
-                               OPTC_SEG0_SRC_SEL, opp_id[0],
-                               OPTC_SEG1_SRC_SEL, opp_id[1],
-                               OPTC_SEG2_SRC_SEL, opp_id[2],
-                               OPTC_SEG3_SRC_SEL, opp_id[3]);
-       }
-
-       REG_UPDATE(OPTC_WIDTH_CONTROL,
-                       OPTC_SEGMENT_WIDTH, mpcc_hactive);
-
-       REG_UPDATE(OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, opp_cnt - 1);
-       optc1->opp_count = opp_cnt;
-}
-
-static bool optc35_enable_crtc(struct timing_generator *optc)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       /* opp instance for OTG, 1 to 1 mapping and odm will adjust */
-       REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
-                       OPTC_SEG0_SRC_SEL, optc->inst);
-
-       /* VTG enable first is for HW workaround */
-       REG_UPDATE(CONTROL,
-                       VTG0_ENABLE, 1);
-
-       REG_SEQ_START();
-
-       /* Enable CRTC */
-       REG_UPDATE_2(OTG_CONTROL,
-                       OTG_DISABLE_POINT_CNTL, 2,
-                       OTG_MASTER_EN, 1);
-
-       REG_SEQ_SUBMIT();
-       REG_SEQ_WAIT_DONE();
-
-       return true;
-}
-
-/* disable_crtc */
-static bool optc35_disable_crtc(struct timing_generator *optc)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       /* disable otg request until end of the first line
-        * in the vertical blank region
-        */
-       REG_UPDATE(OTG_CONTROL,
-                       OTG_MASTER_EN, 0);
-
-       REG_UPDATE(CONTROL,
-                       VTG0_ENABLE, 0);
-
-       /* CRTC disabled, so disable  clock. */
-       REG_WAIT(OTG_CLOCK_CONTROL,
-                       OTG_BUSY, 0,
-                       1, 100000);
-       optc1_clear_optc_underflow(optc);
-
-       return true;
-}
-
-static void optc35_phantom_crtc_post_enable(struct timing_generator *optc)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       /* Disable immediately. */
-       REG_UPDATE_2(OTG_CONTROL, OTG_DISABLE_POINT_CNTL, 0, OTG_MASTER_EN, 0);
-
-       /* CRTC disabled, so disable  clock. */
-       REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 100000);
-}
-
-static bool optc35_configure_crc(struct timing_generator *optc,
-                                const struct crc_params *params)
-{
-       struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-       if (!optc1_is_tg_enabled(optc))
-               return false;
-       REG_WRITE(OTG_CRC_CNTL, 0);
-       if (!params->enable)
-               return true;
-       REG_UPDATE_2(OTG_CRC0_WINDOWA_X_CONTROL,
-                       OTG_CRC0_WINDOWA_X_START, params->windowa_x_start,
-                       OTG_CRC0_WINDOWA_X_END, params->windowa_x_end);
-       REG_UPDATE_2(OTG_CRC0_WINDOWA_Y_CONTROL,
-                       OTG_CRC0_WINDOWA_Y_START, params->windowa_y_start,
-                       OTG_CRC0_WINDOWA_Y_END, params->windowa_y_end);
-       REG_UPDATE_2(OTG_CRC0_WINDOWB_X_CONTROL,
-                       OTG_CRC0_WINDOWB_X_START, params->windowb_x_start,
-                       OTG_CRC0_WINDOWB_X_END, params->windowb_x_end);
-       REG_UPDATE_2(OTG_CRC0_WINDOWB_Y_CONTROL,
-                       OTG_CRC0_WINDOWB_Y_START, params->windowb_y_start,
-                       OTG_CRC0_WINDOWB_Y_END, params->windowb_y_end);
-       if (optc1->base.ctx->dc->debug.otg_crc_db && optc1->tg_mask->OTG_CRC_WINDOW_DB_EN != 0) {
-               REG_UPDATE_4(OTG_CRC_CNTL,
-                               OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0,
-                               OTG_CRC0_SELECT, params->selection,
-                               OTG_CRC_EN, 1,
-                               OTG_CRC_WINDOW_DB_EN, 1);
-       } else
-               REG_UPDATE_3(OTG_CRC_CNTL,
-                               OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0,
-                               OTG_CRC0_SELECT, params->selection,
-                               OTG_CRC_EN, 1);
-       return true;
-}
-
-static struct timing_generator_funcs dcn35_tg_funcs = {
-               .validate_timing = optc1_validate_timing,
-               .program_timing = optc1_program_timing,
-               .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
-               .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
-               .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
-               .program_global_sync = optc1_program_global_sync,
-               .enable_crtc = optc35_enable_crtc,
-               .disable_crtc = optc35_disable_crtc,
-               .immediate_disable_crtc = optc31_immediate_disable_crtc,
-               .phantom_crtc_post_enable = optc35_phantom_crtc_post_enable,
-               /* used by enable_timing_synchronization. Not need for FPGA */
-               .is_counter_moving = optc1_is_counter_moving,
-               .get_position = optc1_get_position,
-               .get_frame_count = optc1_get_vblank_counter,
-               .get_scanoutpos = optc1_get_crtc_scanoutpos,
-               .get_otg_active_size = optc1_get_otg_active_size,
-               .set_early_control = optc1_set_early_control,
-               /* used by enable_timing_synchronization. Not need for FPGA */
-               .wait_for_state = optc1_wait_for_state,
-               .set_blank_color = optc3_program_blank_color,
-               .did_triggered_reset_occur = optc1_did_triggered_reset_occur,
-               .triplebuffer_lock = optc3_triplebuffer_lock,
-               .triplebuffer_unlock = optc2_triplebuffer_unlock,
-               .enable_reset_trigger = optc1_enable_reset_trigger,
-               .enable_crtc_reset = optc1_enable_crtc_reset,
-               .disable_reset_trigger = optc1_disable_reset_trigger,
-               .lock = optc3_lock,
-               .unlock = optc1_unlock,
-               .lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,
-               .lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
-               .enable_optc_clock = optc1_enable_optc_clock,
-               .set_drr = optc31_set_drr,
-               .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
-               .set_vtotal_min_max = optc1_set_vtotal_min_max,
-               .set_static_screen_control = optc1_set_static_screen_control,
-               .program_stereo = optc1_program_stereo,
-               .is_stereo_left_eye = optc1_is_stereo_left_eye,
-               .tg_init = optc3_tg_init,
-               .is_tg_enabled = optc1_is_tg_enabled,
-               .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
-               .clear_optc_underflow = optc1_clear_optc_underflow,
-               .setup_global_swap_lock = NULL,
-               .get_crc = optc1_get_crc,
-               .configure_crc = optc35_configure_crc,
-               .set_dsc_config = optc3_set_dsc_config,
-               .get_dsc_status = optc2_get_dsc_status,
-               .set_dwb_source = NULL,
-               .set_odm_bypass = optc32_set_odm_bypass,
-               .set_odm_combine = optc35_set_odm_combine,
-               .get_optc_source = optc2_get_optc_source,
-               .set_h_timing_div_manual_mode = optc32_set_h_timing_div_manual_mode,
-               .set_out_mux = optc3_set_out_mux,
-               .set_drr_trigger_window = optc3_set_drr_trigger_window,
-               .set_vtotal_change_limit = optc3_set_vtotal_change_limit,
-               .set_gsl = optc2_set_gsl,
-               .set_gsl_source_select = optc2_set_gsl_source_select,
-               .set_vtg_params = optc1_set_vtg_params,
-               .program_manual_trigger = optc2_program_manual_trigger,
-               .setup_manual_trigger = optc2_setup_manual_trigger,
-               .get_hw_timing = optc1_get_hw_timing,
-               .init_odm = optc3_init_odm,
-};
-
-void dcn35_timing_generator_init(struct optc *optc1)
-{
-       optc1->base.funcs = &dcn35_tg_funcs;
-
-       optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
-       optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
-
-       optc1->min_h_blank = 32;
-       optc1->min_v_blank = 3;
-       optc1->min_v_blank_interlace = 5;
-       optc1->min_h_sync_width = 4;
-       optc1->min_v_sync_width = 1;
-
-       dcn35_timing_generator_set_fgcg(
-               optc1, CTX->dc->debug.enable_fine_grain_clock_gating.bits.optc);
-}
-
-void dcn35_timing_generator_set_fgcg(struct optc *optc1, bool enable)
-{
-       REG_UPDATE(OPTC_CLOCK_CONTROL, OPTC_FGCG_REP_DIS, !enable);
-}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.h b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.h
deleted file mode 100644 (file)
index 1f422e4..0000000
+++ /dev/null
@@ -1,74 +0,0 @@
-/* SPDX-License-Identifier: MIT */
-/*
- * Copyright 2023 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DC_OPTC_DCN35_H__
-#define __DC_OPTC_DCN35_H__
-
-#include "dcn10/dcn10_optc.h"
-#include "dcn32/dcn32_optc.h"
-#define OPTC_COMMON_MASK_SH_LIST_DCN3_5(mask_sh)\
-       OPTC_COMMON_MASK_SH_LIST_DCN3_2(mask_sh),\
-       SF(OTG0_OTG_CRC_CNTL, OTG_CRC_WINDOW_DB_EN, mask_sh),\
-       SF(OTG0_OTG_CRC1_DATA_RG, CRC1_R_CR, mask_sh),\
-       SF(OTG0_OTG_CRC1_DATA_RG, CRC1_G_Y, mask_sh),\
-       SF(OTG0_OTG_CRC1_DATA_B,  CRC1_B_CB, mask_sh),\
-       SF(OTG0_OTG_CRC2_DATA_RG, CRC2_R_CR, mask_sh),\
-       SF(OTG0_OTG_CRC2_DATA_RG, CRC2_G_Y, mask_sh),\
-       SF(OTG0_OTG_CRC2_DATA_B,  CRC2_B_CB, mask_sh),\
-       SF(OTG0_OTG_CRC3_DATA_RG, CRC3_R_CR, mask_sh),\
-       SF(OTG0_OTG_CRC3_DATA_RG, CRC3_G_Y, mask_sh),\
-       SF(OTG0_OTG_CRC3_DATA_B,  CRC3_B_CB, mask_sh),\
-       SF(OTG0_OTG_CRC1_WINDOWA_X_CONTROL, OTG_CRC1_WINDOWA_X_START, mask_sh),\
-       SF(OTG0_OTG_CRC1_WINDOWA_X_CONTROL, OTG_CRC1_WINDOWA_X_END, mask_sh),\
-       SF(OTG0_OTG_CRC1_WINDOWA_Y_CONTROL, OTG_CRC1_WINDOWA_Y_START, mask_sh),\
-       SF(OTG0_OTG_CRC1_WINDOWA_Y_CONTROL, OTG_CRC1_WINDOWA_Y_END, mask_sh),\
-       SF(OTG0_OTG_CRC1_WINDOWB_X_CONTROL, OTG_CRC1_WINDOWB_X_START, mask_sh),\
-       SF(OTG0_OTG_CRC1_WINDOWB_X_CONTROL, OTG_CRC1_WINDOWB_X_END, mask_sh),\
-       SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL, OTG_CRC1_WINDOWB_Y_START, mask_sh),\
-       SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL, OTG_CRC1_WINDOWB_Y_END, mask_sh),\
-       SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK, OTG_CRC0_WINDOWA_X_START_READBACK, mask_sh),\
-       SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK, OTG_CRC0_WINDOWA_X_END_READBACK, mask_sh),\
-       SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK, OTG_CRC0_WINDOWA_Y_START_READBACK, mask_sh),\
-       SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK, OTG_CRC0_WINDOWA_Y_END_READBACK, mask_sh),\
-       SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK, OTG_CRC0_WINDOWB_X_START_READBACK, mask_sh),\
-       SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK, OTG_CRC0_WINDOWB_X_END_READBACK, mask_sh),\
-       SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK, OTG_CRC0_WINDOWB_Y_START_READBACK, mask_sh),\
-       SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK, OTG_CRC0_WINDOWB_Y_END_READBACK, mask_sh),\
-       SF(OTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK, OTG_CRC1_WINDOWA_X_START_READBACK, mask_sh),\
-       SF(OTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK, OTG_CRC1_WINDOWA_X_END_READBACK, mask_sh),\
-       SF(OTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK, OTG_CRC1_WINDOWA_Y_START_READBACK, mask_sh),\
-       SF(OTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK, OTG_CRC1_WINDOWA_Y_END_READBACK, mask_sh),\
-       SF(OTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK, OTG_CRC1_WINDOWB_X_START_READBACK, mask_sh),\
-       SF(OTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK, OTG_CRC1_WINDOWB_X_END_READBACK, mask_sh),\
-       SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK, OTG_CRC1_WINDOWB_Y_START_READBACK, mask_sh),\
-       SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK, OTG_CRC1_WINDOWB_Y_END_READBACK, mask_sh),\
-       SF(OPTC_CLOCK_CONTROL, OPTC_FGCG_REP_DIS, mask_sh)
-
-void dcn35_timing_generator_init(struct optc *optc1);
-
-void dcn35_timing_generator_set_fgcg(struct optc *optc1, bool enable);
-
-#endif /* __DC_OPTC_DCN35_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/optc/Makefile b/drivers/gpu/drm/amd/display/dc/optc/Makefile
new file mode 100644 (file)
index 0000000..bb21333
--- /dev/null
@@ -0,0 +1,108 @@
+
+# Copyright 2022 Advanced Micro Devices, Inc.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+# OTHER DEALINGS IN THE SOFTWARE.
+#
+# Makefile for the 'optc' sub-component of DAL.
+#
+
+
+ifdef CONFIG_DRM_AMD_DC_FP
+###############################################################################
+# DCN
+###############################################################################
+
+OPTC_DCN10 = dcn10_optc.o
+
+AMD_DAL_OPTC_DCN10 = $(addprefix $(AMDDALPATH)/dc/optc/dcn10/,$(OPTC_DCN10))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_OPTC_DCN10)
+
+###############################################################################
+
+OPTC_DCN20 = dcn20_optc.o
+
+AMD_DAL_OPTC_DCN20 = $(addprefix $(AMDDALPATH)/dc/optc/dcn20/,$(OPTC_DCN20))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_OPTC_DCN20)
+
+###############################################################################
+
+OPTC_DCN201 = dcn201_optc.o
+
+AMD_DAL_OPTC_DCN201 = $(addprefix $(AMDDALPATH)/dc/optc/dcn201/,$(OPTC_DCN201))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_OPTC_DCN201)
+
+###############################################################################
+
+###############################################################################
+
+###############################################################################
+
+OPTC_DCN30 = dcn30_optc.o
+
+AMD_DAL_OPTC_DCN30 = $(addprefix $(AMDDALPATH)/dc/optc/dcn30/,$(OPTC_DCN30))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_OPTC_DCN30)
+
+###############################################################################
+
+OPTC_DCN301 = dcn301_optc.o
+
+AMD_DAL_OPTC_DCN301 = $(addprefix $(AMDDALPATH)/dc/optc/dcn301/,$(OPTC_DCN301))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_OPTC_DCN301)
+
+###############################################################################
+
+OPTC_DCN31 = dcn31_optc.o
+
+AMD_DAL_OPTC_DCN31 = $(addprefix $(AMDDALPATH)/dc/optc/dcn31/,$(OPTC_DCN31))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_OPTC_DCN31)
+
+###############################################################################
+
+OPTC_DCN314 = dcn314_optc.o
+
+AMD_DAL_OPTC_DCN314 = $(addprefix $(AMDDALPATH)/dc/optc/dcn314/,$(OPTC_DCN314))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_OPTC_DCN314)
+
+###############################################################################
+
+OPTC_DCN32 = dcn32_optc.o
+
+AMD_DAL_OPTC_DCN32 = $(addprefix $(AMDDALPATH)/dc/optc/dcn32/,$(OPTC_DCN32))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_OPTC_DCN32)
+
+###############################################################################
+
+OPTC_DCN35 = dcn35_optc.o
+
+AMD_DAL_OPTC_DCN35 = $(addprefix $(AMDDALPATH)/dc/optc/dcn35/,$(OPTC_DCN35))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_OPTC_DCN35)
+
+###############################################################################
+
+###############################################################################
+endif
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
new file mode 100644 (file)
index 0000000..0e8f4f3
--- /dev/null
@@ -0,0 +1,1621 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+
+#include "reg_helper.h"
+#include "dcn10_optc.h"
+#include "dc.h"
+#include "dc_trace.h"
+
+#define REG(reg)\
+       optc1->tg_regs->reg
+
+#define CTX \
+       optc1->base.ctx
+
+#undef FN
+#define FN(reg_name, field_name) \
+       optc1->tg_shift->field_name, optc1->tg_mask->field_name
+
+#define STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN 0x100
+
+/**
+ * apply_front_porch_workaround() - This is a workaround for a bug that has
+ *                                  existed since R5xx and has not been fixed
+ *                                  keep Front porch at minimum 2 for Interlaced
+ *                                  mode or 1 for progressive.
+ *
+ * @timing: Timing parameters used to configure DCN blocks.
+ */
+static void apply_front_porch_workaround(struct dc_crtc_timing *timing)
+{
+       if (timing->flags.INTERLACE == 1) {
+               if (timing->v_front_porch < 2)
+                       timing->v_front_porch = 2;
+       } else {
+               if (timing->v_front_porch < 1)
+                       timing->v_front_porch = 1;
+       }
+}
+
+void optc1_program_global_sync(
+               struct timing_generator *optc,
+               int vready_offset,
+               int vstartup_start,
+               int vupdate_offset,
+               int vupdate_width)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       optc1->vready_offset = vready_offset;
+       optc1->vstartup_start = vstartup_start;
+       optc1->vupdate_offset = vupdate_offset;
+       optc1->vupdate_width = vupdate_width;
+
+       if (optc1->vstartup_start == 0) {
+               BREAK_TO_DEBUGGER();
+               return;
+       }
+
+       REG_SET(OTG_VSTARTUP_PARAM, 0,
+               VSTARTUP_START, optc1->vstartup_start);
+
+       REG_SET_2(OTG_VUPDATE_PARAM, 0,
+                       VUPDATE_OFFSET, optc1->vupdate_offset,
+                       VUPDATE_WIDTH, optc1->vupdate_width);
+
+       REG_SET(OTG_VREADY_PARAM, 0,
+                       VREADY_OFFSET, optc1->vready_offset);
+}
+
+static void optc1_disable_stereo(struct timing_generator *optc)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       REG_SET(OTG_STEREO_CONTROL, 0,
+               OTG_STEREO_EN, 0);
+
+       REG_SET_2(OTG_3D_STRUCTURE_CONTROL, 0,
+               OTG_3D_STRUCTURE_EN, 0,
+               OTG_3D_STRUCTURE_STEREO_SEL_OVR, 0);
+}
+
+void optc1_setup_vertical_interrupt0(
+               struct timing_generator *optc,
+               uint32_t start_line,
+               uint32_t end_line)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       REG_SET_2(OTG_VERTICAL_INTERRUPT0_POSITION, 0,
+                       OTG_VERTICAL_INTERRUPT0_LINE_START, start_line,
+                       OTG_VERTICAL_INTERRUPT0_LINE_END, end_line);
+}
+
+void optc1_setup_vertical_interrupt1(
+               struct timing_generator *optc,
+               uint32_t start_line)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       REG_SET(OTG_VERTICAL_INTERRUPT1_POSITION, 0,
+                               OTG_VERTICAL_INTERRUPT1_LINE_START, start_line);
+}
+
+void optc1_setup_vertical_interrupt2(
+               struct timing_generator *optc,
+               uint32_t start_line)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       REG_SET(OTG_VERTICAL_INTERRUPT2_POSITION, 0,
+                       OTG_VERTICAL_INTERRUPT2_LINE_START, start_line);
+}
+
+/**
+ * optc1_program_timing() - used by mode timing set Program
+ *                          CRTC Timing Registers - OTG_H_*,
+ *                          OTG_V_*, Pixel repetition.
+ *                          Including SYNC. Call BIOS command table to program Timings.
+ *
+ * @optc: timing_generator instance.
+ * @dc_crtc_timing: Timing parameters used to configure DCN blocks.
+ * @vready_offset: Vready's starting position.
+ * @vstartup_start: Vstartup period.
+ * @vupdate_offset: Vupdate starting position.
+ * @vupdate_width: Vupdate duration.
+ * @signal: DC signal types.
+ * @use_vbios: to program timings from BIOS command table.
+ *
+ */
+void optc1_program_timing(
+       struct timing_generator *optc,
+       const struct dc_crtc_timing *dc_crtc_timing,
+       int vready_offset,
+       int vstartup_start,
+       int vupdate_offset,
+       int vupdate_width,
+       const enum signal_type signal,
+       bool use_vbios)
+{
+       struct dc_crtc_timing patched_crtc_timing;
+       uint32_t asic_blank_end;
+       uint32_t asic_blank_start;
+       uint32_t v_total;
+       uint32_t v_sync_end;
+       uint32_t h_sync_polarity, v_sync_polarity;
+       uint32_t start_point = 0;
+       uint32_t field_num = 0;
+       enum h_timing_div_mode h_div = H_TIMING_NO_DIV;
+
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       optc1->signal = signal;
+       optc1->vready_offset = vready_offset;
+       optc1->vstartup_start = vstartup_start;
+       optc1->vupdate_offset = vupdate_offset;
+       optc1->vupdate_width = vupdate_width;
+       patched_crtc_timing = *dc_crtc_timing;
+       apply_front_porch_workaround(&patched_crtc_timing);
+       optc1->orginal_patched_timing = patched_crtc_timing;
+
+       /* Load horizontal timing */
+
+       /* CRTC_H_TOTAL = vesa.h_total - 1 */
+       REG_SET(OTG_H_TOTAL, 0,
+                       OTG_H_TOTAL,  patched_crtc_timing.h_total - 1);
+
+       /* h_sync_start = 0, h_sync_end = vesa.h_sync_width */
+       REG_UPDATE_2(OTG_H_SYNC_A,
+                       OTG_H_SYNC_A_START, 0,
+                       OTG_H_SYNC_A_END, patched_crtc_timing.h_sync_width);
+
+       /* blank_start = line end - front porch */
+       asic_blank_start = patched_crtc_timing.h_total -
+                       patched_crtc_timing.h_front_porch;
+
+       /* blank_end = blank_start - active */
+       asic_blank_end = asic_blank_start -
+                       patched_crtc_timing.h_border_right -
+                       patched_crtc_timing.h_addressable -
+                       patched_crtc_timing.h_border_left;
+
+       REG_UPDATE_2(OTG_H_BLANK_START_END,
+                       OTG_H_BLANK_START, asic_blank_start,
+                       OTG_H_BLANK_END, asic_blank_end);
+
+       /* h_sync polarity */
+       h_sync_polarity = patched_crtc_timing.flags.HSYNC_POSITIVE_POLARITY ?
+                       0 : 1;
+
+       REG_UPDATE(OTG_H_SYNC_A_CNTL,
+                       OTG_H_SYNC_A_POL, h_sync_polarity);
+
+       v_total = patched_crtc_timing.v_total - 1;
+
+       REG_SET(OTG_V_TOTAL, 0,
+                       OTG_V_TOTAL, v_total);
+
+       /* In case of V_TOTAL_CONTROL is on, make sure OTG_V_TOTAL_MAX and
+        * OTG_V_TOTAL_MIN are equal to V_TOTAL.
+        */
+       optc->funcs->set_vtotal_min_max(optc, v_total, v_total);
+
+       /* v_sync_start = 0, v_sync_end = v_sync_width */
+       v_sync_end = patched_crtc_timing.v_sync_width;
+
+       REG_UPDATE_2(OTG_V_SYNC_A,
+                       OTG_V_SYNC_A_START, 0,
+                       OTG_V_SYNC_A_END, v_sync_end);
+
+       /* blank_start = frame end - front porch */
+       asic_blank_start = patched_crtc_timing.v_total -
+                       patched_crtc_timing.v_front_porch;
+
+       /* blank_end = blank_start - active */
+       asic_blank_end = asic_blank_start -
+                       patched_crtc_timing.v_border_bottom -
+                       patched_crtc_timing.v_addressable -
+                       patched_crtc_timing.v_border_top;
+
+       REG_UPDATE_2(OTG_V_BLANK_START_END,
+                       OTG_V_BLANK_START, asic_blank_start,
+                       OTG_V_BLANK_END, asic_blank_end);
+
+       /* v_sync polarity */
+       v_sync_polarity = patched_crtc_timing.flags.VSYNC_POSITIVE_POLARITY ?
+                       0 : 1;
+
+       REG_UPDATE(OTG_V_SYNC_A_CNTL,
+               OTG_V_SYNC_A_POL, v_sync_polarity);
+
+       if (optc1->signal == SIGNAL_TYPE_DISPLAY_PORT ||
+                       optc1->signal == SIGNAL_TYPE_DISPLAY_PORT_MST ||
+                       optc1->signal == SIGNAL_TYPE_EDP) {
+               start_point = 1;
+               if (patched_crtc_timing.flags.INTERLACE == 1)
+                       field_num = 1;
+       }
+
+       /* Interlace */
+       if (REG(OTG_INTERLACE_CONTROL)) {
+               if (patched_crtc_timing.flags.INTERLACE == 1)
+                       REG_UPDATE(OTG_INTERLACE_CONTROL,
+                                       OTG_INTERLACE_ENABLE, 1);
+               else
+                       REG_UPDATE(OTG_INTERLACE_CONTROL,
+                                       OTG_INTERLACE_ENABLE, 0);
+       }
+
+       /* VTG enable set to 0 first VInit */
+       REG_UPDATE(CONTROL,
+                       VTG0_ENABLE, 0);
+
+       /* original code is using VTG offset to address OTG reg, seems wrong */
+       REG_UPDATE_2(OTG_CONTROL,
+                       OTG_START_POINT_CNTL, start_point,
+                       OTG_FIELD_NUMBER_CNTL, field_num);
+
+       optc->funcs->program_global_sync(optc,
+                       vready_offset,
+                       vstartup_start,
+                       vupdate_offset,
+                       vupdate_width);
+
+       optc->funcs->set_vtg_params(optc, dc_crtc_timing, true);
+
+       /* TODO
+        * patched_crtc_timing.flags.HORZ_COUNT_BY_TWO == 1
+        * program_horz_count_by_2
+        * for DVI 30bpp mode, 0 otherwise
+        * program_horz_count_by_2(optc, &patched_crtc_timing);
+        */
+
+       /* Enable stereo - only when we need to pack 3D frame. Other types
+        * of stereo handled in explicit call
+        */
+
+       if (optc1_is_two_pixels_per_containter(&patched_crtc_timing) || optc1->opp_count == 2)
+               h_div = H_TIMING_DIV_BY2;
+
+       if (REG(OPTC_DATA_FORMAT_CONTROL) && optc1->tg_mask->OPTC_DATA_FORMAT != 0) {
+               uint32_t data_fmt = 0;
+
+               if (patched_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
+                       data_fmt = 1;
+               else if (patched_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
+                       data_fmt = 2;
+
+               REG_UPDATE(OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, data_fmt);
+       }
+
+       if (optc1->tg_mask->OTG_H_TIMING_DIV_MODE != 0) {
+               if (optc1->opp_count == 4)
+                       h_div = H_TIMING_DIV_BY4;
+
+               REG_UPDATE(OTG_H_TIMING_CNTL,
+               OTG_H_TIMING_DIV_MODE, h_div);
+       } else {
+               REG_UPDATE(OTG_H_TIMING_CNTL,
+               OTG_H_TIMING_DIV_BY2, h_div);
+       }
+}
+
+/**
+ * optc1_set_vtg_params - Set Vertical Timing Generator (VTG) parameters
+ *
+ * @optc: timing_generator struct used to extract the optc parameters
+ * @dc_crtc_timing: Timing parameters configured
+ * @program_fp2: Boolean value indicating if FP2 will be programmed or not
+ *
+ * OTG is responsible for generating the global sync signals, including
+ * vertical timing information for each HUBP in the dcfclk domain. Each VTG is
+ * associated with one OTG that provides HUBP with vertical timing information
+ * (i.e., there is 1:1 correspondence between OTG and VTG). This function is
+ * responsible for setting the OTG parameters to the VTG during the pipe
+ * programming.
+ */
+void optc1_set_vtg_params(struct timing_generator *optc,
+               const struct dc_crtc_timing *dc_crtc_timing, bool program_fp2)
+{
+       struct dc_crtc_timing patched_crtc_timing;
+       uint32_t asic_blank_end;
+       uint32_t v_init;
+       uint32_t v_fp2 = 0;
+       int32_t vertical_line_start;
+
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       patched_crtc_timing = *dc_crtc_timing;
+       apply_front_porch_workaround(&patched_crtc_timing);
+
+       /* VCOUNT_INIT is the start of blank */
+       v_init = patched_crtc_timing.v_total - patched_crtc_timing.v_front_porch;
+
+       /* end of blank = v_init - active */
+       asic_blank_end = v_init -
+                       patched_crtc_timing.v_border_bottom -
+                       patched_crtc_timing.v_addressable -
+                       patched_crtc_timing.v_border_top;
+
+       /* if VSTARTUP is before VSYNC, FP2 is the offset, otherwise 0 */
+       vertical_line_start = asic_blank_end - optc1->vstartup_start + 1;
+       if (vertical_line_start < 0)
+               v_fp2 = -vertical_line_start;
+
+       /* Interlace */
+       if (REG(OTG_INTERLACE_CONTROL)) {
+               if (patched_crtc_timing.flags.INTERLACE == 1) {
+                       v_init = v_init / 2;
+                       if ((optc1->vstartup_start/2)*2 > asic_blank_end)
+                               v_fp2 = v_fp2 / 2;
+               }
+       }
+
+       if (program_fp2)
+               REG_UPDATE_2(CONTROL,
+                               VTG0_FP2, v_fp2,
+                               VTG0_VCOUNT_INIT, v_init);
+       else
+               REG_UPDATE(CONTROL, VTG0_VCOUNT_INIT, v_init);
+}
+
+void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       uint32_t blank_data_double_buffer_enable = enable ? 1 : 0;
+
+       REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,
+                       OTG_BLANK_DATA_DOUBLE_BUFFER_EN, blank_data_double_buffer_enable);
+}
+
+/**
+ * optc1_set_timing_double_buffer() - DRR double buffering control
+ *
+ * Sets double buffer point for V_TOTAL, H_TOTAL, VTOTAL_MIN,
+ * VTOTAL_MAX, VTOTAL_MIN_SEL and VTOTAL_MAX_SEL registers.
+ *
+ * @optc: timing_generator instance.
+ * @enable: Enable DRR double buffering control if true, disable otherwise.
+ *
+ * Options: any time,  start of frame, dp start of frame (range timing)
+ */
+void optc1_set_timing_double_buffer(struct timing_generator *optc, bool enable)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+       uint32_t mode = enable ? 2 : 0;
+
+       REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,
+                  OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mode);
+}
+
+/**
+ * optc1_unblank_crtc() - Call ASIC Control Object to UnBlank CRTC.
+ *
+ * @optc: timing_generator instance.
+ */
+static void optc1_unblank_crtc(struct timing_generator *optc)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       REG_UPDATE_2(OTG_BLANK_CONTROL,
+                       OTG_BLANK_DATA_EN, 0,
+                       OTG_BLANK_DE_MODE, 0);
+
+       /* W/A for automated testing
+        * Automated testing will fail underflow test as there
+        * sporadic underflows which occur during the optc blank
+        * sequence.  As a w/a, clear underflow on unblank.
+        * This prevents the failure, but will not mask actual
+        * underflow that affect real use cases.
+        */
+       optc1_clear_optc_underflow(optc);
+}
+
+/**
+ * optc1_blank_crtc() - Call ASIC Control Object to Blank CRTC.
+ *
+ * @optc: timing_generator instance.
+ */
+
+static void optc1_blank_crtc(struct timing_generator *optc)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       REG_UPDATE_2(OTG_BLANK_CONTROL,
+                       OTG_BLANK_DATA_EN, 1,
+                       OTG_BLANK_DE_MODE, 0);
+
+       optc1_set_blank_data_double_buffer(optc, false);
+}
+
+void optc1_set_blank(struct timing_generator *optc,
+               bool enable_blanking)
+{
+       if (enable_blanking)
+               optc1_blank_crtc(optc);
+       else
+               optc1_unblank_crtc(optc);
+}
+
+bool optc1_is_blanked(struct timing_generator *optc)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+       uint32_t blank_en;
+       uint32_t blank_state;
+
+       REG_GET_2(OTG_BLANK_CONTROL,
+                       OTG_BLANK_DATA_EN, &blank_en,
+                       OTG_CURRENT_BLANK_STATE, &blank_state);
+
+       return blank_en && blank_state;
+}
+
+void optc1_enable_optc_clock(struct timing_generator *optc, bool enable)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       if (enable) {
+               REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL,
+                               OPTC_INPUT_CLK_EN, 1,
+                               OPTC_INPUT_CLK_GATE_DIS, 1);
+
+               REG_WAIT(OPTC_INPUT_CLOCK_CONTROL,
+                               OPTC_INPUT_CLK_ON, 1,
+                               1, 1000);
+
+               /* Enable clock */
+               REG_UPDATE_2(OTG_CLOCK_CONTROL,
+                               OTG_CLOCK_EN, 1,
+                               OTG_CLOCK_GATE_DIS, 1);
+               REG_WAIT(OTG_CLOCK_CONTROL,
+                               OTG_CLOCK_ON, 1,
+                               1, 1000);
+       } else  {
+
+               //last chance to clear underflow, otherwise, it will always there due to clock is off.
+               if (optc->funcs->is_optc_underflow_occurred(optc) == true)
+                       optc->funcs->clear_optc_underflow(optc);
+
+               REG_UPDATE_2(OTG_CLOCK_CONTROL,
+                               OTG_CLOCK_GATE_DIS, 0,
+                               OTG_CLOCK_EN, 0);
+
+               REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL,
+                               OPTC_INPUT_CLK_GATE_DIS, 0,
+                               OPTC_INPUT_CLK_EN, 0);
+       }
+}
+
+/**
+ * optc1_enable_crtc() - Enable CRTC - call ASIC Control Object to enable Timing generator.
+ *
+ * @optc: timing_generator instance.
+ */
+static bool optc1_enable_crtc(struct timing_generator *optc)
+{
+       /* TODO FPGA wait for answer
+        * OTG_MASTER_UPDATE_MODE != CRTC_MASTER_UPDATE_MODE
+        * OTG_MASTER_UPDATE_LOCK != CRTC_MASTER_UPDATE_LOCK
+        */
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       /* opp instance for OTG. For DCN1.0, ODM is remoed.
+        * OPP and OPTC should 1:1 mapping
+        */
+       REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
+                       OPTC_SRC_SEL, optc->inst);
+
+       /* VTG enable first is for HW workaround */
+       REG_UPDATE(CONTROL,
+                       VTG0_ENABLE, 1);
+
+       REG_SEQ_START();
+
+       /* Enable CRTC */
+       REG_UPDATE_2(OTG_CONTROL,
+                       OTG_DISABLE_POINT_CNTL, 3,
+                       OTG_MASTER_EN, 1);
+
+       REG_SEQ_SUBMIT();
+       REG_SEQ_WAIT_DONE();
+
+       return true;
+}
+
+/* disable_crtc - call ASIC Control Object to disable Timing generator. */
+bool optc1_disable_crtc(struct timing_generator *optc)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       /* disable otg request until end of the first line
+        * in the vertical blank region
+        */
+       REG_UPDATE_2(OTG_CONTROL,
+                       OTG_DISABLE_POINT_CNTL, 3,
+                       OTG_MASTER_EN, 0);
+
+       REG_UPDATE(CONTROL,
+                       VTG0_ENABLE, 0);
+
+       /* CRTC disabled, so disable  clock. */
+       REG_WAIT(OTG_CLOCK_CONTROL,
+                       OTG_BUSY, 0,
+                       1, 100000);
+
+       return true;
+}
+
+
+void optc1_program_blank_color(
+               struct timing_generator *optc,
+               const struct tg_color *black_color)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       REG_SET_3(OTG_BLACK_COLOR, 0,
+                       OTG_BLACK_COLOR_B_CB, black_color->color_b_cb,
+                       OTG_BLACK_COLOR_G_Y, black_color->color_g_y,
+                       OTG_BLACK_COLOR_R_CR, black_color->color_r_cr);
+}
+
+bool optc1_validate_timing(
+       struct timing_generator *optc,
+       const struct dc_crtc_timing *timing)
+{
+       uint32_t v_blank;
+       uint32_t h_blank;
+       uint32_t min_v_blank;
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       ASSERT(timing != NULL);
+
+       v_blank = (timing->v_total - timing->v_addressable -
+                                       timing->v_border_top - timing->v_border_bottom);
+
+       h_blank = (timing->h_total - timing->h_addressable -
+               timing->h_border_right -
+               timing->h_border_left);
+
+       if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE &&
+               timing->timing_3d_format != TIMING_3D_FORMAT_HW_FRAME_PACKING &&
+               timing->timing_3d_format != TIMING_3D_FORMAT_TOP_AND_BOTTOM &&
+               timing->timing_3d_format != TIMING_3D_FORMAT_SIDE_BY_SIDE &&
+               timing->timing_3d_format != TIMING_3D_FORMAT_FRAME_ALTERNATE &&
+               timing->timing_3d_format != TIMING_3D_FORMAT_INBAND_FA)
+               return false;
+
+       /* Temporarily blocking interlacing mode until it's supported */
+       if (timing->flags.INTERLACE == 1)
+               return false;
+
+       /* Check maximum number of pixels supported by Timing Generator
+        * (Currently will never fail, in order to fail needs display which
+        * needs more than 8192 horizontal and
+        * more than 8192 vertical total pixels)
+        */
+       if (timing->h_total > optc1->max_h_total ||
+               timing->v_total > optc1->max_v_total)
+               return false;
+
+
+       if (h_blank < optc1->min_h_blank)
+               return false;
+
+       if (timing->h_sync_width  < optc1->min_h_sync_width ||
+                timing->v_sync_width  < optc1->min_v_sync_width)
+               return false;
+
+       min_v_blank = timing->flags.INTERLACE?optc1->min_v_blank_interlace:optc1->min_v_blank;
+
+       if (v_blank < min_v_blank)
+               return false;
+
+       return true;
+
+}
+
+/*
+ * get_vblank_counter
+ *
+ * @brief
+ * Get counter for vertical blanks. use register CRTC_STATUS_FRAME_COUNT which
+ * holds the counter of frames.
+ *
+ * @param
+ * struct timing_generator *optc - [in] timing generator which controls the
+ * desired CRTC
+ *
+ * @return
+ * Counter of frames, which should equal to number of vblanks.
+ */
+uint32_t optc1_get_vblank_counter(struct timing_generator *optc)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+       uint32_t frame_count;
+
+       REG_GET(OTG_STATUS_FRAME_COUNT,
+               OTG_FRAME_COUNT, &frame_count);
+
+       return frame_count;
+}
+
+void optc1_lock(struct timing_generator *optc)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       REG_SET(OTG_GLOBAL_CONTROL0, 0,
+                       OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
+       REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
+                       OTG_MASTER_UPDATE_LOCK, 1);
+
+       REG_WAIT(OTG_MASTER_UPDATE_LOCK,
+                       UPDATE_LOCK_STATUS, 1,
+                       1, 10);
+
+       TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, true);
+}
+
+void optc1_unlock(struct timing_generator *optc)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
+                       OTG_MASTER_UPDATE_LOCK, 0);
+
+       TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, false);
+}
+
+void optc1_get_position(struct timing_generator *optc,
+               struct crtc_position *position)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       REG_GET_2(OTG_STATUS_POSITION,
+                       OTG_HORZ_COUNT, &position->horizontal_count,
+                       OTG_VERT_COUNT, &position->vertical_count);
+
+       REG_GET(OTG_NOM_VERT_POSITION,
+                       OTG_VERT_COUNT_NOM, &position->nominal_vcount);
+}
+
+bool optc1_is_counter_moving(struct timing_generator *optc)
+{
+       struct crtc_position position1, position2;
+
+       optc->funcs->get_position(optc, &position1);
+       optc->funcs->get_position(optc, &position2);
+
+       if (position1.horizontal_count == position2.horizontal_count &&
+               position1.vertical_count == position2.vertical_count)
+               return false;
+       else
+               return true;
+}
+
+bool optc1_did_triggered_reset_occur(
+       struct timing_generator *optc)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+       uint32_t occurred_force, occurred_vsync;
+
+       REG_GET(OTG_FORCE_COUNT_NOW_CNTL,
+               OTG_FORCE_COUNT_NOW_OCCURRED, &occurred_force);
+
+       REG_GET(OTG_VERT_SYNC_CONTROL,
+               OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, &occurred_vsync);
+
+       return occurred_vsync != 0 || occurred_force != 0;
+}
+
+void optc1_disable_reset_trigger(struct timing_generator *optc)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       REG_WRITE(OTG_TRIGA_CNTL, 0);
+
+       REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,
+               OTG_FORCE_COUNT_NOW_CLEAR, 1);
+
+       REG_SET(OTG_VERT_SYNC_CONTROL, 0,
+               OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, 1);
+}
+
+void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+       uint32_t falling_edge;
+
+       REG_GET(OTG_V_SYNC_A_CNTL,
+                       OTG_V_SYNC_A_POL, &falling_edge);
+
+       if (falling_edge)
+               REG_SET_3(OTG_TRIGA_CNTL, 0,
+                               /* vsync signal from selected OTG pipe based
+                                * on OTG_TRIG_SOURCE_PIPE_SELECT setting
+                                */
+                               OTG_TRIGA_SOURCE_SELECT, 20,
+                               OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst,
+                               /* always detect falling edge */
+                               OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 1);
+       else
+               REG_SET_3(OTG_TRIGA_CNTL, 0,
+                               /* vsync signal from selected OTG pipe based
+                                * on OTG_TRIG_SOURCE_PIPE_SELECT setting
+                                */
+                               OTG_TRIGA_SOURCE_SELECT, 20,
+                               OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst,
+                               /* always detect rising edge */
+                               OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1);
+
+       REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,
+                       /* force H count to H_TOTAL and V count to V_TOTAL in
+                        * progressive mode and V_TOTAL-1 in interlaced mode
+                        */
+                       OTG_FORCE_COUNT_NOW_MODE, 2);
+}
+
+void optc1_enable_crtc_reset(
+               struct timing_generator *optc,
+               int source_tg_inst,
+               struct crtc_trigger_info *crtc_tp)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+       uint32_t falling_edge = 0;
+       uint32_t rising_edge = 0;
+
+       switch (crtc_tp->event) {
+
+       case CRTC_EVENT_VSYNC_RISING:
+               rising_edge = 1;
+               break;
+
+       case CRTC_EVENT_VSYNC_FALLING:
+               falling_edge = 1;
+               break;
+       }
+
+       REG_SET_4(OTG_TRIGA_CNTL, 0,
+                /* vsync signal from selected OTG pipe based
+                 * on OTG_TRIG_SOURCE_PIPE_SELECT setting
+                 */
+                 OTG_TRIGA_SOURCE_SELECT, 20,
+                 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst,
+                 /* always detect falling edge */
+                 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, rising_edge,
+                 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, falling_edge);
+
+       switch (crtc_tp->delay) {
+       case TRIGGER_DELAY_NEXT_LINE:
+               REG_SET(OTG_VERT_SYNC_CONTROL, 0,
+                               OTG_AUTO_FORCE_VSYNC_MODE, 1);
+               break;
+       case TRIGGER_DELAY_NEXT_PIXEL:
+               REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,
+                       /* force H count to H_TOTAL and V count to V_TOTAL in
+                        * progressive mode and V_TOTAL-1 in interlaced mode
+                        */
+                       OTG_FORCE_COUNT_NOW_MODE, 2);
+               break;
+       }
+}
+
+void optc1_wait_for_state(struct timing_generator *optc,
+               enum crtc_state state)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       switch (state) {
+       case CRTC_STATE_VBLANK:
+               REG_WAIT(OTG_STATUS,
+                               OTG_V_BLANK, 1,
+                               1, 100000); /* 1 vupdate at 10hz */
+               break;
+
+       case CRTC_STATE_VACTIVE:
+               REG_WAIT(OTG_STATUS,
+                               OTG_V_ACTIVE_DISP, 1,
+                               1, 100000); /* 1 vupdate at 10hz */
+               break;
+
+       default:
+               break;
+       }
+}
+
+void optc1_set_early_control(
+       struct timing_generator *optc,
+       uint32_t early_cntl)
+{
+       /* asic design change, do not need this control
+        * empty for share caller logic
+        */
+}
+
+
+void optc1_set_static_screen_control(
+       struct timing_generator *optc,
+       uint32_t event_triggers,
+       uint32_t num_frames)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       // By register spec, it only takes 8 bit value
+       if (num_frames > 0xFF)
+               num_frames = 0xFF;
+
+       /* Bit 8 is no longer applicable in RV for PSR case,
+        * set bit 8 to 0 if given
+        */
+       if ((event_triggers & STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN)
+                       != 0)
+               event_triggers = event_triggers &
+               ~STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN;
+
+       REG_SET_2(OTG_STATIC_SCREEN_CONTROL, 0,
+                       OTG_STATIC_SCREEN_EVENT_MASK, event_triggers,
+                       OTG_STATIC_SCREEN_FRAME_COUNT, num_frames);
+}
+
+static void optc1_setup_manual_trigger(struct timing_generator *optc)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       REG_SET(OTG_GLOBAL_CONTROL2, 0,
+                       MANUAL_FLOW_CONTROL_SEL, optc->inst);
+
+       REG_SET_8(OTG_TRIGA_CNTL, 0,
+                       OTG_TRIGA_SOURCE_SELECT, 22,
+                       OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst,
+                       OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1,
+                       OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 0,
+                       OTG_TRIGA_POLARITY_SELECT, 0,
+                       OTG_TRIGA_FREQUENCY_SELECT, 0,
+                       OTG_TRIGA_DELAY, 0,
+                       OTG_TRIGA_CLEAR, 1);
+}
+
+static void optc1_program_manual_trigger(struct timing_generator *optc)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       REG_SET(OTG_MANUAL_FLOW_CONTROL, 0,
+                       MANUAL_FLOW_CONTROL, 1);
+
+       REG_SET(OTG_MANUAL_FLOW_CONTROL, 0,
+                       MANUAL_FLOW_CONTROL, 0);
+}
+
+/**
+ * optc1_set_drr() - Program dynamic refresh rate registers m_OTGx_OTG_V_TOTAL_*.
+ *
+ * @optc: timing_generator instance.
+ * @params: parameters used for Dynamic Refresh Rate.
+ */
+void optc1_set_drr(
+       struct timing_generator *optc,
+       const struct drr_params *params)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       if (params != NULL &&
+               params->vertical_total_max > 0 &&
+               params->vertical_total_min > 0) {
+
+               if (params->vertical_total_mid != 0) {
+
+                       REG_SET(OTG_V_TOTAL_MID, 0,
+                               OTG_V_TOTAL_MID, params->vertical_total_mid - 1);
+
+                       REG_UPDATE_2(OTG_V_TOTAL_CONTROL,
+                                       OTG_VTOTAL_MID_REPLACING_MAX_EN, 1,
+                                       OTG_VTOTAL_MID_FRAME_NUM,
+                                       (uint8_t)params->vertical_total_mid_frame_num);
+
+               }
+
+               optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1);
+
+               REG_UPDATE_5(OTG_V_TOTAL_CONTROL,
+                               OTG_V_TOTAL_MIN_SEL, 1,
+                               OTG_V_TOTAL_MAX_SEL, 1,
+                               OTG_FORCE_LOCK_ON_EVENT, 0,
+                               OTG_SET_V_TOTAL_MIN_MASK_EN, 0,
+                               OTG_SET_V_TOTAL_MIN_MASK, 0);
+       }
+
+       // Setup manual flow control for EOF via TRIG_A
+       optc->funcs->setup_manual_trigger(optc);
+}
+
+void optc1_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       REG_SET(OTG_V_TOTAL_MAX, 0,
+               OTG_V_TOTAL_MAX, vtotal_max);
+
+       REG_SET(OTG_V_TOTAL_MIN, 0,
+               OTG_V_TOTAL_MIN, vtotal_min);
+}
+
+static void optc1_set_test_pattern(
+       struct timing_generator *optc,
+       /* TODO: replace 'controller_dp_test_pattern' by 'test_pattern_mode'
+        * because this is not DP-specific (which is probably somewhere in DP
+        * encoder) */
+       enum controller_dp_test_pattern test_pattern,
+       enum dc_color_depth color_depth)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+       enum test_pattern_color_format bit_depth;
+       enum test_pattern_dyn_range dyn_range;
+       enum test_pattern_mode mode;
+       uint32_t pattern_mask;
+       uint32_t pattern_data;
+       /* color ramp generator mixes 16-bits color */
+       uint32_t src_bpc = 16;
+       /* requested bpc */
+       uint32_t dst_bpc;
+       uint32_t index;
+       /* RGB values of the color bars.
+        * Produce two RGB colors: RGB0 - white (all Fs)
+        * and RGB1 - black (all 0s)
+        * (three RGB components for two colors)
+        */
+       uint16_t src_color[6] = {0xFFFF, 0xFFFF, 0xFFFF, 0x0000,
+                                               0x0000, 0x0000};
+       /* dest color (converted to the specified color format) */
+       uint16_t dst_color[6];
+       uint32_t inc_base;
+
+       /* translate to bit depth */
+       switch (color_depth) {
+       case COLOR_DEPTH_666:
+               bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_6;
+       break;
+       case COLOR_DEPTH_888:
+               bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8;
+       break;
+       case COLOR_DEPTH_101010:
+               bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_10;
+       break;
+       case COLOR_DEPTH_121212:
+               bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_12;
+       break;
+       default:
+               bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8;
+       break;
+       }
+
+       switch (test_pattern) {
+       case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES:
+       case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA:
+       {
+               dyn_range = (test_pattern ==
+                               CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA ?
+                               TEST_PATTERN_DYN_RANGE_CEA :
+                               TEST_PATTERN_DYN_RANGE_VESA);
+               mode = TEST_PATTERN_MODE_COLORSQUARES_RGB;
+
+               REG_UPDATE_2(OTG_TEST_PATTERN_PARAMETERS,
+                               OTG_TEST_PATTERN_VRES, 6,
+                               OTG_TEST_PATTERN_HRES, 6);
+
+               REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL,
+                               OTG_TEST_PATTERN_EN, 1,
+                               OTG_TEST_PATTERN_MODE, mode,
+                               OTG_TEST_PATTERN_DYNAMIC_RANGE, dyn_range,
+                               OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth);
+       }
+       break;
+
+       case CONTROLLER_DP_TEST_PATTERN_VERTICALBARS:
+       case CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS:
+       {
+               mode = (test_pattern ==
+                       CONTROLLER_DP_TEST_PATTERN_VERTICALBARS ?
+                       TEST_PATTERN_MODE_VERTICALBARS :
+                       TEST_PATTERN_MODE_HORIZONTALBARS);
+
+               switch (bit_depth) {
+               case TEST_PATTERN_COLOR_FORMAT_BPC_6:
+                       dst_bpc = 6;
+               break;
+               case TEST_PATTERN_COLOR_FORMAT_BPC_8:
+                       dst_bpc = 8;
+               break;
+               case TEST_PATTERN_COLOR_FORMAT_BPC_10:
+                       dst_bpc = 10;
+               break;
+               default:
+                       dst_bpc = 8;
+               break;
+               }
+
+               /* adjust color to the required colorFormat */
+               for (index = 0; index < 6; index++) {
+                       /* dst = 2^dstBpc * src / 2^srcBpc = src >>
+                        * (srcBpc - dstBpc);
+                        */
+                       dst_color[index] =
+                               src_color[index] >> (src_bpc - dst_bpc);
+               /* CRTC_TEST_PATTERN_DATA has 16 bits,
+                * lowest 6 are hardwired to ZERO
+                * color bits should be left aligned to MSB
+                * XXXXXXXXXX000000 for 10 bit,
+                * XXXXXXXX00000000 for 8 bit and XXXXXX0000000000 for 6
+                */
+                       dst_color[index] <<= (16 - dst_bpc);
+               }
+
+               REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0);
+
+               /* We have to write the mask before data, similar to pipeline.
+                * For example, for 8 bpc, if we want RGB0 to be magenta,
+                * and RGB1 to be cyan,
+                * we need to make 7 writes:
+                * MASK   DATA
+                * 000001 00000000 00000000                     set mask to R0
+                * 000010 11111111 00000000     R0 255, 0xFF00, set mask to G0
+                * 000100 00000000 00000000     G0 0,   0x0000, set mask to B0
+                * 001000 11111111 00000000     B0 255, 0xFF00, set mask to R1
+                * 010000 00000000 00000000     R1 0,   0x0000, set mask to G1
+                * 100000 11111111 00000000     G1 255, 0xFF00, set mask to B1
+                * 100000 11111111 00000000     B1 255, 0xFF00
+                *
+                * we will make a loop of 6 in which we prepare the mask,
+                * then write, then prepare the color for next write.
+                * first iteration will write mask only,
+                * but each next iteration color prepared in
+                * previous iteration will be written within new mask,
+                * the last component will written separately,
+                * mask is not changing between 6th and 7th write
+                * and color will be prepared by last iteration
+                */
+
+               /* write color, color values mask in CRTC_TEST_PATTERN_MASK
+                * is B1, G1, R1, B0, G0, R0
+                */
+               pattern_data = 0;
+               for (index = 0; index < 6; index++) {
+                       /* prepare color mask, first write PATTERN_DATA
+                        * will have all zeros
+                        */
+                       pattern_mask = (1 << index);
+
+                       /* write color component */
+                       REG_SET_2(OTG_TEST_PATTERN_COLOR, 0,
+                                       OTG_TEST_PATTERN_MASK, pattern_mask,
+                                       OTG_TEST_PATTERN_DATA, pattern_data);
+
+                       /* prepare next color component,
+                        * will be written in the next iteration
+                        */
+                       pattern_data = dst_color[index];
+               }
+               /* write last color component,
+                * it's been already prepared in the loop
+                */
+               REG_SET_2(OTG_TEST_PATTERN_COLOR, 0,
+                               OTG_TEST_PATTERN_MASK, pattern_mask,
+                               OTG_TEST_PATTERN_DATA, pattern_data);
+
+               /* enable test pattern */
+               REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL,
+                               OTG_TEST_PATTERN_EN, 1,
+                               OTG_TEST_PATTERN_MODE, mode,
+                               OTG_TEST_PATTERN_DYNAMIC_RANGE, 0,
+                               OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth);
+       }
+       break;
+
+       case CONTROLLER_DP_TEST_PATTERN_COLORRAMP:
+       {
+               mode = (bit_depth ==
+                       TEST_PATTERN_COLOR_FORMAT_BPC_10 ?
+                       TEST_PATTERN_MODE_DUALRAMP_RGB :
+                       TEST_PATTERN_MODE_SINGLERAMP_RGB);
+
+               switch (bit_depth) {
+               case TEST_PATTERN_COLOR_FORMAT_BPC_6:
+                       dst_bpc = 6;
+               break;
+               case TEST_PATTERN_COLOR_FORMAT_BPC_8:
+                       dst_bpc = 8;
+               break;
+               case TEST_PATTERN_COLOR_FORMAT_BPC_10:
+                       dst_bpc = 10;
+               break;
+               default:
+                       dst_bpc = 8;
+               break;
+               }
+
+               /* increment for the first ramp for one color gradation
+                * 1 gradation for 6-bit color is 2^10
+                * gradations in 16-bit color
+                */
+               inc_base = (src_bpc - dst_bpc);
+
+               switch (bit_depth) {
+               case TEST_PATTERN_COLOR_FORMAT_BPC_6:
+               {
+                       REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS,
+                                       OTG_TEST_PATTERN_INC0, inc_base,
+                                       OTG_TEST_PATTERN_INC1, 0,
+                                       OTG_TEST_PATTERN_HRES, 6,
+                                       OTG_TEST_PATTERN_VRES, 6,
+                                       OTG_TEST_PATTERN_RAMP0_OFFSET, 0);
+               }
+               break;
+               case TEST_PATTERN_COLOR_FORMAT_BPC_8:
+               {
+                       REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS,
+                                       OTG_TEST_PATTERN_INC0, inc_base,
+                                       OTG_TEST_PATTERN_INC1, 0,
+                                       OTG_TEST_PATTERN_HRES, 8,
+                                       OTG_TEST_PATTERN_VRES, 6,
+                                       OTG_TEST_PATTERN_RAMP0_OFFSET, 0);
+               }
+               break;
+               case TEST_PATTERN_COLOR_FORMAT_BPC_10:
+               {
+                       REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS,
+                                       OTG_TEST_PATTERN_INC0, inc_base,
+                                       OTG_TEST_PATTERN_INC1, inc_base + 2,
+                                       OTG_TEST_PATTERN_HRES, 8,
+                                       OTG_TEST_PATTERN_VRES, 5,
+                                       OTG_TEST_PATTERN_RAMP0_OFFSET, 384 << 6);
+               }
+               break;
+               default:
+               break;
+               }
+
+               REG_WRITE(OTG_TEST_PATTERN_COLOR, 0);
+
+               /* enable test pattern */
+               REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0);
+
+               REG_SET_4(OTG_TEST_PATTERN_CONTROL, 0,
+                               OTG_TEST_PATTERN_EN, 1,
+                               OTG_TEST_PATTERN_MODE, mode,
+                               OTG_TEST_PATTERN_DYNAMIC_RANGE, 0,
+                               OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth);
+       }
+       break;
+       case CONTROLLER_DP_TEST_PATTERN_VIDEOMODE:
+       {
+               REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0);
+               REG_WRITE(OTG_TEST_PATTERN_COLOR, 0);
+               REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0);
+       }
+       break;
+       default:
+               break;
+
+       }
+}
+
+void optc1_get_crtc_scanoutpos(
+       struct timing_generator *optc,
+       uint32_t *v_blank_start,
+       uint32_t *v_blank_end,
+       uint32_t *h_position,
+       uint32_t *v_position)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+       struct crtc_position position;
+
+       REG_GET_2(OTG_V_BLANK_START_END,
+                       OTG_V_BLANK_START, v_blank_start,
+                       OTG_V_BLANK_END, v_blank_end);
+
+       optc1_get_position(optc, &position);
+
+       *h_position = position.horizontal_count;
+       *v_position = position.vertical_count;
+}
+
+static void optc1_enable_stereo(struct timing_generator *optc,
+       const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       if (flags) {
+               uint32_t stereo_en;
+               stereo_en = flags->FRAME_PACKED == 0 ? 1 : 0;
+
+               if (flags->PROGRAM_STEREO)
+                       REG_UPDATE_3(OTG_STEREO_CONTROL,
+                               OTG_STEREO_EN, stereo_en,
+                               OTG_STEREO_SYNC_OUTPUT_LINE_NUM, 0,
+                               OTG_STEREO_SYNC_OUTPUT_POLARITY, flags->RIGHT_EYE_POLARITY == 0 ? 0 : 1);
+
+               if (flags->PROGRAM_POLARITY)
+                       REG_UPDATE(OTG_STEREO_CONTROL,
+                               OTG_STEREO_EYE_FLAG_POLARITY,
+                               flags->RIGHT_EYE_POLARITY == 0 ? 0 : 1);
+
+               if (flags->DISABLE_STEREO_DP_SYNC)
+                       REG_UPDATE(OTG_STEREO_CONTROL,
+                               OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, 1);
+
+               if (flags->PROGRAM_STEREO)
+                       REG_UPDATE_2(OTG_3D_STRUCTURE_CONTROL,
+                               OTG_3D_STRUCTURE_EN, flags->FRAME_PACKED,
+                               OTG_3D_STRUCTURE_STEREO_SEL_OVR, flags->FRAME_PACKED);
+
+       }
+}
+
+void optc1_program_stereo(struct timing_generator *optc,
+       const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags)
+{
+       if (flags->PROGRAM_STEREO)
+               optc1_enable_stereo(optc, timing, flags);
+       else
+               optc1_disable_stereo(optc);
+}
+
+
+bool optc1_is_stereo_left_eye(struct timing_generator *optc)
+{
+       bool ret = false;
+       uint32_t left_eye = 0;
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       REG_GET(OTG_STEREO_STATUS,
+               OTG_STEREO_CURRENT_EYE, &left_eye);
+       if (left_eye == 1)
+               ret = true;
+       else
+               ret = false;
+
+       return ret;
+}
+
+bool optc1_get_hw_timing(struct timing_generator *tg,
+               struct dc_crtc_timing *hw_crtc_timing)
+{
+       struct dcn_otg_state s = {0};
+
+       if (tg == NULL || hw_crtc_timing == NULL)
+               return false;
+
+       optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s);
+
+       hw_crtc_timing->h_total = s.h_total + 1;
+       hw_crtc_timing->h_addressable = s.h_total - ((s.h_total - s.h_blank_start) + s.h_blank_end);
+       hw_crtc_timing->h_front_porch = s.h_total + 1 - s.h_blank_start;
+       hw_crtc_timing->h_sync_width = s.h_sync_a_end - s.h_sync_a_start;
+
+       hw_crtc_timing->v_total = s.v_total + 1;
+       hw_crtc_timing->v_addressable = s.v_total - ((s.v_total - s.v_blank_start) + s.v_blank_end);
+       hw_crtc_timing->v_front_porch = s.v_total + 1 - s.v_blank_start;
+       hw_crtc_timing->v_sync_width = s.v_sync_a_end - s.v_sync_a_start;
+
+       return true;
+}
+
+
+void optc1_read_otg_state(struct optc *optc1,
+               struct dcn_otg_state *s)
+{
+       REG_GET(OTG_CONTROL,
+                       OTG_MASTER_EN, &s->otg_enabled);
+
+       REG_GET_2(OTG_V_BLANK_START_END,
+                       OTG_V_BLANK_START, &s->v_blank_start,
+                       OTG_V_BLANK_END, &s->v_blank_end);
+
+       REG_GET(OTG_V_SYNC_A_CNTL,
+                       OTG_V_SYNC_A_POL, &s->v_sync_a_pol);
+
+       REG_GET(OTG_V_TOTAL,
+                       OTG_V_TOTAL, &s->v_total);
+
+       REG_GET(OTG_V_TOTAL_MAX,
+                       OTG_V_TOTAL_MAX, &s->v_total_max);
+
+       REG_GET(OTG_V_TOTAL_MIN,
+                       OTG_V_TOTAL_MIN, &s->v_total_min);
+
+       REG_GET(OTG_V_TOTAL_CONTROL,
+                       OTG_V_TOTAL_MAX_SEL, &s->v_total_max_sel);
+
+       REG_GET(OTG_V_TOTAL_CONTROL,
+                       OTG_V_TOTAL_MIN_SEL, &s->v_total_min_sel);
+
+       REG_GET_2(OTG_V_SYNC_A,
+                       OTG_V_SYNC_A_START, &s->v_sync_a_start,
+                       OTG_V_SYNC_A_END, &s->v_sync_a_end);
+
+       REG_GET_2(OTG_H_BLANK_START_END,
+                       OTG_H_BLANK_START, &s->h_blank_start,
+                       OTG_H_BLANK_END, &s->h_blank_end);
+
+       REG_GET_2(OTG_H_SYNC_A,
+                       OTG_H_SYNC_A_START, &s->h_sync_a_start,
+                       OTG_H_SYNC_A_END, &s->h_sync_a_end);
+
+       REG_GET(OTG_H_SYNC_A_CNTL,
+                       OTG_H_SYNC_A_POL, &s->h_sync_a_pol);
+
+       REG_GET(OTG_H_TOTAL,
+                       OTG_H_TOTAL, &s->h_total);
+
+       REG_GET(OPTC_INPUT_GLOBAL_CONTROL,
+                       OPTC_UNDERFLOW_OCCURRED_STATUS, &s->underflow_occurred_status);
+
+       REG_GET(OTG_VERTICAL_INTERRUPT1_CONTROL,
+                       OTG_VERTICAL_INTERRUPT1_INT_ENABLE, &s->vertical_interrupt1_en);
+
+       REG_GET(OTG_VERTICAL_INTERRUPT1_POSITION,
+                               OTG_VERTICAL_INTERRUPT1_LINE_START, &s->vertical_interrupt1_line);
+
+       REG_GET(OTG_VERTICAL_INTERRUPT2_CONTROL,
+                       OTG_VERTICAL_INTERRUPT2_INT_ENABLE, &s->vertical_interrupt2_en);
+
+       REG_GET(OTG_VERTICAL_INTERRUPT2_POSITION,
+                       OTG_VERTICAL_INTERRUPT2_LINE_START, &s->vertical_interrupt2_line);
+}
+
+bool optc1_get_otg_active_size(struct timing_generator *optc,
+               uint32_t *otg_active_width,
+               uint32_t *otg_active_height)
+{
+       uint32_t otg_enabled;
+       uint32_t v_blank_start;
+       uint32_t v_blank_end;
+       uint32_t h_blank_start;
+       uint32_t h_blank_end;
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+
+       REG_GET(OTG_CONTROL,
+                       OTG_MASTER_EN, &otg_enabled);
+
+       if (otg_enabled == 0)
+               return false;
+
+       REG_GET_2(OTG_V_BLANK_START_END,
+                       OTG_V_BLANK_START, &v_blank_start,
+                       OTG_V_BLANK_END, &v_blank_end);
+
+       REG_GET_2(OTG_H_BLANK_START_END,
+                       OTG_H_BLANK_START, &h_blank_start,
+                       OTG_H_BLANK_END, &h_blank_end);
+
+       *otg_active_width = v_blank_start - v_blank_end;
+       *otg_active_height = h_blank_start - h_blank_end;
+       return true;
+}
+
+void optc1_clear_optc_underflow(struct timing_generator *optc)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       REG_UPDATE(OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, 1);
+}
+
+void optc1_tg_init(struct timing_generator *optc)
+{
+       optc1_set_blank_data_double_buffer(optc, true);
+       optc1_set_timing_double_buffer(optc, true);
+       optc1_clear_optc_underflow(optc);
+}
+
+bool optc1_is_tg_enabled(struct timing_generator *optc)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+       uint32_t otg_enabled = 0;
+
+       REG_GET(OTG_CONTROL, OTG_MASTER_EN, &otg_enabled);
+
+       return (otg_enabled != 0);
+
+}
+
+bool optc1_is_optc_underflow_occurred(struct timing_generator *optc)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+       uint32_t underflow_occurred = 0;
+
+       REG_GET(OPTC_INPUT_GLOBAL_CONTROL,
+                       OPTC_UNDERFLOW_OCCURRED_STATUS,
+                       &underflow_occurred);
+
+       return (underflow_occurred == 1);
+}
+
+bool optc1_configure_crc(struct timing_generator *optc,
+                         const struct crc_params *params)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       /* Cannot configure crc on a CRTC that is disabled */
+       if (!optc1_is_tg_enabled(optc))
+               return false;
+
+       REG_WRITE(OTG_CRC_CNTL, 0);
+
+       if (!params->enable)
+               return true;
+
+       /* Program frame boundaries */
+       /* Window A x axis start and end. */
+       REG_UPDATE_2(OTG_CRC0_WINDOWA_X_CONTROL,
+                       OTG_CRC0_WINDOWA_X_START, params->windowa_x_start,
+                       OTG_CRC0_WINDOWA_X_END, params->windowa_x_end);
+
+       /* Window A y axis start and end. */
+       REG_UPDATE_2(OTG_CRC0_WINDOWA_Y_CONTROL,
+                       OTG_CRC0_WINDOWA_Y_START, params->windowa_y_start,
+                       OTG_CRC0_WINDOWA_Y_END, params->windowa_y_end);
+
+       /* Window B x axis start and end. */
+       REG_UPDATE_2(OTG_CRC0_WINDOWB_X_CONTROL,
+                       OTG_CRC0_WINDOWB_X_START, params->windowb_x_start,
+                       OTG_CRC0_WINDOWB_X_END, params->windowb_x_end);
+
+       /* Window B y axis start and end. */
+       REG_UPDATE_2(OTG_CRC0_WINDOWB_Y_CONTROL,
+                       OTG_CRC0_WINDOWB_Y_START, params->windowb_y_start,
+                       OTG_CRC0_WINDOWB_Y_END, params->windowb_y_end);
+
+       /* Set crc mode and selection, and enable. Only using CRC0*/
+       REG_UPDATE_3(OTG_CRC_CNTL,
+                       OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0,
+                       OTG_CRC0_SELECT, params->selection,
+                       OTG_CRC_EN, 1);
+
+       return true;
+}
+
+/**
+ * optc1_get_crc - Capture CRC result per component
+ *
+ * @optc: timing_generator instance.
+ * @r_cr: 16-bit primary CRC signature for red data.
+ * @g_y: 16-bit primary CRC signature for green data.
+ * @b_cb: 16-bit primary CRC signature for blue data.
+ *
+ * This function reads the CRC signature from the OPTC registers. Notice that
+ * we have three registers to keep the CRC result per color component (RGB).
+ *
+ * Returns:
+ * If CRC is disabled, return false; otherwise, return true, and the CRC
+ * results in the parameters.
+ */
+bool optc1_get_crc(struct timing_generator *optc,
+                  uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)
+{
+       uint32_t field = 0;
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       REG_GET(OTG_CRC_CNTL, OTG_CRC_EN, &field);
+
+       /* Early return if CRC is not enabled for this CRTC */
+       if (!field)
+               return false;
+
+       /* OTG_CRC0_DATA_RG has the CRC16 results for the red and green component */
+       REG_GET_2(OTG_CRC0_DATA_RG,
+                 CRC0_R_CR, r_cr,
+                 CRC0_G_Y, g_y);
+
+       /* OTG_CRC0_DATA_B has the CRC16 results for the blue component */
+       REG_GET(OTG_CRC0_DATA_B,
+               CRC0_B_CB, b_cb);
+
+       return true;
+}
+
+static const struct timing_generator_funcs dcn10_tg_funcs = {
+               .validate_timing = optc1_validate_timing,
+               .program_timing = optc1_program_timing,
+               .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
+               .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
+               .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
+               .program_global_sync = optc1_program_global_sync,
+               .enable_crtc = optc1_enable_crtc,
+               .disable_crtc = optc1_disable_crtc,
+               /* used by enable_timing_synchronization. Not need for FPGA */
+               .is_counter_moving = optc1_is_counter_moving,
+               .get_position = optc1_get_position,
+               .get_frame_count = optc1_get_vblank_counter,
+               .get_scanoutpos = optc1_get_crtc_scanoutpos,
+               .get_otg_active_size = optc1_get_otg_active_size,
+               .set_early_control = optc1_set_early_control,
+               /* used by enable_timing_synchronization. Not need for FPGA */
+               .wait_for_state = optc1_wait_for_state,
+               .set_blank = optc1_set_blank,
+               .is_blanked = optc1_is_blanked,
+               .set_blank_color = optc1_program_blank_color,
+               .did_triggered_reset_occur = optc1_did_triggered_reset_occur,
+               .enable_reset_trigger = optc1_enable_reset_trigger,
+               .enable_crtc_reset = optc1_enable_crtc_reset,
+               .disable_reset_trigger = optc1_disable_reset_trigger,
+               .lock = optc1_lock,
+               .unlock = optc1_unlock,
+               .enable_optc_clock = optc1_enable_optc_clock,
+               .set_drr = optc1_set_drr,
+               .get_last_used_drr_vtotal = NULL,
+               .set_vtotal_min_max = optc1_set_vtotal_min_max,
+               .set_static_screen_control = optc1_set_static_screen_control,
+               .set_test_pattern = optc1_set_test_pattern,
+               .program_stereo = optc1_program_stereo,
+               .is_stereo_left_eye = optc1_is_stereo_left_eye,
+               .set_blank_data_double_buffer = optc1_set_blank_data_double_buffer,
+               .tg_init = optc1_tg_init,
+               .is_tg_enabled = optc1_is_tg_enabled,
+               .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
+               .clear_optc_underflow = optc1_clear_optc_underflow,
+               .get_crc = optc1_get_crc,
+               .configure_crc = optc1_configure_crc,
+               .set_vtg_params = optc1_set_vtg_params,
+               .program_manual_trigger = optc1_program_manual_trigger,
+               .setup_manual_trigger = optc1_setup_manual_trigger,
+               .get_hw_timing = optc1_get_hw_timing,
+};
+
+void dcn10_timing_generator_init(struct optc *optc1)
+{
+       optc1->base.funcs = &dcn10_tg_funcs;
+
+       optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
+       optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
+
+       optc1->min_h_blank = 32;
+       optc1->min_v_blank = 3;
+       optc1->min_v_blank_interlace = 5;
+       optc1->min_h_sync_width = 4;
+       optc1->min_v_sync_width = 1;
+}
+
+/* "Containter" vs. "pixel" is a concept within HW blocks, mostly those closer to the back-end. It works like this:
+ *
+ * - In most of the formats (RGB or YCbCr 4:4:4, 4:2:2 uncompressed and DSC 4:2:2 Simple) pixel rate is the same as
+ *   containter rate.
+ *
+ * - In 4:2:0 (DSC or uncompressed) there are two pixels per container, hence the target container rate has to be
+ *   halved to maintain the correct pixel rate.
+ *
+ * - Unlike 4:2:2 uncompressed, DSC 4:2:2 Native also has two pixels per container (this happens when DSC is applied
+ *   to it) and has to be treated the same as 4:2:0, i.e. target containter rate has to be halved in this case as well.
+ *
+ */
+bool optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
+{
+       bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;
+
+       two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422
+                       && !timing->dsc_cfg.ycbcr422_simple);
+       return two_pix;
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
new file mode 100644 (file)
index 0000000..ab81594
--- /dev/null
@@ -0,0 +1,599 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ *  and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_TIMING_GENERATOR_DCN10_H__
+#define __DC_TIMING_GENERATOR_DCN10_H__
+
+#include "optc.h"
+
+#define DCN10TG_FROM_TG(tg)\
+       container_of(tg, struct optc, base)
+
+#define TG_COMMON_REG_LIST_DCN(inst) \
+       SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
+       SRI(OTG_VUPDATE_PARAM, OTG, inst),\
+       SRI(OTG_VREADY_PARAM, OTG, inst),\
+       SRI(OTG_BLANK_CONTROL, OTG, inst),\
+       SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
+       SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
+       SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
+       SRI(OTG_H_TOTAL, OTG, inst),\
+       SRI(OTG_H_BLANK_START_END, OTG, inst),\
+       SRI(OTG_H_SYNC_A, OTG, inst),\
+       SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\
+       SRI(OTG_H_TIMING_CNTL, OTG, inst),\
+       SRI(OTG_V_TOTAL, OTG, inst),\
+       SRI(OTG_V_BLANK_START_END, OTG, inst),\
+       SRI(OTG_V_SYNC_A, OTG, inst),\
+       SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\
+       SRI(OTG_INTERLACE_CONTROL, OTG, inst),\
+       SRI(OTG_CONTROL, OTG, inst),\
+       SRI(OTG_STEREO_CONTROL, OTG, inst),\
+       SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\
+       SRI(OTG_STEREO_STATUS, OTG, inst),\
+       SRI(OTG_V_TOTAL_MAX, OTG, inst),\
+       SRI(OTG_V_TOTAL_MID, OTG, inst),\
+       SRI(OTG_V_TOTAL_MIN, OTG, inst),\
+       SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\
+       SRI(OTG_TRIGA_CNTL, OTG, inst),\
+       SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\
+       SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\
+       SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\
+       SRI(OTG_STATUS, OTG, inst),\
+       SRI(OTG_STATUS_POSITION, OTG, inst),\
+       SRI(OTG_NOM_VERT_POSITION, OTG, inst),\
+       SRI(OTG_BLACK_COLOR, OTG, inst),\
+       SRI(OTG_CLOCK_CONTROL, OTG, inst),\
+       SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\
+       SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\
+       SRI(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\
+       SRI(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\
+       SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\
+       SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\
+       SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\
+       SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\
+       SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\
+       SRI(CONTROL, VTG, inst),\
+       SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\
+       SRI(OTG_MASTER_UPDATE_MODE, OTG, inst),\
+       SRI(OTG_GSL_CONTROL, OTG, inst),\
+       SRI(OTG_CRC_CNTL, OTG, inst),\
+       SRI(OTG_CRC0_DATA_RG, OTG, inst),\
+       SRI(OTG_CRC0_DATA_B, OTG, inst),\
+       SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\
+       SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\
+       SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\
+       SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\
+       SR(GSL_SOURCE_SELECT),\
+       SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
+       SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst)
+
+#define TG_COMMON_REG_LIST_DCN1_0(inst) \
+       TG_COMMON_REG_LIST_DCN(inst),\
+       SRI(OTG_TEST_PATTERN_PARAMETERS, OTG, inst),\
+       SRI(OTG_TEST_PATTERN_CONTROL, OTG, inst),\
+       SRI(OTG_TEST_PATTERN_COLOR, OTG, inst),\
+       SRI(OTG_MANUAL_FLOW_CONTROL, OTG, inst)
+
+
+struct dcn_optc_registers {
+       uint32_t OTG_GLOBAL_CONTROL1;
+       uint32_t OTG_GLOBAL_CONTROL2;
+       uint32_t OTG_VERT_SYNC_CONTROL;
+       uint32_t OTG_MASTER_UPDATE_MODE;
+       uint32_t OTG_GSL_CONTROL;
+       uint32_t OTG_VSTARTUP_PARAM;
+       uint32_t OTG_VUPDATE_PARAM;
+       uint32_t OTG_VREADY_PARAM;
+       uint32_t OTG_BLANK_CONTROL;
+       uint32_t OTG_MASTER_UPDATE_LOCK;
+       uint32_t OTG_GLOBAL_CONTROL0;
+       uint32_t OTG_DOUBLE_BUFFER_CONTROL;
+       uint32_t OTG_H_TOTAL;
+       uint32_t OTG_H_BLANK_START_END;
+       uint32_t OTG_H_SYNC_A;
+       uint32_t OTG_H_SYNC_A_CNTL;
+       uint32_t OTG_H_TIMING_CNTL;
+       uint32_t OTG_V_TOTAL;
+       uint32_t OTG_V_BLANK_START_END;
+       uint32_t OTG_V_SYNC_A;
+       uint32_t OTG_V_SYNC_A_CNTL;
+       uint32_t OTG_INTERLACE_CONTROL;
+       uint32_t OTG_CONTROL;
+       uint32_t OTG_STEREO_CONTROL;
+       uint32_t OTG_3D_STRUCTURE_CONTROL;
+       uint32_t OTG_STEREO_STATUS;
+       uint32_t OTG_V_TOTAL_MAX;
+       uint32_t OTG_V_TOTAL_MID;
+       uint32_t OTG_V_TOTAL_MIN;
+       uint32_t OTG_V_TOTAL_CONTROL;
+       uint32_t OTG_TRIGA_CNTL;
+       uint32_t OTG_TRIGA_MANUAL_TRIG;
+       uint32_t OTG_MANUAL_FLOW_CONTROL;
+       uint32_t OTG_FORCE_COUNT_NOW_CNTL;
+       uint32_t OTG_STATIC_SCREEN_CONTROL;
+       uint32_t OTG_STATUS_FRAME_COUNT;
+       uint32_t OTG_STATUS;
+       uint32_t OTG_STATUS_POSITION;
+       uint32_t OTG_NOM_VERT_POSITION;
+       uint32_t OTG_BLACK_COLOR;
+       uint32_t OTG_TEST_PATTERN_PARAMETERS;
+       uint32_t OTG_TEST_PATTERN_CONTROL;
+       uint32_t OTG_TEST_PATTERN_COLOR;
+       uint32_t OTG_CLOCK_CONTROL;
+       uint32_t OTG_VERTICAL_INTERRUPT0_CONTROL;
+       uint32_t OTG_VERTICAL_INTERRUPT0_POSITION;
+       uint32_t OTG_VERTICAL_INTERRUPT1_CONTROL;
+       uint32_t OTG_VERTICAL_INTERRUPT1_POSITION;
+       uint32_t OTG_VERTICAL_INTERRUPT2_CONTROL;
+       uint32_t OTG_VERTICAL_INTERRUPT2_POSITION;
+       uint32_t OPTC_INPUT_CLOCK_CONTROL;
+       uint32_t OPTC_DATA_SOURCE_SELECT;
+       uint32_t OPTC_MEMORY_CONFIG;
+       uint32_t OPTC_INPUT_GLOBAL_CONTROL;
+       uint32_t CONTROL;
+       uint32_t OTG_GSL_WINDOW_X;
+       uint32_t OTG_GSL_WINDOW_Y;
+       uint32_t OTG_VUPDATE_KEEPOUT;
+       uint32_t OTG_CRC_CNTL;
+       uint32_t OTG_CRC_CNTL2;
+       uint32_t OTG_CRC0_DATA_RG;
+       uint32_t OTG_CRC0_DATA_B;
+       uint32_t OTG_CRC1_DATA_B;
+       uint32_t OTG_CRC2_DATA_B;
+       uint32_t OTG_CRC3_DATA_B;
+       uint32_t OTG_CRC1_DATA_RG;
+       uint32_t OTG_CRC2_DATA_RG;
+       uint32_t OTG_CRC3_DATA_RG;
+       uint32_t OTG_CRC0_WINDOWA_X_CONTROL;
+       uint32_t OTG_CRC0_WINDOWA_Y_CONTROL;
+       uint32_t OTG_CRC0_WINDOWB_X_CONTROL;
+       uint32_t OTG_CRC0_WINDOWB_Y_CONTROL;
+       uint32_t OTG_CRC1_WINDOWA_X_CONTROL;
+       uint32_t OTG_CRC1_WINDOWA_Y_CONTROL;
+       uint32_t OTG_CRC1_WINDOWB_X_CONTROL;
+       uint32_t OTG_CRC1_WINDOWB_Y_CONTROL;
+       uint32_t GSL_SOURCE_SELECT;
+       uint32_t DWB_SOURCE_SELECT;
+       uint32_t OTG_DSC_START_POSITION;
+       uint32_t OPTC_DATA_FORMAT_CONTROL;
+       uint32_t OPTC_BYTES_PER_PIXEL;
+       uint32_t OPTC_WIDTH_CONTROL;
+       uint32_t OTG_DRR_CONTROL;
+       uint32_t OTG_BLANK_DATA_COLOR;
+       uint32_t OTG_BLANK_DATA_COLOR_EXT;
+       uint32_t OTG_DRR_TRIGGER_WINDOW;
+       uint32_t OTG_M_CONST_DTO0;
+       uint32_t OTG_M_CONST_DTO1;
+       uint32_t OTG_DRR_V_TOTAL_CHANGE;
+       uint32_t OTG_GLOBAL_CONTROL4;
+       uint32_t OTG_CRC0_WINDOWA_X_CONTROL_READBACK;
+       uint32_t OTG_CRC0_WINDOWA_Y_CONTROL_READBACK;
+       uint32_t OTG_CRC0_WINDOWB_X_CONTROL_READBACK;
+       uint32_t OTG_CRC0_WINDOWB_Y_CONTROL_READBACK;
+       uint32_t OTG_CRC1_WINDOWA_X_CONTROL_READBACK;
+       uint32_t OTG_CRC1_WINDOWA_Y_CONTROL_READBACK;
+       uint32_t OTG_CRC1_WINDOWB_X_CONTROL_READBACK;
+       uint32_t OTG_CRC1_WINDOWB_Y_CONTROL_READBACK;
+       uint32_t OPTC_CLOCK_CONTROL;
+};
+
+#define TG_COMMON_MASK_SH_LIST_DCN(mask_sh)\
+       SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
+       SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
+       SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
+       SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
+       SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DATA_EN, mask_sh),\
+       SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DE_MODE, mask_sh),\
+       SF(OTG0_OTG_BLANK_CONTROL, OTG_CURRENT_BLANK_STATE, mask_sh),\
+       SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\
+       SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL0, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\
+       SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\
+       SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_BLANK_DATA_DOUBLE_BUFFER_EN, mask_sh),\
+       SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mask_sh),\
+       SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, mask_sh), \
+       SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, mask_sh), \
+       SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, mask_sh), \
+       SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
+       SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_START, mask_sh),\
+       SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_END, mask_sh),\
+       SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_START, mask_sh),\
+       SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_END, mask_sh),\
+       SF(OTG0_OTG_H_SYNC_A_CNTL, OTG_H_SYNC_A_POL, mask_sh),\
+       SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_BY2, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
+       SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_START, mask_sh),\
+       SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_END, mask_sh),\
+       SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_START, mask_sh),\
+       SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_END, mask_sh),\
+       SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_A_POL, mask_sh),\
+       SF(OTG0_OTG_INTERLACE_CONTROL, OTG_INTERLACE_ENABLE, mask_sh),\
+       SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
+       SF(OTG0_OTG_CONTROL, OTG_START_POINT_CNTL, mask_sh),\
+       SF(OTG0_OTG_CONTROL, OTG_DISABLE_POINT_CNTL, mask_sh),\
+       SF(OTG0_OTG_CONTROL, OTG_FIELD_NUMBER_CNTL, mask_sh),\
+       SF(OTG0_OTG_CONTROL, OTG_CURRENT_MASTER_EN_STATE, mask_sh),\
+       SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EN, mask_sh),\
+       SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_LINE_NUM, mask_sh),\
+       SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_POLARITY, mask_sh),\
+       SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EYE_FLAG_POLARITY, mask_sh),\
+       SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\
+       SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\
+       SF(OTG0_OTG_STEREO_STATUS, OTG_STEREO_CURRENT_EYE, mask_sh),\
+       SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_EN, mask_sh),\
+       SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\
+       SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL_MID, OTG_V_TOTAL_MID, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK_EN, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_FRAME_NUM, mask_sh),\
+       SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\
+       SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\
+       SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\
+       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_SELECT, mask_sh),\
+       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_PIPE_SELECT, mask_sh),\
+       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_RISING_EDGE_DETECT_CNTL, mask_sh),\
+       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, mask_sh),\
+       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_POLARITY_SELECT, mask_sh),\
+       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FREQUENCY_SELECT, mask_sh),\
+       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_DELAY, mask_sh),\
+       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_CLEAR, mask_sh),\
+       SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\
+       SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_EVENT_MASK, mask_sh),\
+       SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_FRAME_COUNT, mask_sh),\
+       SF(OTG0_OTG_STATUS_FRAME_COUNT, OTG_FRAME_COUNT, mask_sh),\
+       SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
+       SF(OTG0_OTG_STATUS, OTG_V_ACTIVE_DISP, mask_sh),\
+       SF(OTG0_OTG_STATUS_POSITION, OTG_HORZ_COUNT, mask_sh),\
+       SF(OTG0_OTG_STATUS_POSITION, OTG_VERT_COUNT, mask_sh),\
+       SF(OTG0_OTG_NOM_VERT_POSITION, OTG_VERT_COUNT_NOM, mask_sh),\
+       SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_B_CB, mask_sh),\
+       SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_G_Y, mask_sh),\
+       SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_R_CR, mask_sh),\
+       SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\
+       SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\
+       SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\
+       SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\
+       SF(OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE, mask_sh),\
+       SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_START, mask_sh),\
+       SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_END, mask_sh),\
+       SF(OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_INT_ENABLE, mask_sh),\
+       SF(OTG0_OTG_VERTICAL_INTERRUPT1_POSITION, OTG_VERTICAL_INTERRUPT1_LINE_START, mask_sh),\
+       SF(OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE, mask_sh),\
+       SF(OTG0_OTG_VERTICAL_INTERRUPT2_POSITION, OTG_VERTICAL_INTERRUPT2_LINE_START, mask_sh),\
+       SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\
+       SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\
+       SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\
+       SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\
+       SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\
+       SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
+       SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
+       SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
+       SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, mask_sh),\
+       SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, mask_sh),\
+       SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_AUTO_FORCE_VSYNC_MODE, mask_sh),\
+       SF(OTG0_OTG_MASTER_UPDATE_MODE, MASTER_UPDATE_INTERLACED_MODE, mask_sh),\
+       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL0_EN, mask_sh),\
+       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL1_EN, mask_sh),\
+       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL2_EN, mask_sh),\
+       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_EN, mask_sh),\
+       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_FORCE_DELAY, mask_sh),\
+       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\
+       SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\
+       SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\
+       SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
+       SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\
+       SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\
+       SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\
+       SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_START, mask_sh),\
+       SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_END, mask_sh),\
+       SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_START, mask_sh),\
+       SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_END, mask_sh),\
+       SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_START, mask_sh),\
+       SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\
+       SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\
+       SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\
+       SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\
+       SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\
+       SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh)
+
+
+
+#define TG_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\
+       TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\
+       SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_INC0, mask_sh),\
+       SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_INC1, mask_sh),\
+       SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_VRES, mask_sh),\
+       SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_HRES, mask_sh),\
+       SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_RAMP0_OFFSET, mask_sh),\
+       SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_EN, mask_sh),\
+       SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_MODE, mask_sh),\
+       SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_DYNAMIC_RANGE, mask_sh),\
+       SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_COLOR_FORMAT, mask_sh),\
+       SF(OTG0_OTG_TEST_PATTERN_COLOR, OTG_TEST_PATTERN_MASK, mask_sh),\
+       SF(OTG0_OTG_TEST_PATTERN_COLOR, OTG_TEST_PATTERN_DATA, mask_sh),\
+       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SRC_SEL, mask_sh),\
+       SF(OTG0_OTG_MANUAL_FLOW_CONTROL, MANUAL_FLOW_CONTROL, mask_sh),\
+
+#define TG_REG_FIELD_LIST_DCN1_0(type) \
+       type VSTARTUP_START;\
+       type VUPDATE_OFFSET;\
+       type VUPDATE_WIDTH;\
+       type VREADY_OFFSET;\
+       type OTG_BLANK_DATA_EN;\
+       type OTG_BLANK_DE_MODE;\
+       type OTG_CURRENT_BLANK_STATE;\
+       type OTG_MASTER_UPDATE_LOCK;\
+       type UPDATE_LOCK_STATUS;\
+       type OTG_UPDATE_PENDING;\
+       type OTG_MASTER_UPDATE_LOCK_SEL;\
+       type OTG_BLANK_DATA_DOUBLE_BUFFER_EN;\
+       type OTG_H_TOTAL;\
+       type OTG_H_BLANK_START;\
+       type OTG_H_BLANK_END;\
+       type OTG_H_SYNC_A_START;\
+       type OTG_H_SYNC_A_END;\
+       type OTG_H_SYNC_A_POL;\
+       type OTG_H_TIMING_DIV_BY2;\
+       type OTG_V_TOTAL;\
+       type OTG_V_BLANK_START;\
+       type OTG_V_BLANK_END;\
+       type OTG_V_SYNC_A_START;\
+       type OTG_V_SYNC_A_END;\
+       type OTG_V_SYNC_A_POL;\
+       type OTG_INTERLACE_ENABLE;\
+       type OTG_MASTER_EN;\
+       type OTG_START_POINT_CNTL;\
+       type OTG_DISABLE_POINT_CNTL;\
+       type OTG_FIELD_NUMBER_CNTL;\
+       type OTG_CURRENT_MASTER_EN_STATE;\
+       type OTG_STEREO_EN;\
+       type OTG_STEREO_SYNC_OUTPUT_LINE_NUM;\
+       type OTG_STEREO_SYNC_OUTPUT_POLARITY;\
+       type OTG_STEREO_EYE_FLAG_POLARITY;\
+       type OTG_STEREO_CURRENT_EYE;\
+       type OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP;\
+       type OTG_3D_STRUCTURE_EN;\
+       type OTG_3D_STRUCTURE_V_UPDATE_MODE;\
+       type OTG_3D_STRUCTURE_STEREO_SEL_OVR;\
+       type OTG_V_TOTAL_MAX;\
+       type OTG_V_TOTAL_MID;\
+       type OTG_V_TOTAL_MIN;\
+       type OTG_V_TOTAL_MIN_SEL;\
+       type OTG_V_TOTAL_MAX_SEL;\
+       type OTG_VTOTAL_MID_REPLACING_MAX_EN;\
+       type OTG_VTOTAL_MID_FRAME_NUM;\
+       type OTG_FORCE_LOCK_ON_EVENT;\
+       type OTG_SET_V_TOTAL_MIN_MASK_EN;\
+       type OTG_SET_V_TOTAL_MIN_MASK;\
+       type OTG_FORCE_COUNT_NOW_CLEAR;\
+       type OTG_FORCE_COUNT_NOW_MODE;\
+       type OTG_FORCE_COUNT_NOW_OCCURRED;\
+       type OTG_TRIGA_SOURCE_SELECT;\
+       type OTG_TRIGA_SOURCE_PIPE_SELECT;\
+       type OTG_TRIGA_RISING_EDGE_DETECT_CNTL;\
+       type OTG_TRIGA_FALLING_EDGE_DETECT_CNTL;\
+       type OTG_TRIGA_POLARITY_SELECT;\
+       type OTG_TRIGA_FREQUENCY_SELECT;\
+       type OTG_TRIGA_DELAY;\
+       type OTG_TRIGA_CLEAR;\
+       type OTG_TRIGA_MANUAL_TRIG;\
+       type OTG_STATIC_SCREEN_EVENT_MASK;\
+       type OTG_STATIC_SCREEN_FRAME_COUNT;\
+       type OTG_FRAME_COUNT;\
+       type OTG_V_BLANK;\
+       type OTG_V_ACTIVE_DISP;\
+       type OTG_HORZ_COUNT;\
+       type OTG_VERT_COUNT;\
+       type OTG_VERT_COUNT_NOM;\
+       type OTG_BLACK_COLOR_B_CB;\
+       type OTG_BLACK_COLOR_G_Y;\
+       type OTG_BLACK_COLOR_R_CR;\
+       type OTG_BLANK_DATA_COLOR_BLUE_CB;\
+       type OTG_BLANK_DATA_COLOR_GREEN_Y;\
+       type OTG_BLANK_DATA_COLOR_RED_CR;\
+       type OTG_BLANK_DATA_COLOR_BLUE_CB_EXT;\
+       type OTG_BLANK_DATA_COLOR_GREEN_Y_EXT;\
+       type OTG_BLANK_DATA_COLOR_RED_CR_EXT;\
+       type OTG_VTOTAL_MID_REPLACING_MIN_EN;\
+       type OTG_TEST_PATTERN_INC0;\
+       type OTG_TEST_PATTERN_INC1;\
+       type OTG_TEST_PATTERN_VRES;\
+       type OTG_TEST_PATTERN_HRES;\
+       type OTG_TEST_PATTERN_RAMP0_OFFSET;\
+       type OTG_TEST_PATTERN_EN;\
+       type OTG_TEST_PATTERN_MODE;\
+       type OTG_TEST_PATTERN_DYNAMIC_RANGE;\
+       type OTG_TEST_PATTERN_COLOR_FORMAT;\
+       type OTG_TEST_PATTERN_MASK;\
+       type OTG_TEST_PATTERN_DATA;\
+       type OTG_BUSY;\
+       type OTG_CLOCK_EN;\
+       type OTG_CLOCK_ON;\
+       type OTG_CLOCK_GATE_DIS;\
+       type OTG_VERTICAL_INTERRUPT0_INT_ENABLE;\
+       type OTG_VERTICAL_INTERRUPT0_LINE_START;\
+       type OTG_VERTICAL_INTERRUPT0_LINE_END;\
+       type OTG_VERTICAL_INTERRUPT1_INT_ENABLE;\
+       type OTG_VERTICAL_INTERRUPT1_LINE_START;\
+       type OTG_VERTICAL_INTERRUPT2_INT_ENABLE;\
+       type OTG_VERTICAL_INTERRUPT2_LINE_START;\
+       type OPTC_INPUT_CLK_EN;\
+       type OPTC_INPUT_CLK_ON;\
+       type OPTC_INPUT_CLK_GATE_DIS;\
+       type OPTC_UNDERFLOW_OCCURRED_STATUS;\
+       type OPTC_UNDERFLOW_CLEAR;\
+       type OPTC_SRC_SEL;\
+       type VTG0_ENABLE;\
+       type VTG0_FP2;\
+       type VTG0_VCOUNT_INIT;\
+       type OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED;\
+       type OTG_FORCE_VSYNC_NEXT_LINE_CLEAR;\
+       type OTG_AUTO_FORCE_VSYNC_MODE;\
+       type MASTER_UPDATE_INTERLACED_MODE;\
+       type OTG_GSL0_EN;\
+       type OTG_GSL1_EN;\
+       type OTG_GSL2_EN;\
+       type OTG_GSL_MASTER_EN;\
+       type OTG_GSL_FORCE_DELAY;\
+       type OTG_GSL_CHECK_ALL_FIELDS;\
+       type OTG_GSL_WINDOW_START_X;\
+       type OTG_GSL_WINDOW_END_X;\
+       type OTG_GSL_WINDOW_START_Y;\
+       type OTG_GSL_WINDOW_END_Y;\
+       type OTG_RANGE_TIMING_DBUF_UPDATE_MODE;\
+       type OTG_GSL_MASTER_MODE;\
+       type OTG_MASTER_UPDATE_LOCK_GSL_EN;\
+       type MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET;\
+       type MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET;\
+       type OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN;\
+       type OTG_CRC_CONT_EN;\
+       type OTG_CRC0_SELECT;\
+       type OTG_CRC_EN;\
+       type CRC0_R_CR;\
+       type CRC0_G_Y;\
+       type CRC0_B_CB;\
+       type CRC1_R_CR;\
+       type CRC1_G_Y;\
+       type CRC1_B_CB;\
+       type CRC2_R_CR;\
+       type CRC2_G_Y;\
+       type CRC2_B_CB;\
+       type CRC3_R_CR;\
+       type CRC3_G_Y;\
+       type CRC3_B_CB;\
+       type OTG_CRC0_WINDOWA_X_START;\
+       type OTG_CRC0_WINDOWA_X_END;\
+       type OTG_CRC0_WINDOWA_Y_START;\
+       type OTG_CRC0_WINDOWA_Y_END;\
+       type OTG_CRC0_WINDOWB_X_START;\
+       type OTG_CRC0_WINDOWB_X_END;\
+       type OTG_CRC0_WINDOWB_Y_START;\
+       type OTG_CRC0_WINDOWB_Y_END;\
+       type OTG_CRC_WINDOW_DB_EN;\
+       type OTG_CRC1_WINDOWA_X_START;\
+       type OTG_CRC1_WINDOWA_X_END;\
+       type OTG_CRC1_WINDOWA_Y_START;\
+       type OTG_CRC1_WINDOWA_Y_END;\
+       type OTG_CRC1_WINDOWB_X_START;\
+       type OTG_CRC1_WINDOWB_X_END;\
+       type OTG_CRC1_WINDOWB_Y_START;\
+       type OTG_CRC1_WINDOWB_Y_END;\
+       type GSL0_READY_SOURCE_SEL;\
+       type GSL1_READY_SOURCE_SEL;\
+       type GSL2_READY_SOURCE_SEL;\
+       type MANUAL_FLOW_CONTROL;\
+       type MANUAL_FLOW_CONTROL_SEL;
+
+#define TG_REG_FIELD_LIST(type) \
+       TG_REG_FIELD_LIST_DCN1_0(type)\
+       type OTG_V_SYNC_MODE;\
+       type OTG_DRR_TRIGGER_WINDOW_START_X;\
+       type OTG_DRR_TRIGGER_WINDOW_END_X;\
+       type OTG_DRR_V_TOTAL_CHANGE_LIMIT;\
+       type OTG_OUT_MUX;\
+       type OTG_M_CONST_DTO_PHASE;\
+       type OTG_M_CONST_DTO_MODULO;\
+       type MASTER_UPDATE_LOCK_DB_X;\
+       type MASTER_UPDATE_LOCK_DB_Y;\
+       type MASTER_UPDATE_LOCK_DB_EN;\
+       type GLOBAL_UPDATE_LOCK_EN;\
+       type DIG_UPDATE_LOCATION;\
+       type OTG_DSC_START_POSITION_X;\
+       type OTG_DSC_START_POSITION_LINE_NUM;\
+       type OPTC_NUM_OF_INPUT_SEGMENT;\
+       type OPTC_SEG0_SRC_SEL;\
+       type OPTC_SEG1_SRC_SEL;\
+       type OPTC_SEG2_SRC_SEL;\
+       type OPTC_SEG3_SRC_SEL;\
+       type OPTC_MEM_SEL;\
+       type OPTC_DATA_FORMAT;\
+       type OPTC_DSC_MODE;\
+       type OPTC_DSC_BYTES_PER_PIXEL;\
+       type OPTC_DSC_SLICE_WIDTH;\
+       type OPTC_SEGMENT_WIDTH;\
+       type OPTC_DWB0_SOURCE_SELECT;\
+       type OPTC_DWB1_SOURCE_SELECT;\
+       type MASTER_UPDATE_LOCK_DB_START_X;\
+       type MASTER_UPDATE_LOCK_DB_END_X;\
+       type MASTER_UPDATE_LOCK_DB_START_Y;\
+       type MASTER_UPDATE_LOCK_DB_END_Y;\
+       type DIG_UPDATE_POSITION_X;\
+       type DIG_UPDATE_POSITION_Y;\
+       type OTG_H_TIMING_DIV_MODE;\
+       type OTG_DRR_TIMING_DBUF_UPDATE_MODE;\
+       type OTG_CRC_DSC_MODE;\
+       type OTG_CRC_DATA_STREAM_COMBINE_MODE;\
+       type OTG_CRC_DATA_STREAM_SPLIT_MODE;\
+       type OTG_CRC_DATA_FORMAT;\
+       type OTG_V_TOTAL_LAST_USED_BY_DRR;\
+       type OTG_DRR_TIMING_DBUF_UPDATE_PENDING;
+
+#define TG_REG_FIELD_LIST_DCN3_2(type) \
+       type OTG_H_TIMING_DIV_MODE_MANUAL;
+
+
+#define TG_REG_FIELD_LIST_DCN3_5(type) \
+       type OTG_CRC0_WINDOWA_X_START_READBACK;\
+       type OTG_CRC0_WINDOWA_X_END_READBACK;\
+       type OTG_CRC0_WINDOWA_Y_START_READBACK;\
+       type OTG_CRC0_WINDOWA_Y_END_READBACK;\
+       type OTG_CRC0_WINDOWB_X_START_READBACK;\
+       type OTG_CRC0_WINDOWB_X_END_READBACK;\
+       type OTG_CRC0_WINDOWB_Y_START_READBACK;\
+       type OTG_CRC0_WINDOWB_Y_END_READBACK; \
+       type OTG_CRC1_WINDOWA_X_START_READBACK;\
+       type OTG_CRC1_WINDOWA_X_END_READBACK;\
+       type OTG_CRC1_WINDOWA_Y_START_READBACK;\
+       type OTG_CRC1_WINDOWA_Y_END_READBACK;\
+       type OTG_CRC1_WINDOWB_X_START_READBACK;\
+       type OTG_CRC1_WINDOWB_X_END_READBACK;\
+       type OTG_CRC1_WINDOWB_Y_START_READBACK;\
+       type OTG_CRC1_WINDOWB_Y_END_READBACK;\
+       type OPTC_FGCG_REP_DIS;
+
+struct dcn_optc_shift {
+       TG_REG_FIELD_LIST(uint8_t)
+       TG_REG_FIELD_LIST_DCN3_2(uint8_t)
+       TG_REG_FIELD_LIST_DCN3_5(uint8_t)
+};
+
+struct dcn_optc_mask {
+       TG_REG_FIELD_LIST(uint32_t)
+       TG_REG_FIELD_LIST_DCN3_2(uint32_t)
+       TG_REG_FIELD_LIST_DCN3_5(uint32_t)
+};
+
+void dcn10_timing_generator_init(struct optc *optc);
+
+#endif /* __DC_TIMING_GENERATOR_DCN10_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
new file mode 100644 (file)
index 0000000..58bdbd8
--- /dev/null
@@ -0,0 +1,587 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "reg_helper.h"
+#include "dcn20_optc.h"
+#include "dc.h"
+
+#define REG(reg)\
+       optc1->tg_regs->reg
+
+#define CTX \
+       optc1->base.ctx
+
+#undef FN
+#define FN(reg_name, field_name) \
+       optc1->tg_shift->field_name, optc1->tg_mask->field_name
+
+/**
+ * optc2_enable_crtc() - Enable CRTC - call ASIC Control Object to enable Timing generator.
+ *
+ * @optc: timing_generator instance.
+ *
+ * Return: If CRTC is enabled, return true.
+ *
+ */
+bool optc2_enable_crtc(struct timing_generator *optc)
+{
+       /* TODO FPGA wait for answer
+        * OTG_MASTER_UPDATE_MODE != CRTC_MASTER_UPDATE_MODE
+        * OTG_MASTER_UPDATE_LOCK != CRTC_MASTER_UPDATE_LOCK
+        */
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       /* opp instance for OTG. For DCN1.0, ODM is remoed.
+        * OPP and OPTC should 1:1 mapping
+        */
+       REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
+                       OPTC_SEG0_SRC_SEL, optc->inst);
+
+       /* VTG enable first is for HW workaround */
+       REG_UPDATE(CONTROL,
+                       VTG0_ENABLE, 1);
+
+       REG_SEQ_START();
+
+       /* Enable CRTC */
+       REG_UPDATE_2(OTG_CONTROL,
+                       OTG_DISABLE_POINT_CNTL, 3,
+                       OTG_MASTER_EN, 1);
+
+       REG_SEQ_SUBMIT();
+       REG_SEQ_WAIT_DONE();
+
+       return true;
+}
+
+/**
+ * optc2_set_gsl() - Assign OTG to GSL groups,
+ *                   set one of the OTGs to be master & rest are slaves
+ *
+ * @optc: timing_generator instance.
+ * @params: pointer to gsl_params
+ */
+void optc2_set_gsl(struct timing_generator *optc,
+                  const struct gsl_params *params)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+/*
+ * There are (MAX_OPTC+1)/2 gsl groups available for use.
+ * In each group (assign an OTG to a group by setting OTG_GSLX_EN = 1,
+ * set one of the OTGs to be the master (OTG_GSL_MASTER_EN = 1) and the rest are slaves.
+ */
+       REG_UPDATE_5(OTG_GSL_CONTROL,
+               OTG_GSL0_EN, params->gsl0_en,
+               OTG_GSL1_EN, params->gsl1_en,
+               OTG_GSL2_EN, params->gsl2_en,
+               OTG_GSL_MASTER_EN, params->gsl_master_en,
+               OTG_GSL_MASTER_MODE, params->gsl_master_mode);
+}
+
+
+void optc2_set_gsl_source_select(
+               struct timing_generator *optc,
+               int group_idx,
+               uint32_t gsl_ready_signal)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       switch (group_idx) {
+       case 1:
+               REG_UPDATE(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, gsl_ready_signal);
+               break;
+       case 2:
+               REG_UPDATE(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, gsl_ready_signal);
+               break;
+       case 3:
+               REG_UPDATE(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, gsl_ready_signal);
+               break;
+       default:
+               break;
+       }
+}
+
+/* Set DSC-related configuration.
+ *   dsc_mode: 0 disables DSC, other values enable DSC in specified format
+ *   sc_bytes_per_pixel: Bytes per pixel in u3.28 format
+ *   dsc_slice_width: Slice width in pixels
+ */
+void optc2_set_dsc_config(struct timing_generator *optc,
+                                       enum optc_dsc_mode dsc_mode,
+                                       uint32_t dsc_bytes_per_pixel,
+                                       uint32_t dsc_slice_width)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       REG_UPDATE(OPTC_DATA_FORMAT_CONTROL,
+               OPTC_DSC_MODE, dsc_mode);
+
+       REG_SET(OPTC_BYTES_PER_PIXEL, 0,
+               OPTC_DSC_BYTES_PER_PIXEL, dsc_bytes_per_pixel);
+
+       REG_UPDATE(OPTC_WIDTH_CONTROL,
+               OPTC_DSC_SLICE_WIDTH, dsc_slice_width);
+}
+
+/* Get DSC-related configuration.
+ *   dsc_mode: 0 disables DSC, other values enable DSC in specified format
+ */
+void optc2_get_dsc_status(struct timing_generator *optc,
+                                       uint32_t *dsc_mode)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       REG_GET(OPTC_DATA_FORMAT_CONTROL,
+               OPTC_DSC_MODE, dsc_mode);
+}
+
+
+/*TEMP: Need to figure out inheritance model here.*/
+bool optc2_is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
+{
+       return optc1_is_two_pixels_per_containter(timing);
+}
+
+void optc2_set_odm_bypass(struct timing_generator *optc,
+               const struct dc_crtc_timing *dc_crtc_timing)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+       uint32_t h_div_2 = 0;
+
+       REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
+                       OPTC_NUM_OF_INPUT_SEGMENT, 0,
+                       OPTC_SEG0_SRC_SEL, optc->inst,
+                       OPTC_SEG1_SRC_SEL, 0xf);
+       REG_WRITE(OTG_H_TIMING_CNTL, 0);
+
+       h_div_2 = optc2_is_two_pixels_per_containter(dc_crtc_timing);
+       REG_UPDATE(OTG_H_TIMING_CNTL,
+                       OTG_H_TIMING_DIV_BY2, h_div_2);
+       REG_SET(OPTC_MEMORY_CONFIG, 0,
+                       OPTC_MEM_SEL, 0);
+       optc1->opp_count = 1;
+}
+
+void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
+               struct dc_crtc_timing *timing)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+       int mpcc_hactive = (timing->h_addressable + timing->h_border_left + timing->h_border_right)
+                       / opp_cnt;
+       uint32_t memory_mask;
+
+       ASSERT(opp_cnt == 2);
+
+       /* TODO: In pseudocode but does not affect maximus, delete comment if we dont need on asic
+        * REG_SET(OTG_GLOBAL_CONTROL2, 0, GLOBAL_UPDATE_LOCK_EN, 1);
+        * Program OTG register MASTER_UPDATE_LOCK_DB_X/Y to the position before DP frame start
+        * REG_SET_2(OTG_GLOBAL_CONTROL1, 0,
+        *              MASTER_UPDATE_LOCK_DB_X, 160,
+        *              MASTER_UPDATE_LOCK_DB_Y, 240);
+        */
+
+       /* 2 pieces of memory required for up to 5120 displays, 4 for up to 8192,
+        * however, for ODM combine we can simplify by always using 4.
+        * To make sure there's no overlap, each instance "reserves" 2 memories and
+        * they are uniquely combined here.
+        */
+       memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);
+
+       if (REG(OPTC_MEMORY_CONFIG))
+               REG_SET(OPTC_MEMORY_CONFIG, 0,
+                       OPTC_MEM_SEL, memory_mask);
+
+       REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
+                       OPTC_NUM_OF_INPUT_SEGMENT, 1,
+                       OPTC_SEG0_SRC_SEL, opp_id[0],
+                       OPTC_SEG1_SRC_SEL, opp_id[1]);
+
+       REG_UPDATE(OPTC_WIDTH_CONTROL,
+                       OPTC_SEGMENT_WIDTH, mpcc_hactive);
+
+       REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_BY2, 1);
+       optc1->opp_count = opp_cnt;
+}
+
+void optc2_get_optc_source(struct timing_generator *optc,
+               uint32_t *num_of_src_opp,
+               uint32_t *src_opp_id_0,
+               uint32_t *src_opp_id_1)
+{
+       uint32_t num_of_input_segments;
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       REG_GET_3(OPTC_DATA_SOURCE_SELECT,
+                       OPTC_NUM_OF_INPUT_SEGMENT, &num_of_input_segments,
+                       OPTC_SEG0_SRC_SEL, src_opp_id_0,
+                       OPTC_SEG1_SRC_SEL, src_opp_id_1);
+
+       if (num_of_input_segments == 1)
+               *num_of_src_opp = 2;
+       else
+               *num_of_src_opp = 1;
+
+       /* Work around VBIOS not updating OPTC_NUM_OF_INPUT_SEGMENT */
+       if (*src_opp_id_1 == 0xf)
+               *num_of_src_opp = 1;
+}
+
+static void optc2_set_dwb_source(struct timing_generator *optc,
+                                uint32_t dwb_pipe_inst)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       if (dwb_pipe_inst == 0)
+               REG_UPDATE(DWB_SOURCE_SELECT,
+                               OPTC_DWB0_SOURCE_SELECT, optc->inst);
+       else if (dwb_pipe_inst == 1)
+               REG_UPDATE(DWB_SOURCE_SELECT,
+                               OPTC_DWB1_SOURCE_SELECT, optc->inst);
+}
+
+static void optc2_align_vblanks(
+       struct timing_generator *optc_master,
+       struct timing_generator *optc_slave,
+       uint32_t master_pixel_clock_100Hz,
+       uint32_t slave_pixel_clock_100Hz,
+       uint8_t master_clock_divider,
+       uint8_t slave_clock_divider)
+{
+       /* accessing slave OTG registers */
+       struct optc *optc1 = DCN10TG_FROM_TG(optc_slave);
+
+       uint32_t master_v_active = 0;
+       uint32_t master_h_total = 0;
+       uint32_t slave_h_total = 0;
+       uint64_t L, XY;
+       uint32_t X, Y, p = 10000;
+       uint32_t master_update_lock;
+
+       /* disable slave OTG */
+       REG_UPDATE(OTG_CONTROL, OTG_MASTER_EN, 0);
+       /* wait until disabled */
+       REG_WAIT(OTG_CONTROL,
+                        OTG_CURRENT_MASTER_EN_STATE,
+                        0, 10, 5000);
+
+       REG_GET(OTG_H_TOTAL, OTG_H_TOTAL, &slave_h_total);
+
+       /* assign slave OTG to be controlled by master update lock */
+       REG_SET(OTG_GLOBAL_CONTROL0, 0,
+                       OTG_MASTER_UPDATE_LOCK_SEL, optc_master->inst);
+
+       /* accessing master OTG registers */
+       optc1 = DCN10TG_FROM_TG(optc_master);
+
+       /* saving update lock state, not sure if it's needed */
+       REG_GET(OTG_MASTER_UPDATE_LOCK,
+                       OTG_MASTER_UPDATE_LOCK, &master_update_lock);
+       /* unlocking master OTG */
+       REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
+                       OTG_MASTER_UPDATE_LOCK, 0);
+
+       REG_GET(OTG_V_BLANK_START_END,
+                       OTG_V_BLANK_START, &master_v_active);
+       REG_GET(OTG_H_TOTAL, OTG_H_TOTAL, &master_h_total);
+
+       /* calculate when to enable slave OTG */
+       L = (uint64_t)p * slave_h_total * master_pixel_clock_100Hz;
+       L = div_u64(L, master_h_total);
+       L = div_u64(L, slave_pixel_clock_100Hz);
+       XY = div_u64(L, p);
+       Y = master_v_active - XY - 1;
+       X = div_u64(((XY + 1) * p - L) * master_h_total, p * master_clock_divider);
+
+       /*
+        * set master OTG to unlock when V/H
+        * counters reach calculated values
+        */
+       REG_UPDATE(OTG_GLOBAL_CONTROL1,
+                          MASTER_UPDATE_LOCK_DB_EN, 1);
+       REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
+                                MASTER_UPDATE_LOCK_DB_X,
+                                X,
+                                MASTER_UPDATE_LOCK_DB_Y,
+                                Y);
+
+       /* lock master OTG */
+       REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
+                       OTG_MASTER_UPDATE_LOCK, 1);
+       REG_WAIT(OTG_MASTER_UPDATE_LOCK,
+                        UPDATE_LOCK_STATUS, 1, 1, 10);
+
+       /* accessing slave OTG registers */
+       optc1 = DCN10TG_FROM_TG(optc_slave);
+
+       /*
+        * enable slave OTG, the OTG is locked with
+        * master's update lock, so it will not run
+        */
+       REG_UPDATE(OTG_CONTROL,
+                          OTG_MASTER_EN, 1);
+
+       /* accessing master OTG registers */
+       optc1 = DCN10TG_FROM_TG(optc_master);
+
+       /*
+        * unlock master OTG. When master H/V counters reach
+        * DB_XY point, slave OTG will start
+        */
+       REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
+                       OTG_MASTER_UPDATE_LOCK, 0);
+
+       /* accessing slave OTG registers */
+       optc1 = DCN10TG_FROM_TG(optc_slave);
+
+       /* wait for slave OTG to start running*/
+       REG_WAIT(OTG_CONTROL,
+                        OTG_CURRENT_MASTER_EN_STATE,
+                        1, 10, 5000);
+
+       /* accessing master OTG registers */
+       optc1 = DCN10TG_FROM_TG(optc_master);
+
+       /* disable the XY point*/
+       REG_UPDATE(OTG_GLOBAL_CONTROL1,
+                          MASTER_UPDATE_LOCK_DB_EN, 0);
+       REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
+                                MASTER_UPDATE_LOCK_DB_X,
+                                0,
+                                MASTER_UPDATE_LOCK_DB_Y,
+                                0);
+
+       /*restore master update lock*/
+       REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
+                       OTG_MASTER_UPDATE_LOCK, master_update_lock);
+
+       /* accessing slave OTG registers */
+       optc1 = DCN10TG_FROM_TG(optc_slave);
+       /* restore slave to be controlled by it's own */
+       REG_SET(OTG_GLOBAL_CONTROL0, 0,
+                       OTG_MASTER_UPDATE_LOCK_SEL, optc_slave->inst);
+
+}
+
+void optc2_triplebuffer_lock(struct timing_generator *optc)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       REG_SET(OTG_GLOBAL_CONTROL0, 0,
+               OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
+
+       REG_SET(OTG_VUPDATE_KEEPOUT, 0,
+               OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 1);
+
+       REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
+               OTG_MASTER_UPDATE_LOCK, 1);
+
+       REG_WAIT(OTG_MASTER_UPDATE_LOCK,
+                       UPDATE_LOCK_STATUS, 1,
+                       1, 10);
+}
+
+void optc2_triplebuffer_unlock(struct timing_generator *optc)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
+               OTG_MASTER_UPDATE_LOCK, 0);
+
+       REG_SET(OTG_VUPDATE_KEEPOUT, 0,
+               OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 0);
+
+}
+
+void optc2_lock_doublebuffer_enable(struct timing_generator *optc)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+       uint32_t v_blank_start = 0;
+       uint32_t h_blank_start = 0;
+
+       REG_UPDATE(OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, 1);
+
+       REG_UPDATE_2(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 1,
+                       DIG_UPDATE_LOCATION, 20);
+
+       REG_GET(OTG_V_BLANK_START_END, OTG_V_BLANK_START, &v_blank_start);
+
+       REG_GET(OTG_H_BLANK_START_END, OTG_H_BLANK_START, &h_blank_start);
+
+       REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
+                       MASTER_UPDATE_LOCK_DB_X,
+                       (h_blank_start - 200 - 1) / optc1->opp_count,
+                       MASTER_UPDATE_LOCK_DB_Y,
+                       v_blank_start - 1);
+
+       REG_SET_3(OTG_VUPDATE_KEEPOUT, 0,
+               MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, 0,
+               MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, 100,
+               OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 1);
+}
+
+void optc2_lock_doublebuffer_disable(struct timing_generator *optc)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
+                               MASTER_UPDATE_LOCK_DB_X,
+                               0,
+                               MASTER_UPDATE_LOCK_DB_Y,
+                               0);
+
+       REG_UPDATE_2(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 0,
+                               DIG_UPDATE_LOCATION, 0);
+
+       REG_UPDATE(OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, 0);
+}
+
+void optc2_setup_manual_trigger(struct timing_generator *optc)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       /* Set the min/max selectors unconditionally so that
+        * DMCUB fw may change OTG timings when necessary
+        * TODO: Remove the w/a after fixing the issue in DMCUB firmware
+        */
+       REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
+                                OTG_V_TOTAL_MIN_SEL, 1,
+                                OTG_V_TOTAL_MAX_SEL, 1,
+                                OTG_FORCE_LOCK_ON_EVENT, 0,
+                                OTG_SET_V_TOTAL_MIN_MASK, (1 << 1)); /* TRIGA */
+
+       REG_SET_8(OTG_TRIGA_CNTL, 0,
+                       OTG_TRIGA_SOURCE_SELECT, 21,
+                       OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst,
+                       OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1,
+                       OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 0,
+                       OTG_TRIGA_POLARITY_SELECT, 0,
+                       OTG_TRIGA_FREQUENCY_SELECT, 0,
+                       OTG_TRIGA_DELAY, 0,
+                       OTG_TRIGA_CLEAR, 1);
+}
+
+void optc2_program_manual_trigger(struct timing_generator *optc)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       REG_SET(OTG_TRIGA_MANUAL_TRIG, 0,
+                       OTG_TRIGA_MANUAL_TRIG, 1);
+}
+
+bool optc2_configure_crc(struct timing_generator *optc,
+                         const struct crc_params *params)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       REG_SET_2(OTG_CRC_CNTL2, 0,
+                       OTG_CRC_DSC_MODE, params->dsc_mode,
+                       OTG_CRC_DATA_STREAM_COMBINE_MODE, params->odm_mode);
+
+       return optc1_configure_crc(optc, params);
+}
+
+
+void optc2_get_last_used_drr_vtotal(struct timing_generator *optc, uint32_t *refresh_rate)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       REG_GET(OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, refresh_rate);
+}
+
+static struct timing_generator_funcs dcn20_tg_funcs = {
+               .validate_timing = optc1_validate_timing,
+               .program_timing = optc1_program_timing,
+               .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
+               .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
+               .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
+               .program_global_sync = optc1_program_global_sync,
+               .enable_crtc = optc2_enable_crtc,
+               .disable_crtc = optc1_disable_crtc,
+               /* used by enable_timing_synchronization. Not need for FPGA */
+               .is_counter_moving = optc1_is_counter_moving,
+               .get_position = optc1_get_position,
+               .get_frame_count = optc1_get_vblank_counter,
+               .get_scanoutpos = optc1_get_crtc_scanoutpos,
+               .get_otg_active_size = optc1_get_otg_active_size,
+               .set_early_control = optc1_set_early_control,
+               /* used by enable_timing_synchronization. Not need for FPGA */
+               .wait_for_state = optc1_wait_for_state,
+               .set_blank = optc1_set_blank,
+               .is_blanked = optc1_is_blanked,
+               .set_blank_color = optc1_program_blank_color,
+               .enable_reset_trigger = optc1_enable_reset_trigger,
+               .enable_crtc_reset = optc1_enable_crtc_reset,
+               .did_triggered_reset_occur = optc1_did_triggered_reset_occur,
+               .triplebuffer_lock = optc2_triplebuffer_lock,
+               .triplebuffer_unlock = optc2_triplebuffer_unlock,
+               .disable_reset_trigger = optc1_disable_reset_trigger,
+               .lock = optc1_lock,
+               .unlock = optc1_unlock,
+               .lock_doublebuffer_enable = optc2_lock_doublebuffer_enable,
+               .lock_doublebuffer_disable = optc2_lock_doublebuffer_disable,
+               .enable_optc_clock = optc1_enable_optc_clock,
+               .set_drr = optc1_set_drr,
+               .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
+               .set_vtotal_min_max = optc1_set_vtotal_min_max,
+               .set_static_screen_control = optc1_set_static_screen_control,
+               .program_stereo = optc1_program_stereo,
+               .is_stereo_left_eye = optc1_is_stereo_left_eye,
+               .set_blank_data_double_buffer = optc1_set_blank_data_double_buffer,
+               .tg_init = optc1_tg_init,
+               .is_tg_enabled = optc1_is_tg_enabled,
+               .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
+               .clear_optc_underflow = optc1_clear_optc_underflow,
+               .setup_global_swap_lock = NULL,
+               .get_crc = optc1_get_crc,
+               .configure_crc = optc2_configure_crc,
+               .set_dsc_config = optc2_set_dsc_config,
+               .get_dsc_status = optc2_get_dsc_status,
+               .set_dwb_source = optc2_set_dwb_source,
+               .set_odm_bypass = optc2_set_odm_bypass,
+               .set_odm_combine = optc2_set_odm_combine,
+               .get_optc_source = optc2_get_optc_source,
+               .set_gsl = optc2_set_gsl,
+               .set_gsl_source_select = optc2_set_gsl_source_select,
+               .set_vtg_params = optc1_set_vtg_params,
+               .program_manual_trigger = optc2_program_manual_trigger,
+               .setup_manual_trigger = optc2_setup_manual_trigger,
+               .get_hw_timing = optc1_get_hw_timing,
+               .align_vblanks = optc2_align_vblanks,
+};
+
+void dcn20_timing_generator_init(struct optc *optc1)
+{
+       optc1->base.funcs = &dcn20_tg_funcs;
+
+       optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
+       optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
+
+       optc1->min_h_blank = 32;
+       optc1->min_v_blank = 3;
+       optc1->min_v_blank_interlace = 5;
+       optc1->min_h_sync_width = 4;//  Minimum HSYNC = 8 pixels asked By HW in the first place for no actual reason. Oculus Rift S will not light up with 8 as it's hsyncWidth is 6. Changing it to 4 to fix that issue.
+       optc1->min_v_sync_width = 1;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
new file mode 100644 (file)
index 0000000..c2e03ce
--- /dev/null
@@ -0,0 +1,124 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_OPTC_DCN20_H__
+#define __DC_OPTC_DCN20_H__
+
+#include "dcn10/dcn10_optc.h"
+
+#define TG_COMMON_REG_LIST_DCN2_0(inst) \
+       TG_COMMON_REG_LIST_DCN(inst),\
+       SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
+       SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
+       SRI(OTG_GSL_WINDOW_X, OTG, inst),\
+       SRI(OTG_GSL_WINDOW_Y, OTG, inst),\
+       SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\
+       SRI(OTG_DSC_START_POSITION, OTG, inst),\
+       SRI(OTG_CRC_CNTL2, OTG, inst),\
+       SRI(OPTC_DATA_FORMAT_CONTROL, ODM, inst),\
+       SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\
+       SRI(OPTC_WIDTH_CONTROL, ODM, inst),\
+       SRI(OPTC_MEMORY_CONFIG, ODM, inst),\
+       SR(DWB_SOURCE_SELECT),\
+       SRI(OTG_MANUAL_FLOW_CONTROL, OTG, inst), \
+       SRI(OTG_DRR_CONTROL, OTG, inst)
+
+#define TG_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\
+       TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_X, mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_Y, mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL2, DIG_UPDATE_LOCATION, mask_sh),\
+       SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mask_sh),\
+       SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\
+       SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \
+       SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\
+       SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\
+       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_MODE, mask_sh), \
+       SF(OTG0_OTG_GSL_CONTROL, OTG_MASTER_UPDATE_LOCK_GSL_EN, mask_sh), \
+       SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_X, mask_sh), \
+       SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_LINE_NUM, mask_sh),\
+       SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DSC_MODE, mask_sh),\
+       SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_COMBINE_MODE, mask_sh),\
+       SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_SPLIT_MODE, mask_sh),\
+       SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_FORMAT, mask_sh),\
+       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG0_SRC_SEL, mask_sh),\
+       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG1_SRC_SEL, mask_sh),\
+       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, mask_sh),\
+       SF(ODM0_OPTC_MEMORY_CONFIG, OPTC_MEM_SEL, mask_sh),\
+       SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, mask_sh),\
+       SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\
+       SF(ODM0_OPTC_BYTES_PER_PIXEL, OPTC_DSC_BYTES_PER_PIXEL, mask_sh),\
+       SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, mask_sh),\
+       SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_SEGMENT_WIDTH, mask_sh),\
+       SF(DWB_SOURCE_SELECT, OPTC_DWB0_SOURCE_SELECT, mask_sh),\
+       SF(DWB_SOURCE_SELECT, OPTC_DWB1_SOURCE_SELECT, mask_sh),\
+       SF(OTG0_OTG_MANUAL_FLOW_CONTROL, MANUAL_FLOW_CONTROL, mask_sh), \
+       SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh)
+
+void dcn20_timing_generator_init(struct optc *optc);
+
+void optc2_get_last_used_drr_vtotal(struct timing_generator *optc,
+               uint32_t *refresh_rate);
+
+bool optc2_enable_crtc(struct timing_generator *optc);
+
+void optc2_set_gsl(struct timing_generator *optc,
+               const struct gsl_params *params);
+
+void optc2_set_gsl_source_select(struct timing_generator *optc,
+               int group_idx,
+               uint32_t gsl_ready_signal);
+
+void optc2_set_dsc_config(struct timing_generator *optc,
+                                       enum optc_dsc_mode dsc_mode,
+                                       uint32_t dsc_bytes_per_pixel,
+                                       uint32_t dsc_slice_width);
+
+void optc2_get_dsc_status(struct timing_generator *optc,
+                                       uint32_t *dsc_mode);
+
+void optc2_set_odm_bypass(struct timing_generator *optc,
+               const struct dc_crtc_timing *dc_crtc_timing);
+
+void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
+               struct dc_crtc_timing *timing);
+
+void optc2_get_optc_source(struct timing_generator *optc,
+               uint32_t *num_of_src_opp,
+               uint32_t *src_opp_id_0,
+               uint32_t *src_opp_id_1);
+
+void optc2_triplebuffer_lock(struct timing_generator *optc);
+void optc2_triplebuffer_unlock(struct timing_generator *optc);
+void optc2_lock_doublebuffer_disable(struct timing_generator *optc);
+void optc2_lock_doublebuffer_enable(struct timing_generator *optc);
+void optc2_setup_manual_trigger(struct timing_generator *optc);
+void optc2_program_manual_trigger(struct timing_generator *optc);
+bool optc2_is_two_pixels_per_containter(const struct dc_crtc_timing *timing);
+bool optc2_configure_crc(struct timing_generator *optc,
+                         const struct crc_params *params);
+#endif /* __DC_OPTC_DCN20_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c
new file mode 100644 (file)
index 0000000..70fcbec
--- /dev/null
@@ -0,0 +1,202 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "reg_helper.h"
+#include "dcn201_optc.h"
+#include "dcn10/dcn10_optc.h"
+#include "dc.h"
+
+#define REG(reg)\
+       optc1->tg_regs->reg
+
+#define CTX \
+       optc1->base.ctx
+
+#undef FN
+#define FN(reg_name, field_name) \
+       optc1->tg_shift->field_name, optc1->tg_mask->field_name
+
+/*TEMP: Need to figure out inheritance model here.*/
+bool optc201_is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
+{
+       return optc1_is_two_pixels_per_containter(timing);
+}
+
+static void optc201_triplebuffer_lock(struct timing_generator *optc)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       REG_SET(OTG_GLOBAL_CONTROL0, 0,
+               OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
+       REG_SET(OTG_VUPDATE_KEEPOUT, 0,
+               OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 1);
+       REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
+               OTG_MASTER_UPDATE_LOCK, 1);
+
+       REG_WAIT(OTG_MASTER_UPDATE_LOCK,
+                       UPDATE_LOCK_STATUS, 1,
+                       1, 10);
+}
+
+static void optc201_triplebuffer_unlock(struct timing_generator *optc)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
+               OTG_MASTER_UPDATE_LOCK, 0);
+       REG_SET(OTG_VUPDATE_KEEPOUT, 0,
+               OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 0);
+
+}
+
+static bool optc201_validate_timing(
+       struct timing_generator *optc,
+       const struct dc_crtc_timing *timing)
+{
+       uint32_t v_blank;
+       uint32_t h_blank;
+       uint32_t min_v_blank;
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       ASSERT(timing != NULL);
+
+       v_blank = (timing->v_total - timing->v_addressable -
+                                       timing->v_border_top - timing->v_border_bottom);
+
+       h_blank = (timing->h_total - timing->h_addressable -
+               timing->h_border_right -
+               timing->h_border_left);
+
+       if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE &&
+               timing->timing_3d_format != TIMING_3D_FORMAT_HW_FRAME_PACKING &&
+               timing->timing_3d_format != TIMING_3D_FORMAT_TOP_AND_BOTTOM &&
+               timing->timing_3d_format != TIMING_3D_FORMAT_SIDE_BY_SIDE &&
+               timing->timing_3d_format != TIMING_3D_FORMAT_FRAME_ALTERNATE &&
+               timing->timing_3d_format != TIMING_3D_FORMAT_INBAND_FA)
+               return false;
+
+       /* Check maximum number of pixels supported by Timing Generator
+        * (Currently will never fail, in order to fail needs display which
+        * needs more than 8192 horizontal and
+        * more than 8192 vertical total pixels)
+        */
+       if (timing->h_total > optc1->max_h_total ||
+               timing->v_total > optc1->max_v_total)
+               return false;
+
+       if (h_blank < optc1->min_h_blank)
+               return false;
+
+       if (timing->h_sync_width  < optc1->min_h_sync_width ||
+                timing->v_sync_width  < optc1->min_v_sync_width)
+               return false;
+
+       min_v_blank = timing->flags.INTERLACE?optc1->min_v_blank_interlace:optc1->min_v_blank;
+
+       if (v_blank < min_v_blank)
+               return false;
+
+       return true;
+
+}
+
+static void optc201_get_optc_source(struct timing_generator *optc,
+               uint32_t *num_of_src_opp,
+               uint32_t *src_opp_id_0,
+               uint32_t *src_opp_id_1)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       REG_GET(OPTC_DATA_SOURCE_SELECT,
+                       OPTC_SEG0_SRC_SEL, src_opp_id_0);
+
+       *num_of_src_opp = 1;
+}
+
+static struct timing_generator_funcs dcn201_tg_funcs = {
+               .validate_timing = optc201_validate_timing,
+               .program_timing = optc1_program_timing,
+               .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
+               .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
+               .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
+               .program_global_sync = optc1_program_global_sync,
+               .enable_crtc = optc2_enable_crtc,
+               .disable_crtc = optc1_disable_crtc,
+               /* used by enable_timing_synchronization. Not need for FPGA */
+               .is_counter_moving = optc1_is_counter_moving,
+               .get_position = optc1_get_position,
+               .get_frame_count = optc1_get_vblank_counter,
+               .get_scanoutpos = optc1_get_crtc_scanoutpos,
+               .get_otg_active_size = optc1_get_otg_active_size,
+               .set_early_control = optc1_set_early_control,
+               /* used by enable_timing_synchronization. Not need for FPGA */
+               .wait_for_state = optc1_wait_for_state,
+               .set_blank = optc1_set_blank,
+               .is_blanked = optc1_is_blanked,
+               .set_blank_color = optc1_program_blank_color,
+               .did_triggered_reset_occur = optc1_did_triggered_reset_occur,
+               .enable_reset_trigger = optc1_enable_reset_trigger,
+               .enable_crtc_reset = optc1_enable_crtc_reset,
+               .disable_reset_trigger = optc1_disable_reset_trigger,
+               .triplebuffer_lock = optc201_triplebuffer_lock,
+               .triplebuffer_unlock = optc201_triplebuffer_unlock,
+               .lock = optc1_lock,
+               .unlock = optc1_unlock,
+               .enable_optc_clock = optc1_enable_optc_clock,
+               .set_drr = optc1_set_drr,
+               .get_last_used_drr_vtotal = NULL,
+               .set_vtotal_min_max = optc1_set_vtotal_min_max,
+               .set_static_screen_control = optc1_set_static_screen_control,
+               .program_stereo = optc1_program_stereo,
+               .is_stereo_left_eye = optc1_is_stereo_left_eye,
+               .set_blank_data_double_buffer = optc1_set_blank_data_double_buffer,
+               .tg_init = optc1_tg_init,
+               .is_tg_enabled = optc1_is_tg_enabled,
+               .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
+               .clear_optc_underflow = optc1_clear_optc_underflow,
+               .get_crc = optc1_get_crc,
+               .configure_crc = optc2_configure_crc,
+               .set_dsc_config = optc2_set_dsc_config,
+               .set_dwb_source = NULL,
+               .get_optc_source = optc201_get_optc_source,
+               .set_vtg_params = optc1_set_vtg_params,
+               .program_manual_trigger = optc2_program_manual_trigger,
+               .setup_manual_trigger = optc2_setup_manual_trigger,
+               .get_hw_timing = optc1_get_hw_timing,
+};
+
+void dcn201_timing_generator_init(struct optc *optc1)
+{
+       optc1->base.funcs = &dcn201_tg_funcs;
+
+       optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
+       optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
+
+       optc1->min_h_blank = 32;
+       optc1->min_v_blank = 3;
+       optc1->min_v_blank_interlace = 5;
+       optc1->min_h_sync_width = 8;
+       optc1->min_v_sync_width = 1;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.h
new file mode 100644 (file)
index 0000000..e9545b7
--- /dev/null
@@ -0,0 +1,74 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_OPTC_DCN201_H__
+#define __DC_OPTC_DCN201_H__
+
+#include "dcn20/dcn20_optc.h"
+
+#define TG_COMMON_REG_LIST_DCN201(inst) \
+       TG_COMMON_REG_LIST_DCN(inst),\
+       SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
+       SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
+       SRI(OTG_GSL_WINDOW_X, OTG, inst),\
+       SRI(OTG_GSL_WINDOW_Y, OTG, inst),\
+       SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\
+       SRI(OTG_DSC_START_POSITION, OTG, inst),\
+       SRI(OPTC_DATA_FORMAT_CONTROL, ODM, inst),\
+       SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\
+       SRI(OPTC_WIDTH_CONTROL, ODM, inst),\
+       SR(DWB_SOURCE_SELECT)
+
+#define TG_COMMON_MASK_SH_LIST_DCN201(mask_sh)\
+       TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_X, mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_Y, mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\
+       SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mask_sh),\
+       SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\
+       SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \
+       SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\
+       SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\
+       SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, mask_sh), \
+       SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, mask_sh), \
+       SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, mask_sh), \
+       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_MODE, mask_sh), \
+       SF(OTG0_OTG_GSL_CONTROL, OTG_MASTER_UPDATE_LOCK_GSL_EN, mask_sh), \
+       SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_X, mask_sh), \
+       SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_LINE_NUM, mask_sh),\
+       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG0_SRC_SEL, mask_sh),\
+       SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\
+       SF(ODM0_OPTC_BYTES_PER_PIXEL, OPTC_DSC_BYTES_PER_PIXEL, mask_sh),\
+       SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, mask_sh),\
+       SF(DWB_SOURCE_SELECT, OPTC_DWB0_SOURCE_SELECT, mask_sh),\
+       SF(DWB_SOURCE_SELECT, OPTC_DWB1_SOURCE_SELECT, mask_sh),\
+       SF(DWB_SOURCE_SELECT, OPTC_DWB1_SOURCE_SELECT, mask_sh)
+
+void dcn201_timing_generator_init(struct optc *optc);
+
+bool optc201_is_two_pixels_per_containter(const struct dc_crtc_timing *timing);
+
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c
new file mode 100644 (file)
index 0000000..b97bdb8
--- /dev/null
@@ -0,0 +1,393 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "reg_helper.h"
+#include "dcn30_optc.h"
+#include "dc.h"
+#include "dcn_calc_math.h"
+#include "dc_dmub_srv.h"
+
+#include "dml/dcn30/dcn30_fpu.h"
+#include "dc_trace.h"
+
+#define REG(reg)\
+       optc1->tg_regs->reg
+
+#define CTX \
+       optc1->base.ctx
+
+#undef FN
+#define FN(reg_name, field_name) \
+       optc1->tg_shift->field_name, optc1->tg_mask->field_name
+
+void optc3_triplebuffer_lock(struct timing_generator *optc)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       REG_UPDATE(OTG_GLOBAL_CONTROL2,
+               OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
+
+       REG_SET(OTG_VUPDATE_KEEPOUT, 0,
+               OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 1);
+
+       REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
+               OTG_MASTER_UPDATE_LOCK, 1);
+
+       REG_WAIT(OTG_MASTER_UPDATE_LOCK,
+                       UPDATE_LOCK_STATUS, 1,
+                       1, 10);
+
+       TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, true);
+}
+
+void optc3_lock_doublebuffer_enable(struct timing_generator *optc)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+       uint32_t v_blank_start = 0;
+       uint32_t v_blank_end = 0;
+       uint32_t h_blank_start = 0;
+       uint32_t h_blank_end = 0;
+
+       REG_GET_2(OTG_V_BLANK_START_END,
+               OTG_V_BLANK_START, &v_blank_start,
+               OTG_V_BLANK_END, &v_blank_end);
+       REG_GET_2(OTG_H_BLANK_START_END,
+               OTG_H_BLANK_START, &h_blank_start,
+               OTG_H_BLANK_END, &h_blank_end);
+
+       REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
+               MASTER_UPDATE_LOCK_DB_START_Y, v_blank_start - 1,
+               MASTER_UPDATE_LOCK_DB_END_Y, v_blank_start);
+       REG_UPDATE_2(OTG_GLOBAL_CONTROL4,
+               DIG_UPDATE_POSITION_X, h_blank_start - 180 - 1,
+               DIG_UPDATE_POSITION_Y, v_blank_start - 1);
+       // there is a DIG_UPDATE_VCOUNT_MODE and it is 0.
+
+       REG_UPDATE_3(OTG_GLOBAL_CONTROL0,
+               MASTER_UPDATE_LOCK_DB_START_X, h_blank_start - 200 - 1,
+               MASTER_UPDATE_LOCK_DB_END_X, h_blank_start - 180,
+               MASTER_UPDATE_LOCK_DB_EN, 1);
+       REG_UPDATE(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 1);
+
+       REG_SET_3(OTG_VUPDATE_KEEPOUT, 0,
+               MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, 0,
+               MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, 100,
+               OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 1);
+
+       TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, true);
+}
+
+void optc3_lock_doublebuffer_disable(struct timing_generator *optc)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       REG_UPDATE_2(OTG_GLOBAL_CONTROL0,
+               MASTER_UPDATE_LOCK_DB_START_X, 0,
+               MASTER_UPDATE_LOCK_DB_END_X, 0);
+       REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
+               MASTER_UPDATE_LOCK_DB_START_Y, 0,
+               MASTER_UPDATE_LOCK_DB_END_Y, 0);
+
+       REG_UPDATE(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 0);
+       REG_UPDATE(OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, 0);
+
+       TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, true);
+}
+
+void optc3_lock(struct timing_generator *optc)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       REG_UPDATE(OTG_GLOBAL_CONTROL2,
+               OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
+       REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
+               OTG_MASTER_UPDATE_LOCK, 1);
+
+       REG_WAIT(OTG_MASTER_UPDATE_LOCK,
+                       UPDATE_LOCK_STATUS, 1,
+                       1, 10);
+
+       TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, true);
+}
+
+void optc3_set_out_mux(struct timing_generator *optc, enum otg_out_mux_dest dest)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       REG_UPDATE(OTG_CONTROL, OTG_OUT_MUX, dest);
+}
+
+void optc3_program_blank_color(struct timing_generator *optc,
+               const struct tg_color *blank_color)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       REG_SET_3(OTG_BLANK_DATA_COLOR, 0,
+               OTG_BLANK_DATA_COLOR_BLUE_CB, blank_color->color_b_cb,
+               OTG_BLANK_DATA_COLOR_GREEN_Y, blank_color->color_g_y,
+               OTG_BLANK_DATA_COLOR_RED_CR, blank_color->color_r_cr);
+
+       REG_SET_3(OTG_BLANK_DATA_COLOR_EXT, 0,
+               OTG_BLANK_DATA_COLOR_BLUE_CB_EXT, blank_color->color_b_cb >> 10,
+               OTG_BLANK_DATA_COLOR_GREEN_Y_EXT, blank_color->color_g_y >> 10,
+               OTG_BLANK_DATA_COLOR_RED_CR_EXT, blank_color->color_r_cr >> 10);
+}
+
+void optc3_set_drr_trigger_window(struct timing_generator *optc,
+               uint32_t window_start, uint32_t window_end)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       REG_SET_2(OTG_DRR_TRIGGER_WINDOW, 0,
+               OTG_DRR_TRIGGER_WINDOW_START_X, window_start,
+               OTG_DRR_TRIGGER_WINDOW_END_X, window_end);
+}
+
+void optc3_set_vtotal_change_limit(struct timing_generator *optc,
+               uint32_t limit)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+
+       REG_SET(OTG_DRR_V_TOTAL_CHANGE, 0,
+               OTG_DRR_V_TOTAL_CHANGE_LIMIT, limit);
+}
+
+
+/* Set DSC-related configuration.
+ *   dsc_mode: 0 disables DSC, other values enable DSC in specified format
+ *   sc_bytes_per_pixel: Bytes per pixel in u3.28 format
+ *   dsc_slice_width: Slice width in pixels
+ */
+void optc3_set_dsc_config(struct timing_generator *optc,
+               enum optc_dsc_mode dsc_mode,
+               uint32_t dsc_bytes_per_pixel,
+               uint32_t dsc_slice_width)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       optc2_set_dsc_config(optc, dsc_mode, dsc_bytes_per_pixel, dsc_slice_width);
+       REG_UPDATE(OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, 0);
+}
+
+void optc3_set_odm_bypass(struct timing_generator *optc,
+               const struct dc_crtc_timing *dc_crtc_timing)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+       enum h_timing_div_mode h_div = H_TIMING_NO_DIV;
+
+       REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
+                       OPTC_NUM_OF_INPUT_SEGMENT, 0,
+                       OPTC_SEG0_SRC_SEL, optc->inst,
+                       OPTC_SEG1_SRC_SEL, 0xf,
+                       OPTC_SEG2_SRC_SEL, 0xf,
+                       OPTC_SEG3_SRC_SEL, 0xf
+                       );
+
+       h_div = optc1_is_two_pixels_per_containter(dc_crtc_timing);
+       REG_UPDATE(OTG_H_TIMING_CNTL,
+                       OTG_H_TIMING_DIV_MODE, h_div);
+
+       REG_SET(OPTC_MEMORY_CONFIG, 0,
+                       OPTC_MEM_SEL, 0);
+       optc1->opp_count = 1;
+}
+
+void optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
+               struct dc_crtc_timing *timing)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+       int mpcc_hactive = (timing->h_addressable + timing->h_border_left + timing->h_border_right)
+                       / opp_cnt;
+       uint32_t memory_mask = 0;
+
+       /* TODO: In pseudocode but does not affect maximus, delete comment if we dont need on asic
+        * REG_SET(OTG_GLOBAL_CONTROL2, 0, GLOBAL_UPDATE_LOCK_EN, 1);
+        * Program OTG register MASTER_UPDATE_LOCK_DB_X/Y to the position before DP frame start
+        * REG_SET_2(OTG_GLOBAL_CONTROL1, 0,
+        *              MASTER_UPDATE_LOCK_DB_X, 160,
+        *              MASTER_UPDATE_LOCK_DB_Y, 240);
+        */
+
+       ASSERT(opp_cnt == 2 || opp_cnt == 4);
+
+       /* 2 pieces of memory required for up to 5120 displays, 4 for up to 8192,
+        * however, for ODM combine we can simplify by always using 4.
+        */
+       if (opp_cnt == 2) {
+               /* To make sure there's no memory overlap, each instance "reserves" 2
+                * memories and they are uniquely combined here.
+                */
+               memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);
+       } else if (opp_cnt == 4) {
+               /* To make sure there's no memory overlap, each instance "reserves" 1
+                * memory and they are uniquely combined here.
+                */
+               memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2) | 0x1 << (opp_id[2] * 2) | 0x1 << (opp_id[3] * 2);
+       }
+
+       if (REG(OPTC_MEMORY_CONFIG))
+               REG_SET(OPTC_MEMORY_CONFIG, 0,
+                       OPTC_MEM_SEL, memory_mask);
+
+       if (opp_cnt == 2) {
+               REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
+                               OPTC_NUM_OF_INPUT_SEGMENT, 1,
+                               OPTC_SEG0_SRC_SEL, opp_id[0],
+                               OPTC_SEG1_SRC_SEL, opp_id[1]);
+       } else if (opp_cnt == 4) {
+               REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
+                               OPTC_NUM_OF_INPUT_SEGMENT, 3,
+                               OPTC_SEG0_SRC_SEL, opp_id[0],
+                               OPTC_SEG1_SRC_SEL, opp_id[1],
+                               OPTC_SEG2_SRC_SEL, opp_id[2],
+                               OPTC_SEG3_SRC_SEL, opp_id[3]);
+       }
+
+       REG_UPDATE(OPTC_WIDTH_CONTROL,
+                       OPTC_SEGMENT_WIDTH, mpcc_hactive);
+
+       REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1);
+       optc1->opp_count = opp_cnt;
+}
+
+/**
+ * optc3_set_timing_double_buffer() - DRR double buffering control
+ *
+ * Sets double buffer point for V_TOTAL, H_TOTAL, VTOTAL_MIN,
+ * VTOTAL_MAX, VTOTAL_MIN_SEL and VTOTAL_MAX_SEL registers.
+ *
+ * @optc: timing_generator instance.
+ * @enable: Enable DRR double buffering control if true, disable otherwise.
+ *
+ * Options: any time,  start of frame, dp start of frame (range timing)
+ */
+static void optc3_set_timing_double_buffer(struct timing_generator *optc, bool enable)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+       uint32_t mode = enable ? 2 : 0;
+
+       REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,
+                  OTG_DRR_TIMING_DBUF_UPDATE_MODE, mode);
+}
+
+void optc3_wait_drr_doublebuffer_pending_clear(struct timing_generator *optc)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       REG_WAIT(OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_PENDING, 0, 2, 100000); /* 1 vupdate at 5hz */
+
+}
+
+void optc3_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max)
+{
+       struct dc *dc = optc->ctx->dc;
+
+       if (dc->caps.dmub_caps.mclk_sw && !dc->debug.disable_fams)
+               dc_dmub_srv_drr_update_cmd(dc, optc->inst, vtotal_min, vtotal_max);
+       else
+               optc1_set_vtotal_min_max(optc, vtotal_min, vtotal_max);
+}
+
+void optc3_tg_init(struct timing_generator *optc)
+{
+       optc3_set_timing_double_buffer(optc, true);
+       optc1_clear_optc_underflow(optc);
+}
+
+static struct timing_generator_funcs dcn30_tg_funcs = {
+               .validate_timing = optc1_validate_timing,
+               .program_timing = optc1_program_timing,
+               .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
+               .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
+               .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
+               .program_global_sync = optc1_program_global_sync,
+               .enable_crtc = optc2_enable_crtc,
+               .disable_crtc = optc1_disable_crtc,
+               /* used by enable_timing_synchronization. Not need for FPGA */
+               .is_counter_moving = optc1_is_counter_moving,
+               .get_position = optc1_get_position,
+               .get_frame_count = optc1_get_vblank_counter,
+               .get_scanoutpos = optc1_get_crtc_scanoutpos,
+               .get_otg_active_size = optc1_get_otg_active_size,
+               .set_early_control = optc1_set_early_control,
+               /* used by enable_timing_synchronization. Not need for FPGA */
+               .wait_for_state = optc1_wait_for_state,
+               .set_blank_color = optc3_program_blank_color,
+               .did_triggered_reset_occur = optc1_did_triggered_reset_occur,
+               .triplebuffer_lock = optc3_triplebuffer_lock,
+               .triplebuffer_unlock = optc2_triplebuffer_unlock,
+               .enable_reset_trigger = optc1_enable_reset_trigger,
+               .enable_crtc_reset = optc1_enable_crtc_reset,
+               .disable_reset_trigger = optc1_disable_reset_trigger,
+               .lock = optc3_lock,
+               .unlock = optc1_unlock,
+               .lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,
+               .lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
+               .enable_optc_clock = optc1_enable_optc_clock,
+               .set_drr = optc1_set_drr,
+               .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
+               .set_vtotal_min_max = optc3_set_vtotal_min_max,
+               .set_static_screen_control = optc1_set_static_screen_control,
+               .program_stereo = optc1_program_stereo,
+               .is_stereo_left_eye = optc1_is_stereo_left_eye,
+               .tg_init = optc3_tg_init,
+               .is_tg_enabled = optc1_is_tg_enabled,
+               .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
+               .clear_optc_underflow = optc1_clear_optc_underflow,
+               .setup_global_swap_lock = NULL,
+               .get_crc = optc1_get_crc,
+               .configure_crc = optc2_configure_crc,
+               .set_dsc_config = optc3_set_dsc_config,
+               .get_dsc_status = optc2_get_dsc_status,
+               .set_dwb_source = NULL,
+               .set_odm_bypass = optc3_set_odm_bypass,
+               .set_odm_combine = optc3_set_odm_combine,
+               .get_optc_source = optc2_get_optc_source,
+               .set_out_mux = optc3_set_out_mux,
+               .set_drr_trigger_window = optc3_set_drr_trigger_window,
+               .set_vtotal_change_limit = optc3_set_vtotal_change_limit,
+               .set_gsl = optc2_set_gsl,
+               .set_gsl_source_select = optc2_set_gsl_source_select,
+               .set_vtg_params = optc1_set_vtg_params,
+               .program_manual_trigger = optc2_program_manual_trigger,
+               .setup_manual_trigger = optc2_setup_manual_trigger,
+               .get_hw_timing = optc1_get_hw_timing,
+               .wait_drr_doublebuffer_pending_clear = optc3_wait_drr_doublebuffer_pending_clear,
+};
+
+void dcn30_timing_generator_init(struct optc *optc1)
+{
+       optc1->base.funcs = &dcn30_tg_funcs;
+
+       optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
+       optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
+
+       optc1->min_h_blank = 32;
+       optc1->min_v_blank = 3;
+       optc1->min_v_blank_interlace = 5;
+       optc1->min_h_sync_width = 4;
+       optc1->min_v_sync_width = 1;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
new file mode 100644 (file)
index 0000000..d3a056c
--- /dev/null
@@ -0,0 +1,359 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_OPTC_DCN30_H__
+#define __DC_OPTC_DCN30_H__
+
+#include "dcn20/dcn20_optc.h"
+
+#define V_TOTAL_REGS_DCN30_SRI(inst)
+
+#define OPTC_COMMON_REG_LIST_DCN3_BASE(inst) \
+       SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
+       SRI(OTG_VUPDATE_PARAM, OTG, inst),\
+       SRI(OTG_VREADY_PARAM, OTG, inst),\
+       SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
+       SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
+       SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
+       SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
+       SRI(OTG_GLOBAL_CONTROL4, OTG, inst),\
+       SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
+       SRI(OTG_H_TOTAL, OTG, inst),\
+       SRI(OTG_H_BLANK_START_END, OTG, inst),\
+       SRI(OTG_H_SYNC_A, OTG, inst),\
+       SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\
+       SRI(OTG_H_TIMING_CNTL, OTG, inst),\
+       SRI(OTG_V_TOTAL, OTG, inst),\
+       SRI(OTG_V_BLANK_START_END, OTG, inst),\
+       SRI(OTG_V_SYNC_A, OTG, inst),\
+       SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\
+       SRI(OTG_CONTROL, OTG, inst),\
+       SRI(OTG_STEREO_CONTROL, OTG, inst),\
+       SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\
+       SRI(OTG_STEREO_STATUS, OTG, inst),\
+       SRI(OTG_V_TOTAL_MAX, OTG, inst),\
+       SRI(OTG_V_TOTAL_MIN, OTG, inst),\
+       SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\
+       V_TOTAL_REGS_DCN30_SRI(inst)\
+       SRI(OTG_TRIGA_CNTL, OTG, inst),\
+       SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\
+       SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\
+       SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\
+       SRI(OTG_STATUS, OTG, inst),\
+       SRI(OTG_STATUS_POSITION, OTG, inst),\
+       SRI(OTG_NOM_VERT_POSITION, OTG, inst),\
+       SRI(OTG_BLANK_DATA_COLOR, OTG, inst),\
+       SRI(OTG_BLANK_DATA_COLOR_EXT, OTG, inst),\
+       SRI(OTG_M_CONST_DTO0, OTG, inst),\
+       SRI(OTG_M_CONST_DTO1, OTG, inst),\
+       SRI(OTG_CLOCK_CONTROL, OTG, inst),\
+       SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\
+       SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\
+       SRI(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\
+       SRI(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\
+       SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\
+       SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\
+       SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\
+       SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\
+       SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\
+       SRI(CONTROL, VTG, inst),\
+       SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\
+       SRI(OTG_GSL_CONTROL, OTG, inst),\
+       SRI(OTG_CRC_CNTL, OTG, inst),\
+       SRI(OTG_CRC_CNTL2, OTG, inst),\
+       SRI(OTG_CRC0_DATA_RG, OTG, inst),\
+       SRI(OTG_CRC0_DATA_B, OTG, inst),\
+       SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\
+       SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\
+       SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\
+       SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\
+       SR(GSL_SOURCE_SELECT),\
+       SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst),\
+       SRI(OTG_DRR_CONTROL, OTG, inst)
+
+
+#define OPTC_COMMON_REG_LIST_DCN3_0(inst) \
+       OPTC_COMMON_REG_LIST_DCN3_BASE(inst),\
+       SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
+       SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
+       SRI(OTG_GSL_WINDOW_X, OTG, inst),\
+       SRI(OTG_GSL_WINDOW_Y, OTG, inst),\
+       SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\
+       SRI(OTG_DSC_START_POSITION, OTG, inst),\
+       SRI(OTG_CRC_CNTL2, OTG, inst),\
+       SRI(OTG_DRR_TRIGGER_WINDOW, OTG, inst),\
+       SRI(OTG_DRR_V_TOTAL_CHANGE, OTG, inst),\
+       SRI(OPTC_DATA_FORMAT_CONTROL, ODM, inst),\
+       SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\
+       SRI(OPTC_WIDTH_CONTROL, ODM, inst),\
+       SRI(OPTC_MEMORY_CONFIG, ODM, inst),\
+       SR(DWB_SOURCE_SELECT)
+
+#define DCN30_VTOTAL_REGS_SF(mask_sh)
+
+#define OPTC_COMMON_MASK_SH_LIST_DCN3_BASE(mask_sh)\
+       SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
+       SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
+       SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
+       SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
+       SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\
+       SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_START_X, mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_END_X, mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_START_Y, mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_END_Y, mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL2, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_X, mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_Y, mask_sh),\
+       SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\
+       SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
+       SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_START, mask_sh),\
+       SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_END, mask_sh),\
+       SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_START, mask_sh),\
+       SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_END, mask_sh),\
+       SF(OTG0_OTG_H_SYNC_A_CNTL, OTG_H_SYNC_A_POL, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
+       SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_START, mask_sh),\
+       SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_END, mask_sh),\
+       SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_START, mask_sh),\
+       SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_END, mask_sh),\
+       SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_A_POL, mask_sh),\
+       SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, mask_sh),\
+       SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
+       SF(OTG0_OTG_CONTROL, OTG_START_POINT_CNTL, mask_sh),\
+       SF(OTG0_OTG_CONTROL, OTG_DISABLE_POINT_CNTL, mask_sh),\
+       SF(OTG0_OTG_CONTROL, OTG_FIELD_NUMBER_CNTL, mask_sh),\
+       SF(OTG0_OTG_CONTROL, OTG_OUT_MUX, mask_sh),\
+       SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EN, mask_sh),\
+       SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_LINE_NUM, mask_sh),\
+       SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_POLARITY, mask_sh),\
+       SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EYE_FLAG_POLARITY, mask_sh),\
+       SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\
+       SF(OTG0_OTG_STEREO_STATUS, OTG_STEREO_CURRENT_EYE, mask_sh),\
+       SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_EN, mask_sh),\
+       SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\
+       SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK_EN, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MIN_EN, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\
+       DCN30_VTOTAL_REGS_SF(mask_sh)\
+       SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\
+       SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\
+       SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\
+       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_SELECT, mask_sh),\
+       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_PIPE_SELECT, mask_sh),\
+       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_RISING_EDGE_DETECT_CNTL, mask_sh),\
+       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, mask_sh),\
+       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_POLARITY_SELECT, mask_sh),\
+       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FREQUENCY_SELECT, mask_sh),\
+       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_DELAY, mask_sh),\
+       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_CLEAR, mask_sh),\
+       SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_EVENT_MASK, mask_sh),\
+       SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_FRAME_COUNT, mask_sh),\
+       SF(OTG0_OTG_STATUS_FRAME_COUNT, OTG_FRAME_COUNT, mask_sh),\
+       SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
+       SF(OTG0_OTG_STATUS, OTG_V_ACTIVE_DISP, mask_sh),\
+       SF(OTG0_OTG_STATUS_POSITION, OTG_HORZ_COUNT, mask_sh),\
+       SF(OTG0_OTG_STATUS_POSITION, OTG_VERT_COUNT, mask_sh),\
+       SF(OTG0_OTG_NOM_VERT_POSITION, OTG_VERT_COUNT_NOM, mask_sh),\
+       SF(OTG0_OTG_BLANK_DATA_COLOR, OTG_BLANK_DATA_COLOR_BLUE_CB, mask_sh),\
+       SF(OTG0_OTG_BLANK_DATA_COLOR, OTG_BLANK_DATA_COLOR_GREEN_Y, mask_sh),\
+       SF(OTG0_OTG_BLANK_DATA_COLOR, OTG_BLANK_DATA_COLOR_RED_CR, mask_sh),\
+       SF(OTG0_OTG_BLANK_DATA_COLOR_EXT, OTG_BLANK_DATA_COLOR_BLUE_CB_EXT, mask_sh),\
+       SF(OTG0_OTG_BLANK_DATA_COLOR_EXT, OTG_BLANK_DATA_COLOR_GREEN_Y_EXT, mask_sh),\
+       SF(OTG0_OTG_BLANK_DATA_COLOR_EXT, OTG_BLANK_DATA_COLOR_RED_CR_EXT, mask_sh),\
+       SF(OTG0_OTG_M_CONST_DTO0, OTG_M_CONST_DTO_PHASE, mask_sh),\
+       SF(OTG0_OTG_M_CONST_DTO1, OTG_M_CONST_DTO_MODULO, mask_sh),\
+       SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\
+       SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\
+       SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\
+       SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\
+       SF(OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE, mask_sh),\
+       SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_START, mask_sh),\
+       SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_END, mask_sh),\
+       SF(OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_INT_ENABLE, mask_sh),\
+       SF(OTG0_OTG_VERTICAL_INTERRUPT1_POSITION, OTG_VERTICAL_INTERRUPT1_LINE_START, mask_sh),\
+       SF(OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE, mask_sh),\
+       SF(OTG0_OTG_VERTICAL_INTERRUPT2_POSITION, OTG_VERTICAL_INTERRUPT2_LINE_START, mask_sh),\
+       SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\
+       SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\
+       SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\
+       SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\
+       SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\
+       SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
+       SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
+       SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
+       SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, mask_sh),\
+       SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, mask_sh),\
+       SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_AUTO_FORCE_VSYNC_MODE, mask_sh),\
+       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL0_EN, mask_sh),\
+       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL1_EN, mask_sh),\
+       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL2_EN, mask_sh),\
+       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_EN, mask_sh),\
+       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_FORCE_DELAY, mask_sh),\
+       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\
+       SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\
+       SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\
+       SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
+       SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DSC_MODE, mask_sh),\
+       SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_COMBINE_MODE, mask_sh),\
+       SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_SPLIT_MODE, mask_sh),\
+       SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_FORMAT, mask_sh),\
+       SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\
+       SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\
+       SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\
+       SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_START, mask_sh),\
+       SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_END, mask_sh),\
+       SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_START, mask_sh),\
+       SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_END, mask_sh),\
+       SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_START, mask_sh),\
+       SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\
+       SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\
+       SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\
+       SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\
+       SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\
+       SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\
+       SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh),\
+       SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh)
+
+#define OPTC_COMMON_MASK_SH_LIST_DCN3_0(mask_sh)\
+       OPTC_COMMON_MASK_SH_LIST_DCN3_BASE(mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\
+       SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\
+       SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \
+       SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\
+       SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\
+       SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, mask_sh), \
+       SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, mask_sh), \
+       SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, mask_sh), \
+       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_MODE, mask_sh), \
+       SF(OTG0_OTG_GSL_CONTROL, OTG_MASTER_UPDATE_LOCK_GSL_EN, mask_sh), \
+       SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_X, mask_sh), \
+       SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_LINE_NUM, mask_sh),\
+       SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DSC_MODE, mask_sh),\
+       SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_COMBINE_MODE, mask_sh),\
+       SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_SPLIT_MODE, mask_sh),\
+       SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_FORMAT, mask_sh),\
+       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG0_SRC_SEL, mask_sh),\
+       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG1_SRC_SEL, mask_sh),\
+       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, mask_sh),\
+       SF(ODM0_OPTC_MEMORY_CONFIG, OPTC_MEM_SEL, mask_sh),\
+       SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, mask_sh),\
+       SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\
+       SF(ODM0_OPTC_BYTES_PER_PIXEL, OPTC_DSC_BYTES_PER_PIXEL, mask_sh),\
+       SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, mask_sh),\
+       SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_SEGMENT_WIDTH, mask_sh),\
+       SF(DWB_SOURCE_SELECT, OPTC_DWB0_SOURCE_SELECT, mask_sh),\
+       SF(DWB_SOURCE_SELECT, OPTC_DWB1_SOURCE_SELECT, mask_sh),\
+       SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_START_X, mask_sh),\
+       SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_END_X, mask_sh),\
+       SF(OTG0_OTG_DRR_V_TOTAL_CHANGE, OTG_DRR_V_TOTAL_CHANGE_LIMIT, mask_sh),\
+       SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_BY2, mask_sh),\
+       SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_PENDING, mask_sh),\
+       SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh),\
+       SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_BLANK_DATA_DOUBLE_BUFFER_EN, mask_sh)
+
+#define OPTC_COMMON_MASK_SH_LIST_DCN30(mask_sh)\
+       OPTC_COMMON_MASK_SH_LIST_DCN3_BASE(mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\
+       SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\
+       SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \
+       SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\
+       SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\
+       SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, mask_sh), \
+       SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, mask_sh), \
+       SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, mask_sh), \
+       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_MODE, mask_sh), \
+       SF(OTG0_OTG_GSL_CONTROL, OTG_MASTER_UPDATE_LOCK_GSL_EN, mask_sh), \
+       SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_X, mask_sh), \
+       SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_LINE_NUM, mask_sh),\
+       SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DSC_MODE, mask_sh),\
+       SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_COMBINE_MODE, mask_sh),\
+       SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_SPLIT_MODE, mask_sh),\
+       SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_FORMAT, mask_sh),\
+       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG0_SRC_SEL, mask_sh),\
+       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG1_SRC_SEL, mask_sh),\
+       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG2_SRC_SEL, mask_sh),\
+       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG3_SRC_SEL, mask_sh),\
+       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, mask_sh),\
+       SF(ODM0_OPTC_MEMORY_CONFIG, OPTC_MEM_SEL, mask_sh),\
+       SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, mask_sh),\
+       SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\
+       SF(ODM0_OPTC_BYTES_PER_PIXEL, OPTC_DSC_BYTES_PER_PIXEL, mask_sh),\
+       SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, mask_sh),\
+       SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_SEGMENT_WIDTH, mask_sh),\
+       SF(DWB_SOURCE_SELECT, OPTC_DWB0_SOURCE_SELECT, mask_sh),\
+       SF(DWB_SOURCE_SELECT, OPTC_DWB1_SOURCE_SELECT, mask_sh),\
+       SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_START_X, mask_sh),\
+       SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_END_X, mask_sh),\
+       SF(OTG0_OTG_DRR_V_TOTAL_CHANGE, OTG_DRR_V_TOTAL_CHANGE_LIMIT, mask_sh),\
+       SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\
+       SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_PENDING, mask_sh),\
+       SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh)
+
+void dcn30_timing_generator_init(struct optc *optc1);
+
+void optc3_set_out_mux(struct timing_generator *optc, enum otg_out_mux_dest dest);
+
+void optc3_lock(struct timing_generator *optc);
+
+void optc3_lock_doublebuffer_enable(struct timing_generator *optc);
+
+void optc3_lock_doublebuffer_disable(struct timing_generator *optc);
+
+void optc3_set_drr_trigger_window(struct timing_generator *optc,
+               uint32_t window_start, uint32_t window_end);
+
+void optc3_triplebuffer_lock(struct timing_generator *optc);
+
+void optc3_program_blank_color(struct timing_generator *optc,
+               const struct tg_color *blank_color);
+
+void optc3_set_vtotal_change_limit(struct timing_generator *optc,
+               uint32_t limit);
+
+void optc3_set_dsc_config(struct timing_generator *optc,
+               enum optc_dsc_mode dsc_mode,
+               uint32_t dsc_bytes_per_pixel,
+               uint32_t dsc_slice_width);
+
+void optc3_set_timing_db_mode(struct timing_generator *optc, bool enable);
+
+void optc3_set_odm_bypass(struct timing_generator *optc,
+               const struct dc_crtc_timing *dc_crtc_timing);
+void optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
+               struct dc_crtc_timing *timing);
+void optc3_wait_drr_doublebuffer_pending_clear(struct timing_generator *optc);
+void optc3_tg_init(struct timing_generator *optc);
+void optc3_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max);
+#endif /* __DC_OPTC_DCN30_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c
new file mode 100644 (file)
index 0000000..b3cfcb8
--- /dev/null
@@ -0,0 +1,185 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "reg_helper.h"
+#include "dcn301_optc.h"
+#include "dc.h"
+#include "dcn_calc_math.h"
+#include "dc_dmub_srv.h"
+
+#include "dml/dcn30/dcn30_fpu.h"
+#include "dc_trace.h"
+
+#define REG(reg)\
+       optc1->tg_regs->reg
+
+#define CTX \
+       optc1->base.ctx
+
+#undef FN
+#define FN(reg_name, field_name) \
+       optc1->tg_shift->field_name, optc1->tg_mask->field_name
+
+
+/**
+ * optc301_set_drr() - Program dynamic refresh rate registers m_OTGx_OTG_V_TOTAL_*.
+ *
+ * @optc: timing_generator instance.
+ * @params: parameters used for Dynamic Refresh Rate.
+ */
+void optc301_set_drr(
+       struct timing_generator *optc,
+       const struct drr_params *params)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       if (params != NULL &&
+               params->vertical_total_max > 0 &&
+               params->vertical_total_min > 0) {
+
+               if (params->vertical_total_mid != 0) {
+
+                       REG_SET(OTG_V_TOTAL_MID, 0,
+                               OTG_V_TOTAL_MID, params->vertical_total_mid - 1);
+
+                       REG_UPDATE_2(OTG_V_TOTAL_CONTROL,
+                                       OTG_VTOTAL_MID_REPLACING_MAX_EN, 1,
+                                       OTG_VTOTAL_MID_FRAME_NUM,
+                                       (uint8_t)params->vertical_total_mid_frame_num);
+
+               }
+
+               optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1);
+
+               REG_UPDATE_5(OTG_V_TOTAL_CONTROL,
+                               OTG_V_TOTAL_MIN_SEL, 1,
+                               OTG_V_TOTAL_MAX_SEL, 1,
+                               OTG_FORCE_LOCK_ON_EVENT, 0,
+                               OTG_SET_V_TOTAL_MIN_MASK_EN, 0,
+                               OTG_SET_V_TOTAL_MIN_MASK, 0);
+               // Setup manual flow control for EOF via TRIG_A
+               optc->funcs->setup_manual_trigger(optc);
+
+       } else {
+               REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
+                               OTG_SET_V_TOTAL_MIN_MASK, 0,
+                               OTG_V_TOTAL_MIN_SEL, 0,
+                               OTG_V_TOTAL_MAX_SEL, 0,
+                               OTG_FORCE_LOCK_ON_EVENT, 0);
+
+               optc->funcs->set_vtotal_min_max(optc, 0, 0);
+       }
+}
+
+
+void optc301_setup_manual_trigger(struct timing_generator *optc)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       REG_SET_8(OTG_TRIGA_CNTL, 0,
+                       OTG_TRIGA_SOURCE_SELECT, 21,
+                       OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst,
+                       OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1,
+                       OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 0,
+                       OTG_TRIGA_POLARITY_SELECT, 0,
+                       OTG_TRIGA_FREQUENCY_SELECT, 0,
+                       OTG_TRIGA_DELAY, 0,
+                       OTG_TRIGA_CLEAR, 1);
+}
+
+static struct timing_generator_funcs dcn30_tg_funcs = {
+               .validate_timing = optc1_validate_timing,
+               .program_timing = optc1_program_timing,
+               .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
+               .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
+               .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
+               .program_global_sync = optc1_program_global_sync,
+               .enable_crtc = optc2_enable_crtc,
+               .disable_crtc = optc1_disable_crtc,
+               /* used by enable_timing_synchronization. Not need for FPGA */
+               .is_counter_moving = optc1_is_counter_moving,
+               .get_position = optc1_get_position,
+               .get_frame_count = optc1_get_vblank_counter,
+               .get_scanoutpos = optc1_get_crtc_scanoutpos,
+               .get_otg_active_size = optc1_get_otg_active_size,
+               .set_early_control = optc1_set_early_control,
+               /* used by enable_timing_synchronization. Not need for FPGA */
+               .wait_for_state = optc1_wait_for_state,
+               .set_blank_color = optc3_program_blank_color,
+               .did_triggered_reset_occur = optc1_did_triggered_reset_occur,
+               .triplebuffer_lock = optc3_triplebuffer_lock,
+               .triplebuffer_unlock = optc2_triplebuffer_unlock,
+               .enable_reset_trigger = optc1_enable_reset_trigger,
+               .enable_crtc_reset = optc1_enable_crtc_reset,
+               .disable_reset_trigger = optc1_disable_reset_trigger,
+               .lock = optc3_lock,
+               .unlock = optc1_unlock,
+               .lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,
+               .lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
+               .enable_optc_clock = optc1_enable_optc_clock,
+               .set_drr = optc301_set_drr,
+               .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
+               .set_vtotal_min_max = optc3_set_vtotal_min_max,
+               .set_static_screen_control = optc1_set_static_screen_control,
+               .program_stereo = optc1_program_stereo,
+               .is_stereo_left_eye = optc1_is_stereo_left_eye,
+               .tg_init = optc3_tg_init,
+               .is_tg_enabled = optc1_is_tg_enabled,
+               .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
+               .clear_optc_underflow = optc1_clear_optc_underflow,
+               .setup_global_swap_lock = NULL,
+               .get_crc = optc1_get_crc,
+               .configure_crc = optc2_configure_crc,
+               .set_dsc_config = optc3_set_dsc_config,
+               .get_dsc_status = optc2_get_dsc_status,
+               .set_dwb_source = NULL,
+               .set_odm_bypass = optc3_set_odm_bypass,
+               .set_odm_combine = optc3_set_odm_combine,
+               .get_optc_source = optc2_get_optc_source,
+               .set_out_mux = optc3_set_out_mux,
+               .set_drr_trigger_window = optc3_set_drr_trigger_window,
+               .set_vtotal_change_limit = optc3_set_vtotal_change_limit,
+               .set_gsl = optc2_set_gsl,
+               .set_gsl_source_select = optc2_set_gsl_source_select,
+               .set_vtg_params = optc1_set_vtg_params,
+               .program_manual_trigger = optc2_program_manual_trigger,
+               .setup_manual_trigger = optc301_setup_manual_trigger,
+               .get_hw_timing = optc1_get_hw_timing,
+               .wait_drr_doublebuffer_pending_clear = optc3_wait_drr_doublebuffer_pending_clear,
+};
+
+void dcn301_timing_generator_init(struct optc *optc1)
+{
+       optc1->base.funcs = &dcn30_tg_funcs;
+
+       optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
+       optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
+
+       optc1->min_h_blank = 32;
+       optc1->min_v_blank = 3;
+       optc1->min_v_blank_interlace = 5;
+       optc1->min_h_sync_width = 4;
+       optc1->min_v_sync_width = 1;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.h
new file mode 100644 (file)
index 0000000..b495856
--- /dev/null
@@ -0,0 +1,36 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_OPTC_DCN301_H__
+#define __DC_OPTC_DCN301_H__
+
+#include "dcn20/dcn20_optc.h"
+#include "dcn30/dcn30_optc.h"
+
+void dcn301_timing_generator_init(struct optc *optc1);
+void optc301_setup_manual_trigger(struct timing_generator *optc);
+void optc301_set_drr(struct timing_generator *optc, const struct drr_params *params);
+
+#endif /* __DC_OPTC_DCN301_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
new file mode 100644 (file)
index 0000000..63a677c
--- /dev/null
@@ -0,0 +1,310 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dcn31_optc.h"
+
+#include "dcn30/dcn30_optc.h"
+#include "reg_helper.h"
+#include "dc.h"
+#include "dcn_calc_math.h"
+
+#define REG(reg)\
+       optc1->tg_regs->reg
+
+#define CTX \
+       optc1->base.ctx
+
+#undef FN
+#define FN(reg_name, field_name) \
+       optc1->tg_shift->field_name, optc1->tg_mask->field_name
+
+static void optc31_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
+               struct dc_crtc_timing *timing)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+       int mpcc_hactive = (timing->h_addressable + timing->h_border_left + timing->h_border_right)
+                       / opp_cnt;
+       uint32_t memory_mask = 0;
+       int mem_count_per_opp = (mpcc_hactive + 2559) / 2560;
+
+       /* Assume less than 6 pipes */
+       if (opp_cnt == 4) {
+               if (mem_count_per_opp == 1)
+                       memory_mask = 0xf;
+               else {
+                       ASSERT(mem_count_per_opp == 2);
+                       memory_mask = 0xff;
+               }
+       } else if (mem_count_per_opp == 1)
+               memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2);
+       else if (mem_count_per_opp == 2)
+               memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);
+       else if (mem_count_per_opp == 3)
+               memory_mask = 0x77;
+       else if (mem_count_per_opp == 4)
+               memory_mask = 0xff;
+
+       if (REG(OPTC_MEMORY_CONFIG))
+               REG_SET(OPTC_MEMORY_CONFIG, 0,
+                       OPTC_MEM_SEL, memory_mask);
+
+       if (opp_cnt == 2) {
+               REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
+                               OPTC_NUM_OF_INPUT_SEGMENT, 1,
+                               OPTC_SEG0_SRC_SEL, opp_id[0],
+                               OPTC_SEG1_SRC_SEL, opp_id[1]);
+       } else if (opp_cnt == 4) {
+               REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
+                               OPTC_NUM_OF_INPUT_SEGMENT, 3,
+                               OPTC_SEG0_SRC_SEL, opp_id[0],
+                               OPTC_SEG1_SRC_SEL, opp_id[1],
+                               OPTC_SEG2_SRC_SEL, opp_id[2],
+                               OPTC_SEG3_SRC_SEL, opp_id[3]);
+       }
+
+       REG_UPDATE(OPTC_WIDTH_CONTROL,
+                       OPTC_SEGMENT_WIDTH, mpcc_hactive);
+
+       REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1);
+       optc1->opp_count = opp_cnt;
+}
+
+/*
+ * Enable CRTC - call ASIC Control Object to enable Timing generator.
+ */
+static bool optc31_enable_crtc(struct timing_generator *optc)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       /* opp instance for OTG, 1 to 1 mapping and odm will adjust */
+       REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
+                       OPTC_SEG0_SRC_SEL, optc->inst);
+
+       /* VTG enable first is for HW workaround */
+       REG_UPDATE(CONTROL,
+                       VTG0_ENABLE, 1);
+
+       REG_SEQ_START();
+
+       /* Enable CRTC */
+       REG_UPDATE_2(OTG_CONTROL,
+                       OTG_DISABLE_POINT_CNTL, 2,
+                       OTG_MASTER_EN, 1);
+
+       REG_SEQ_SUBMIT();
+       REG_SEQ_WAIT_DONE();
+
+       return true;
+}
+
+/* disable_crtc - call ASIC Control Object to disable Timing generator. */
+static bool optc31_disable_crtc(struct timing_generator *optc)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+       /* disable otg request until end of the first line
+        * in the vertical blank region
+        */
+       REG_UPDATE(OTG_CONTROL,
+                       OTG_MASTER_EN, 0);
+
+       REG_UPDATE(CONTROL,
+                       VTG0_ENABLE, 0);
+
+       /* CRTC disabled, so disable  clock. */
+       REG_WAIT(OTG_CLOCK_CONTROL,
+                       OTG_BUSY, 0,
+                       1, 100000);
+       optc1_clear_optc_underflow(optc);
+
+       return true;
+}
+
+bool optc31_immediate_disable_crtc(struct timing_generator *optc)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       REG_UPDATE_2(OTG_CONTROL,
+                       OTG_DISABLE_POINT_CNTL, 0,
+                       OTG_MASTER_EN, 0);
+
+       REG_UPDATE(CONTROL,
+                       VTG0_ENABLE, 0);
+
+       /* CRTC disabled, so disable  clock. */
+       REG_WAIT(OTG_CLOCK_CONTROL,
+                       OTG_BUSY, 0,
+                       1, 100000);
+
+       /* clear the false state */
+       optc1_clear_optc_underflow(optc);
+
+       return true;
+}
+
+void optc31_set_drr(
+       struct timing_generator *optc,
+       const struct drr_params *params)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       if (params != NULL &&
+               params->vertical_total_max > 0 &&
+               params->vertical_total_min > 0) {
+
+               if (params->vertical_total_mid != 0) {
+
+                       REG_SET(OTG_V_TOTAL_MID, 0,
+                               OTG_V_TOTAL_MID, params->vertical_total_mid - 1);
+
+                       REG_UPDATE_2(OTG_V_TOTAL_CONTROL,
+                                       OTG_VTOTAL_MID_REPLACING_MAX_EN, 1,
+                                       OTG_VTOTAL_MID_FRAME_NUM,
+                                       (uint8_t)params->vertical_total_mid_frame_num);
+
+               }
+
+               optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1);
+
+               /*
+                * MIN_MASK_EN is gone and MASK is now always enabled.
+                *
+                * To get it to it work with manual trigger we need to make sure
+                * we program the correct bit.
+                */
+               REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
+                               OTG_V_TOTAL_MIN_SEL, 1,
+                               OTG_V_TOTAL_MAX_SEL, 1,
+                               OTG_FORCE_LOCK_ON_EVENT, 0,
+                               OTG_SET_V_TOTAL_MIN_MASK, (1 << 1)); /* TRIGA */
+
+               // Setup manual flow control for EOF via TRIG_A
+               optc->funcs->setup_manual_trigger(optc);
+       } else {
+               REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
+                               OTG_SET_V_TOTAL_MIN_MASK, 0,
+                               OTG_V_TOTAL_MIN_SEL, 0,
+                               OTG_V_TOTAL_MAX_SEL, 0,
+                               OTG_FORCE_LOCK_ON_EVENT, 0);
+
+               optc->funcs->set_vtotal_min_max(optc, 0, 0);
+       }
+}
+
+void optc3_init_odm(struct timing_generator *optc)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
+                       OPTC_NUM_OF_INPUT_SEGMENT, 0,
+                       OPTC_SEG0_SRC_SEL, optc->inst,
+                       OPTC_SEG1_SRC_SEL, 0xf,
+                       OPTC_SEG2_SRC_SEL, 0xf,
+                       OPTC_SEG3_SRC_SEL, 0xf
+                       );
+
+       REG_SET(OTG_H_TIMING_CNTL, 0,
+                       OTG_H_TIMING_DIV_MODE, 0);
+
+       REG_SET(OPTC_MEMORY_CONFIG, 0,
+                       OPTC_MEM_SEL, 0);
+       optc1->opp_count = 1;
+}
+
+static struct timing_generator_funcs dcn31_tg_funcs = {
+               .validate_timing = optc1_validate_timing,
+               .program_timing = optc1_program_timing,
+               .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
+               .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
+               .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
+               .program_global_sync = optc1_program_global_sync,
+               .enable_crtc = optc31_enable_crtc,
+               .disable_crtc = optc31_disable_crtc,
+               .immediate_disable_crtc = optc31_immediate_disable_crtc,
+               /* used by enable_timing_synchronization. Not need for FPGA */
+               .is_counter_moving = optc1_is_counter_moving,
+               .get_position = optc1_get_position,
+               .get_frame_count = optc1_get_vblank_counter,
+               .get_scanoutpos = optc1_get_crtc_scanoutpos,
+               .get_otg_active_size = optc1_get_otg_active_size,
+               .set_early_control = optc1_set_early_control,
+               /* used by enable_timing_synchronization. Not need for FPGA */
+               .wait_for_state = optc1_wait_for_state,
+               .set_blank_color = optc3_program_blank_color,
+               .did_triggered_reset_occur = optc1_did_triggered_reset_occur,
+               .triplebuffer_lock = optc3_triplebuffer_lock,
+               .triplebuffer_unlock = optc2_triplebuffer_unlock,
+               .enable_reset_trigger = optc1_enable_reset_trigger,
+               .enable_crtc_reset = optc1_enable_crtc_reset,
+               .disable_reset_trigger = optc1_disable_reset_trigger,
+               .lock = optc3_lock,
+               .unlock = optc1_unlock,
+               .lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,
+               .lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
+               .enable_optc_clock = optc1_enable_optc_clock,
+               .set_drr = optc31_set_drr,
+               .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
+               .set_vtotal_min_max = optc1_set_vtotal_min_max,
+               .set_static_screen_control = optc1_set_static_screen_control,
+               .program_stereo = optc1_program_stereo,
+               .is_stereo_left_eye = optc1_is_stereo_left_eye,
+               .tg_init = optc3_tg_init,
+               .is_tg_enabled = optc1_is_tg_enabled,
+               .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
+               .clear_optc_underflow = optc1_clear_optc_underflow,
+               .setup_global_swap_lock = NULL,
+               .get_crc = optc1_get_crc,
+               .configure_crc = optc2_configure_crc,
+               .set_dsc_config = optc3_set_dsc_config,
+               .get_dsc_status = optc2_get_dsc_status,
+               .set_dwb_source = NULL,
+               .set_odm_bypass = optc3_set_odm_bypass,
+               .set_odm_combine = optc31_set_odm_combine,
+               .get_optc_source = optc2_get_optc_source,
+               .set_out_mux = optc3_set_out_mux,
+               .set_drr_trigger_window = optc3_set_drr_trigger_window,
+               .set_vtotal_change_limit = optc3_set_vtotal_change_limit,
+               .set_gsl = optc2_set_gsl,
+               .set_gsl_source_select = optc2_set_gsl_source_select,
+               .set_vtg_params = optc1_set_vtg_params,
+               .program_manual_trigger = optc2_program_manual_trigger,
+               .setup_manual_trigger = optc2_setup_manual_trigger,
+               .get_hw_timing = optc1_get_hw_timing,
+               .init_odm = optc3_init_odm,
+};
+
+void dcn31_timing_generator_init(struct optc *optc1)
+{
+       optc1->base.funcs = &dcn31_tg_funcs;
+
+       optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
+       optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
+
+       optc1->min_h_blank = 32;
+       optc1->min_v_blank = 3;
+       optc1->min_v_blank_interlace = 5;
+       optc1->min_h_sync_width = 4;
+       optc1->min_v_sync_width = 1;
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
new file mode 100644 (file)
index 0000000..30b81a4
--- /dev/null
@@ -0,0 +1,267 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_OPTC_DCN31_H__
+#define __DC_OPTC_DCN31_H__
+
+#include "dcn10/dcn10_optc.h"
+
+#define OPTC_COMMON_REG_LIST_DCN3_1(inst) \
+       SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
+       SRI(OTG_VUPDATE_PARAM, OTG, inst),\
+       SRI(OTG_VREADY_PARAM, OTG, inst),\
+       SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
+       SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
+       SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
+       SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
+       SRI(OTG_GLOBAL_CONTROL4, OTG, inst),\
+       SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
+       SRI(OTG_H_TOTAL, OTG, inst),\
+       SRI(OTG_H_BLANK_START_END, OTG, inst),\
+       SRI(OTG_H_SYNC_A, OTG, inst),\
+       SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\
+       SRI(OTG_H_TIMING_CNTL, OTG, inst),\
+       SRI(OTG_V_TOTAL, OTG, inst),\
+       SRI(OTG_V_BLANK_START_END, OTG, inst),\
+       SRI(OTG_V_SYNC_A, OTG, inst),\
+       SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\
+       SRI(OTG_CONTROL, OTG, inst),\
+       SRI(OTG_STEREO_CONTROL, OTG, inst),\
+       SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\
+       SRI(OTG_STEREO_STATUS, OTG, inst),\
+       SRI(OTG_V_TOTAL_MAX, OTG, inst),\
+       SRI(OTG_V_TOTAL_MIN, OTG, inst),\
+       SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\
+       SRI(OTG_TRIGA_CNTL, OTG, inst),\
+       SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\
+       SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\
+       SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\
+       SRI(OTG_STATUS, OTG, inst),\
+       SRI(OTG_STATUS_POSITION, OTG, inst),\
+       SRI(OTG_NOM_VERT_POSITION, OTG, inst),\
+       SRI(OTG_M_CONST_DTO0, OTG, inst),\
+       SRI(OTG_M_CONST_DTO1, OTG, inst),\
+       SRI(OTG_CLOCK_CONTROL, OTG, inst),\
+       SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\
+       SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\
+       SRI(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\
+       SRI(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\
+       SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\
+       SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\
+       SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\
+       SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\
+       SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\
+       SRI(CONTROL, VTG, inst),\
+       SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\
+       SRI(OTG_GSL_CONTROL, OTG, inst),\
+       SRI(OTG_CRC_CNTL, OTG, inst),\
+       SRI(OTG_CRC0_DATA_RG, OTG, inst),\
+       SRI(OTG_CRC0_DATA_B, OTG, inst),\
+       SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\
+       SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\
+       SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\
+       SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\
+       SR(GSL_SOURCE_SELECT),\
+       SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst),\
+       SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
+       SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
+       SRI(OTG_GSL_WINDOW_X, OTG, inst),\
+       SRI(OTG_GSL_WINDOW_Y, OTG, inst),\
+       SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\
+       SRI(OTG_DSC_START_POSITION, OTG, inst),\
+       SRI(OTG_DRR_TRIGGER_WINDOW, OTG, inst),\
+       SRI(OTG_DRR_V_TOTAL_CHANGE, OTG, inst),\
+       SRI(OPTC_DATA_FORMAT_CONTROL, ODM, inst),\
+       SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\
+       SRI(OPTC_WIDTH_CONTROL, ODM, inst),\
+       SRI(OPTC_MEMORY_CONFIG, ODM, inst),\
+       SRI(OTG_CRC_CNTL2, OTG, inst),\
+       SR(DWB_SOURCE_SELECT),\
+       SRI(OTG_DRR_CONTROL, OTG, inst)
+
+#define OPTC_COMMON_MASK_SH_LIST_DCN3_1(mask_sh)\
+       SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
+       SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
+       SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
+       SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
+       SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\
+       SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_START_X, mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_END_X, mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_START_Y, mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_END_Y, mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL2, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_X, mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_Y, mask_sh),\
+       SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\
+       SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
+       SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_START, mask_sh),\
+       SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_END, mask_sh),\
+       SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_START, mask_sh),\
+       SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_END, mask_sh),\
+       SF(OTG0_OTG_H_SYNC_A_CNTL, OTG_H_SYNC_A_POL, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
+       SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_START, mask_sh),\
+       SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_END, mask_sh),\
+       SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_START, mask_sh),\
+       SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_END, mask_sh),\
+       SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_A_POL, mask_sh),\
+       SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, mask_sh),\
+       SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
+       SF(OTG0_OTG_CONTROL, OTG_START_POINT_CNTL, mask_sh),\
+       SF(OTG0_OTG_CONTROL, OTG_DISABLE_POINT_CNTL, mask_sh),\
+       SF(OTG0_OTG_CONTROL, OTG_FIELD_NUMBER_CNTL, mask_sh),\
+       SF(OTG0_OTG_CONTROL, OTG_OUT_MUX, mask_sh),\
+       SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EN, mask_sh),\
+       SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_LINE_NUM, mask_sh),\
+       SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_POLARITY, mask_sh),\
+       SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EYE_FLAG_POLARITY, mask_sh),\
+       SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\
+       SF(OTG0_OTG_STEREO_STATUS, OTG_STEREO_CURRENT_EYE, mask_sh),\
+       SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_EN, mask_sh),\
+       SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\
+       SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MIN_EN, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\
+       SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\
+       SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\
+       SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\
+       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_SELECT, mask_sh),\
+       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_PIPE_SELECT, mask_sh),\
+       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_RISING_EDGE_DETECT_CNTL, mask_sh),\
+       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, mask_sh),\
+       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_POLARITY_SELECT, mask_sh),\
+       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FREQUENCY_SELECT, mask_sh),\
+       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_DELAY, mask_sh),\
+       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_CLEAR, mask_sh),\
+       SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_EVENT_MASK, mask_sh),\
+       SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_FRAME_COUNT, mask_sh),\
+       SF(OTG0_OTG_STATUS_FRAME_COUNT, OTG_FRAME_COUNT, mask_sh),\
+       SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
+       SF(OTG0_OTG_STATUS, OTG_V_ACTIVE_DISP, mask_sh),\
+       SF(OTG0_OTG_STATUS_POSITION, OTG_HORZ_COUNT, mask_sh),\
+       SF(OTG0_OTG_STATUS_POSITION, OTG_VERT_COUNT, mask_sh),\
+       SF(OTG0_OTG_NOM_VERT_POSITION, OTG_VERT_COUNT_NOM, mask_sh),\
+       SF(OTG0_OTG_M_CONST_DTO0, OTG_M_CONST_DTO_PHASE, mask_sh),\
+       SF(OTG0_OTG_M_CONST_DTO1, OTG_M_CONST_DTO_MODULO, mask_sh),\
+       SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\
+       SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\
+       SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\
+       SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\
+       SF(OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE, mask_sh),\
+       SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_START, mask_sh),\
+       SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_END, mask_sh),\
+       SF(OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_INT_ENABLE, mask_sh),\
+       SF(OTG0_OTG_VERTICAL_INTERRUPT1_POSITION, OTG_VERTICAL_INTERRUPT1_LINE_START, mask_sh),\
+       SF(OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE, mask_sh),\
+       SF(OTG0_OTG_VERTICAL_INTERRUPT2_POSITION, OTG_VERTICAL_INTERRUPT2_LINE_START, mask_sh),\
+       SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\
+       SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\
+       SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\
+       SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\
+       SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\
+       SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
+       SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
+       SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
+       SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, mask_sh),\
+       SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, mask_sh),\
+       SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_AUTO_FORCE_VSYNC_MODE, mask_sh),\
+       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL0_EN, mask_sh),\
+       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL1_EN, mask_sh),\
+       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL2_EN, mask_sh),\
+       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_EN, mask_sh),\
+       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_FORCE_DELAY, mask_sh),\
+       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\
+       SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\
+       SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\
+       SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
+       SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\
+       SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\
+       SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\
+       SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_START, mask_sh),\
+       SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_END, mask_sh),\
+       SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_START, mask_sh),\
+       SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_END, mask_sh),\
+       SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_START, mask_sh),\
+       SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\
+       SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\
+       SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\
+       SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\
+       SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\
+       SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\
+       SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\
+       SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\
+       SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \
+       SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\
+       SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\
+       SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, mask_sh), \
+       SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, mask_sh), \
+       SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, mask_sh), \
+       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_MODE, mask_sh), \
+       SF(OTG0_OTG_GSL_CONTROL, OTG_MASTER_UPDATE_LOCK_GSL_EN, mask_sh), \
+       SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_X, mask_sh), \
+       SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_LINE_NUM, mask_sh),\
+       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG0_SRC_SEL, mask_sh),\
+       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG1_SRC_SEL, mask_sh),\
+       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG2_SRC_SEL, mask_sh),\
+       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG3_SRC_SEL, mask_sh),\
+       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, mask_sh),\
+       SF(ODM0_OPTC_MEMORY_CONFIG, OPTC_MEM_SEL, mask_sh),\
+       SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, mask_sh),\
+       SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\
+       SF(ODM0_OPTC_BYTES_PER_PIXEL, OPTC_DSC_BYTES_PER_PIXEL, mask_sh),\
+       SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, mask_sh),\
+       SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_SEGMENT_WIDTH, mask_sh),\
+       SF(DWB_SOURCE_SELECT, OPTC_DWB0_SOURCE_SELECT, mask_sh),\
+       SF(DWB_SOURCE_SELECT, OPTC_DWB1_SOURCE_SELECT, mask_sh),\
+       SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_START_X, mask_sh),\
+       SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_END_X, mask_sh),\
+       SF(OTG0_OTG_DRR_V_TOTAL_CHANGE, OTG_DRR_V_TOTAL_CHANGE_LIMIT, mask_sh),\
+       SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\
+       SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh),\
+       SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DSC_MODE, mask_sh),\
+       SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_COMBINE_MODE, mask_sh),\
+       SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_SPLIT_MODE, mask_sh),\
+       SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_FORMAT, mask_sh),\
+       SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh)
+
+void dcn31_timing_generator_init(struct optc *optc1);
+
+bool optc31_immediate_disable_crtc(struct timing_generator *optc);
+
+void optc31_set_drr(struct timing_generator *optc, const struct drr_params *params);
+
+void optc3_init_odm(struct timing_generator *optc);
+
+#endif /* __DC_OPTC_DCN31_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c
new file mode 100644 (file)
index 0000000..0086caf
--- /dev/null
@@ -0,0 +1,273 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dcn314_optc.h"
+
+#include "dcn30/dcn30_optc.h"
+#include "dcn31/dcn31_optc.h"
+#include "reg_helper.h"
+#include "dc.h"
+#include "dcn_calc_math.h"
+
+#define REG(reg)\
+       optc1->tg_regs->reg
+
+#define CTX \
+       optc1->base.ctx
+
+#undef FN
+#define FN(reg_name, field_name) \
+       optc1->tg_shift->field_name, optc1->tg_mask->field_name
+
+/*
+ * Enable CRTC
+ * Enable CRTC - call ASIC Control Object to enable Timing generator.
+ */
+
+static void optc314_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
+               struct dc_crtc_timing *timing)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+       uint32_t memory_mask = 0;
+       int h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right;
+       int mpcc_hactive = h_active / opp_cnt;
+       /* Each memory instance is 2048x(314x2) bits to support half line of 4096 */
+       int odm_mem_count = (h_active + 2047) / 2048;
+
+       /*
+        * display <= 4k : 2 memories + 2 pipes
+        * 4k < display <= 8k : 4 memories + 2 pipes
+        * 8k < display <= 12k : 6 memories + 4 pipes
+        */
+       if (opp_cnt == 4) {
+               if (odm_mem_count <= 2)
+                       memory_mask = 0x3;
+               else if (odm_mem_count <= 4)
+                       memory_mask = 0xf;
+               else
+                       memory_mask = 0x3f;
+       } else {
+               if (odm_mem_count <= 2)
+                       memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2);
+               else if (odm_mem_count <= 4)
+                       memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);
+               else
+                       memory_mask = 0x77;
+       }
+
+       REG_SET(OPTC_MEMORY_CONFIG, 0,
+               OPTC_MEM_SEL, memory_mask);
+
+       if (opp_cnt == 2) {
+               REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
+                               OPTC_NUM_OF_INPUT_SEGMENT, 1,
+                               OPTC_SEG0_SRC_SEL, opp_id[0],
+                               OPTC_SEG1_SRC_SEL, opp_id[1]);
+       } else if (opp_cnt == 4) {
+               REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
+                               OPTC_NUM_OF_INPUT_SEGMENT, 3,
+                               OPTC_SEG0_SRC_SEL, opp_id[0],
+                               OPTC_SEG1_SRC_SEL, opp_id[1],
+                               OPTC_SEG2_SRC_SEL, opp_id[2],
+                               OPTC_SEG3_SRC_SEL, opp_id[3]);
+       }
+
+       REG_UPDATE(OPTC_WIDTH_CONTROL,
+                       OPTC_SEGMENT_WIDTH, mpcc_hactive);
+
+       REG_UPDATE(OTG_H_TIMING_CNTL,
+                       OTG_H_TIMING_DIV_MODE, opp_cnt - 1);
+       optc1->opp_count = opp_cnt;
+}
+
+static bool optc314_enable_crtc(struct timing_generator *optc)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       /* opp instance for OTG, 1 to 1 mapping and odm will adjust */
+       REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
+                       OPTC_SEG0_SRC_SEL, optc->inst);
+
+       /* VTG enable first is for HW workaround */
+       REG_UPDATE(CONTROL,
+                       VTG0_ENABLE, 1);
+
+       REG_SEQ_START();
+
+       /* Enable CRTC */
+       REG_UPDATE_2(OTG_CONTROL,
+                       OTG_DISABLE_POINT_CNTL, 2,
+                       OTG_MASTER_EN, 1);
+
+       REG_SEQ_SUBMIT();
+       REG_SEQ_WAIT_DONE();
+
+       return true;
+}
+
+/* disable_crtc */
+static bool optc314_disable_crtc(struct timing_generator *optc)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       /* disable otg request until end of the first line
+        * in the vertical blank region
+        */
+       REG_UPDATE(OTG_CONTROL,
+                       OTG_MASTER_EN, 0);
+
+       REG_UPDATE(CONTROL,
+                       VTG0_ENABLE, 0);
+
+       /* CRTC disabled, so disable  clock. */
+       REG_WAIT(OTG_CLOCK_CONTROL,
+                       OTG_BUSY, 0,
+                       1, 100000);
+
+       return true;
+}
+
+static void optc314_phantom_crtc_post_enable(struct timing_generator *optc)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       /* Disable immediately. */
+       REG_UPDATE_2(OTG_CONTROL, OTG_DISABLE_POINT_CNTL, 0, OTG_MASTER_EN, 0);
+
+       /* CRTC disabled, so disable  clock. */
+       REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 100000);
+}
+
+static void optc314_set_odm_bypass(struct timing_generator *optc,
+               const struct dc_crtc_timing *dc_crtc_timing)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+       enum h_timing_div_mode h_div = H_TIMING_NO_DIV;
+
+       REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
+                       OPTC_NUM_OF_INPUT_SEGMENT, 0,
+                       OPTC_SEG0_SRC_SEL, optc->inst,
+                       OPTC_SEG1_SRC_SEL, 0xf,
+                       OPTC_SEG2_SRC_SEL, 0xf,
+                       OPTC_SEG3_SRC_SEL, 0xf
+                       );
+
+       h_div = optc1_is_two_pixels_per_containter(dc_crtc_timing);
+       REG_UPDATE(OTG_H_TIMING_CNTL,
+                       OTG_H_TIMING_DIV_MODE, h_div);
+
+       REG_SET(OPTC_MEMORY_CONFIG, 0,
+                       OPTC_MEM_SEL, 0);
+       optc1->opp_count = 1;
+}
+
+static void optc314_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       REG_UPDATE(OTG_H_TIMING_CNTL,
+                       OTG_H_TIMING_DIV_MODE_MANUAL, manual_mode ? 1 : 0);
+}
+
+
+static struct timing_generator_funcs dcn314_tg_funcs = {
+               .validate_timing = optc1_validate_timing,
+               .program_timing = optc1_program_timing,
+               .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
+               .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
+               .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
+               .program_global_sync = optc1_program_global_sync,
+               .enable_crtc = optc314_enable_crtc,
+               .disable_crtc = optc314_disable_crtc,
+               .immediate_disable_crtc = optc31_immediate_disable_crtc,
+               .phantom_crtc_post_enable = optc314_phantom_crtc_post_enable,
+               /* used by enable_timing_synchronization. Not need for FPGA */
+               .is_counter_moving = optc1_is_counter_moving,
+               .get_position = optc1_get_position,
+               .get_frame_count = optc1_get_vblank_counter,
+               .get_scanoutpos = optc1_get_crtc_scanoutpos,
+               .get_otg_active_size = optc1_get_otg_active_size,
+               .set_early_control = optc1_set_early_control,
+               /* used by enable_timing_synchronization. Not need for FPGA */
+               .wait_for_state = optc1_wait_for_state,
+               .set_blank_color = optc3_program_blank_color,
+               .did_triggered_reset_occur = optc1_did_triggered_reset_occur,
+               .triplebuffer_lock = optc3_triplebuffer_lock,
+               .triplebuffer_unlock = optc2_triplebuffer_unlock,
+               .enable_reset_trigger = optc1_enable_reset_trigger,
+               .enable_crtc_reset = optc1_enable_crtc_reset,
+               .disable_reset_trigger = optc1_disable_reset_trigger,
+               .lock = optc3_lock,
+               .unlock = optc1_unlock,
+               .lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,
+               .lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
+               .enable_optc_clock = optc1_enable_optc_clock,
+               .set_drr = optc31_set_drr,
+               .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
+               .set_vtotal_min_max = optc1_set_vtotal_min_max,
+               .set_static_screen_control = optc1_set_static_screen_control,
+               .program_stereo = optc1_program_stereo,
+               .is_stereo_left_eye = optc1_is_stereo_left_eye,
+               .tg_init = optc3_tg_init,
+               .is_tg_enabled = optc1_is_tg_enabled,
+               .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
+               .clear_optc_underflow = optc1_clear_optc_underflow,
+               .setup_global_swap_lock = NULL,
+               .get_crc = optc1_get_crc,
+               .configure_crc = optc1_configure_crc,
+               .set_dsc_config = optc3_set_dsc_config,
+               .get_dsc_status = optc2_get_dsc_status,
+               .set_dwb_source = NULL,
+               .get_optc_source = optc2_get_optc_source,
+               .set_out_mux = optc3_set_out_mux,
+               .set_drr_trigger_window = optc3_set_drr_trigger_window,
+               .set_vtotal_change_limit = optc3_set_vtotal_change_limit,
+               .set_gsl = optc2_set_gsl,
+               .set_gsl_source_select = optc2_set_gsl_source_select,
+               .set_vtg_params = optc1_set_vtg_params,
+               .program_manual_trigger = optc2_program_manual_trigger,
+               .setup_manual_trigger = optc2_setup_manual_trigger,
+               .get_hw_timing = optc1_get_hw_timing,
+               .init_odm = optc3_init_odm,
+               .set_odm_bypass = optc314_set_odm_bypass,
+               .set_odm_combine = optc314_set_odm_combine,
+               .set_h_timing_div_manual_mode = optc314_set_h_timing_div_manual_mode,
+};
+
+void dcn314_timing_generator_init(struct optc *optc1)
+{
+       optc1->base.funcs = &dcn314_tg_funcs;
+
+       optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
+       optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
+
+       optc1->min_h_blank = 32;
+       optc1->min_v_blank = 3;
+       optc1->min_v_blank_interlace = 5;
+       optc1->min_h_sync_width = 4;
+       optc1->min_v_sync_width = 1;
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
new file mode 100644 (file)
index 0000000..99c098e
--- /dev/null
@@ -0,0 +1,255 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_OPTC_DCN314_H__
+#define __DC_OPTC_DCN314_H__
+
+#include "dcn10/dcn10_optc.h"
+
+#define OPTC_COMMON_REG_LIST_DCN3_14(inst) \
+       SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
+       SRI(OTG_VUPDATE_PARAM, OTG, inst),\
+       SRI(OTG_VREADY_PARAM, OTG, inst),\
+       SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
+       SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
+       SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
+       SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
+       SRI(OTG_GLOBAL_CONTROL4, OTG, inst),\
+       SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
+       SRI(OTG_H_TOTAL, OTG, inst),\
+       SRI(OTG_H_BLANK_START_END, OTG, inst),\
+       SRI(OTG_H_SYNC_A, OTG, inst),\
+       SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\
+       SRI(OTG_H_TIMING_CNTL, OTG, inst),\
+       SRI(OTG_V_TOTAL, OTG, inst),\
+       SRI(OTG_V_BLANK_START_END, OTG, inst),\
+       SRI(OTG_V_SYNC_A, OTG, inst),\
+       SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\
+       SRI(OTG_CONTROL, OTG, inst),\
+       SRI(OTG_STEREO_CONTROL, OTG, inst),\
+       SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\
+       SRI(OTG_STEREO_STATUS, OTG, inst),\
+       SRI(OTG_V_TOTAL_MAX, OTG, inst),\
+       SRI(OTG_V_TOTAL_MIN, OTG, inst),\
+       SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\
+       SRI(OTG_TRIGA_CNTL, OTG, inst),\
+       SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\
+       SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\
+       SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\
+       SRI(OTG_STATUS, OTG, inst),\
+       SRI(OTG_STATUS_POSITION, OTG, inst),\
+       SRI(OTG_NOM_VERT_POSITION, OTG, inst),\
+       SRI(OTG_M_CONST_DTO0, OTG, inst),\
+       SRI(OTG_M_CONST_DTO1, OTG, inst),\
+       SRI(OTG_CLOCK_CONTROL, OTG, inst),\
+       SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\
+       SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\
+       SRI(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\
+       SRI(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\
+       SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\
+       SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\
+       SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\
+       SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\
+       SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\
+       SRI(CONTROL, VTG, inst),\
+       SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\
+       SRI(OTG_GSL_CONTROL, OTG, inst),\
+       SRI(OTG_CRC_CNTL, OTG, inst),\
+       SRI(OTG_CRC0_DATA_RG, OTG, inst),\
+       SRI(OTG_CRC0_DATA_B, OTG, inst),\
+       SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\
+       SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\
+       SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\
+       SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\
+       SR(GSL_SOURCE_SELECT),\
+       SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst),\
+       SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
+       SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
+       SRI(OTG_GSL_WINDOW_X, OTG, inst),\
+       SRI(OTG_GSL_WINDOW_Y, OTG, inst),\
+       SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\
+       SRI(OTG_DSC_START_POSITION, OTG, inst),\
+       SRI(OTG_DRR_TRIGGER_WINDOW, OTG, inst),\
+       SRI(OTG_DRR_V_TOTAL_CHANGE, OTG, inst),\
+       SRI(OPTC_DATA_FORMAT_CONTROL, ODM, inst),\
+       SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\
+       SRI(OPTC_WIDTH_CONTROL, ODM, inst),\
+       SRI(OPTC_MEMORY_CONFIG, ODM, inst),\
+       SRI(OTG_DRR_CONTROL, OTG, inst)
+
+#define OPTC_COMMON_MASK_SH_LIST_DCN3_14(mask_sh)\
+       SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
+       SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
+       SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
+       SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
+       SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\
+       SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_START_X, mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_END_X, mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_START_Y, mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_END_Y, mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL2, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_X, mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_Y, mask_sh),\
+       SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\
+       SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
+       SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_START, mask_sh),\
+       SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_END, mask_sh),\
+       SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_START, mask_sh),\
+       SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_END, mask_sh),\
+       SF(OTG0_OTG_H_SYNC_A_CNTL, OTG_H_SYNC_A_POL, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
+       SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_START, mask_sh),\
+       SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_END, mask_sh),\
+       SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_START, mask_sh),\
+       SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_END, mask_sh),\
+       SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_A_POL, mask_sh),\
+       SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, mask_sh),\
+       SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
+       SF(OTG0_OTG_CONTROL, OTG_START_POINT_CNTL, mask_sh),\
+       SF(OTG0_OTG_CONTROL, OTG_DISABLE_POINT_CNTL, mask_sh),\
+       SF(OTG0_OTG_CONTROL, OTG_FIELD_NUMBER_CNTL, mask_sh),\
+       SF(OTG0_OTG_CONTROL, OTG_OUT_MUX, mask_sh),\
+       SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EN, mask_sh),\
+       SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_LINE_NUM, mask_sh),\
+       SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_POLARITY, mask_sh),\
+       SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EYE_FLAG_POLARITY, mask_sh),\
+       SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\
+       SF(OTG0_OTG_STEREO_STATUS, OTG_STEREO_CURRENT_EYE, mask_sh),\
+       SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_EN, mask_sh),\
+       SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\
+       SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MIN_EN, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\
+       SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\
+       SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\
+       SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\
+       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_SELECT, mask_sh),\
+       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_PIPE_SELECT, mask_sh),\
+       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_RISING_EDGE_DETECT_CNTL, mask_sh),\
+       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, mask_sh),\
+       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_POLARITY_SELECT, mask_sh),\
+       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FREQUENCY_SELECT, mask_sh),\
+       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_DELAY, mask_sh),\
+       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_CLEAR, mask_sh),\
+       SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_EVENT_MASK, mask_sh),\
+       SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_FRAME_COUNT, mask_sh),\
+       SF(OTG0_OTG_STATUS_FRAME_COUNT, OTG_FRAME_COUNT, mask_sh),\
+       SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
+       SF(OTG0_OTG_STATUS, OTG_V_ACTIVE_DISP, mask_sh),\
+       SF(OTG0_OTG_STATUS_POSITION, OTG_HORZ_COUNT, mask_sh),\
+       SF(OTG0_OTG_STATUS_POSITION, OTG_VERT_COUNT, mask_sh),\
+       SF(OTG0_OTG_NOM_VERT_POSITION, OTG_VERT_COUNT_NOM, mask_sh),\
+       SF(OTG0_OTG_M_CONST_DTO0, OTG_M_CONST_DTO_PHASE, mask_sh),\
+       SF(OTG0_OTG_M_CONST_DTO1, OTG_M_CONST_DTO_MODULO, mask_sh),\
+       SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\
+       SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\
+       SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\
+       SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\
+       SF(OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE, mask_sh),\
+       SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_START, mask_sh),\
+       SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_END, mask_sh),\
+       SF(OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_INT_ENABLE, mask_sh),\
+       SF(OTG0_OTG_VERTICAL_INTERRUPT1_POSITION, OTG_VERTICAL_INTERRUPT1_LINE_START, mask_sh),\
+       SF(OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE, mask_sh),\
+       SF(OTG0_OTG_VERTICAL_INTERRUPT2_POSITION, OTG_VERTICAL_INTERRUPT2_LINE_START, mask_sh),\
+       SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\
+       SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\
+       SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\
+       SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\
+       SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\
+       SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
+       SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
+       SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
+       SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, mask_sh),\
+       SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, mask_sh),\
+       SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_AUTO_FORCE_VSYNC_MODE, mask_sh),\
+       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL0_EN, mask_sh),\
+       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL1_EN, mask_sh),\
+       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL2_EN, mask_sh),\
+       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_EN, mask_sh),\
+       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_FORCE_DELAY, mask_sh),\
+       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\
+       SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\
+       SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\
+       SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
+       SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\
+       SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\
+       SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\
+       SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_START, mask_sh),\
+       SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_END, mask_sh),\
+       SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_START, mask_sh),\
+       SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_END, mask_sh),\
+       SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_START, mask_sh),\
+       SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\
+       SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\
+       SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\
+       SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\
+       SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\
+       SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\
+       SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\
+       SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\
+       SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \
+       SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\
+       SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\
+       SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, mask_sh), \
+       SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, mask_sh), \
+       SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, mask_sh), \
+       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_MODE, mask_sh), \
+       SF(OTG0_OTG_GSL_CONTROL, OTG_MASTER_UPDATE_LOCK_GSL_EN, mask_sh), \
+       SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_X, mask_sh), \
+       SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_LINE_NUM, mask_sh),\
+       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG0_SRC_SEL, mask_sh),\
+       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG1_SRC_SEL, mask_sh),\
+       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG2_SRC_SEL, mask_sh),\
+       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG3_SRC_SEL, mask_sh),\
+       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, mask_sh),\
+       SF(ODM0_OPTC_MEMORY_CONFIG, OPTC_MEM_SEL, mask_sh),\
+       SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, mask_sh),\
+       SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\
+       SF(ODM0_OPTC_BYTES_PER_PIXEL, OPTC_DSC_BYTES_PER_PIXEL, mask_sh),\
+       SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, mask_sh),\
+       SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_SEGMENT_WIDTH, mask_sh),\
+       SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_START_X, mask_sh),\
+       SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_END_X, mask_sh),\
+       SF(OTG0_OTG_DRR_V_TOTAL_CHANGE, OTG_DRR_V_TOTAL_CHANGE_LIMIT, mask_sh),\
+       SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\
+       SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE_MANUAL, mask_sh),\
+       SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh),\
+       SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh)
+
+void dcn314_timing_generator_init(struct optc *optc1);
+
+#endif /* __DC_OPTC_DCN314_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c
new file mode 100644 (file)
index 0000000..a2c4db2
--- /dev/null
@@ -0,0 +1,357 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dcn32_optc.h"
+
+#include "dcn30/dcn30_optc.h"
+#include "dcn31/dcn31_optc.h"
+#include "reg_helper.h"
+#include "dc.h"
+#include "dcn_calc_math.h"
+#include "dc_dmub_srv.h"
+
+#define REG(reg)\
+       optc1->tg_regs->reg
+
+#define CTX \
+       optc1->base.ctx
+
+#undef FN
+#define FN(reg_name, field_name) \
+       optc1->tg_shift->field_name, optc1->tg_mask->field_name
+
+static void optc32_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
+               struct dc_crtc_timing *timing)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+       uint32_t memory_mask = 0;
+       int h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right;
+       int mpcc_hactive = h_active / opp_cnt;
+       /* Each memory instance is 2048x(32x2) bits to support half line of 4096 */
+       int odm_mem_count = (h_active + 2047) / 2048;
+
+       /*
+        * display <= 4k : 2 memories + 2 pipes
+        * 4k < display <= 8k : 4 memories + 2 pipes
+        * 8k < display <= 12k : 6 memories + 4 pipes
+        */
+       if (opp_cnt == 4) {
+               if (odm_mem_count <= 2)
+                       memory_mask = 0x3;
+               else if (odm_mem_count <= 4)
+                       memory_mask = 0xf;
+               else
+                       memory_mask = 0x3f;
+       } else {
+               if (odm_mem_count <= 2)
+                       memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2);
+               else if (odm_mem_count <= 4)
+                       memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);
+               else
+                       memory_mask = 0x77;
+       }
+
+       REG_SET(OPTC_MEMORY_CONFIG, 0,
+               OPTC_MEM_SEL, memory_mask);
+
+       if (opp_cnt == 2) {
+               REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
+                               OPTC_NUM_OF_INPUT_SEGMENT, 1,
+                               OPTC_SEG0_SRC_SEL, opp_id[0],
+                               OPTC_SEG1_SRC_SEL, opp_id[1]);
+       } else if (opp_cnt == 4) {
+               REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
+                               OPTC_NUM_OF_INPUT_SEGMENT, 3,
+                               OPTC_SEG0_SRC_SEL, opp_id[0],
+                               OPTC_SEG1_SRC_SEL, opp_id[1],
+                               OPTC_SEG2_SRC_SEL, opp_id[2],
+                               OPTC_SEG3_SRC_SEL, opp_id[3]);
+       }
+
+       REG_UPDATE(OPTC_WIDTH_CONTROL,
+                       OPTC_SEGMENT_WIDTH, mpcc_hactive);
+
+       REG_UPDATE(OTG_H_TIMING_CNTL,
+                       OTG_H_TIMING_DIV_MODE, opp_cnt - 1);
+       optc1->opp_count = opp_cnt;
+}
+
+void optc32_get_odm_combine_segments(struct timing_generator *tg, int *odm_combine_segments)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(tg);
+       int segments;
+
+       REG_GET(OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, &segments);
+
+       switch (segments) {
+       case 0:
+               *odm_combine_segments = 1;
+               break;
+       case 1:
+               *odm_combine_segments = 2;
+               break;
+       case 3:
+               *odm_combine_segments = 4;
+               break;
+       /* 2 is reserved */
+       case 2:
+       default:
+               *odm_combine_segments = -1;
+       }
+}
+
+void optc32_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       REG_UPDATE(OTG_H_TIMING_CNTL,
+                       OTG_H_TIMING_DIV_MODE_MANUAL, manual_mode ? 1 : 0);
+}
+/**
+ * optc32_enable_crtc() - Enable CRTC - call ASIC Control Object to enable Timing generator.
+ *
+ * @optc: timing_generator instance.
+ *
+ * Return: If CRTC is enabled, return true.
+ */
+static bool optc32_enable_crtc(struct timing_generator *optc)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       /* opp instance for OTG, 1 to 1 mapping and odm will adjust */
+       REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
+                       OPTC_SEG0_SRC_SEL, optc->inst);
+
+       /* VTG enable first is for HW workaround */
+       REG_UPDATE(CONTROL,
+                       VTG0_ENABLE, 1);
+
+       REG_SEQ_START();
+
+       /* Enable CRTC */
+       REG_UPDATE_2(OTG_CONTROL,
+                       OTG_DISABLE_POINT_CNTL, 2,
+                       OTG_MASTER_EN, 1);
+
+       REG_SEQ_SUBMIT();
+       REG_SEQ_WAIT_DONE();
+
+       return true;
+}
+
+/* disable_crtc */
+static bool optc32_disable_crtc(struct timing_generator *optc)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       /* disable otg request until end of the first line
+        * in the vertical blank region
+        */
+       REG_UPDATE(OTG_CONTROL,
+                       OTG_MASTER_EN, 0);
+
+       REG_UPDATE(CONTROL,
+                       VTG0_ENABLE, 0);
+
+       /* CRTC disabled, so disable  clock. */
+       REG_WAIT(OTG_CLOCK_CONTROL,
+                       OTG_BUSY, 0,
+                       1, 150000);
+
+       return true;
+}
+
+static void optc32_phantom_crtc_post_enable(struct timing_generator *optc)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       /* Disable immediately. */
+       REG_UPDATE_2(OTG_CONTROL, OTG_DISABLE_POINT_CNTL, 0, OTG_MASTER_EN, 0);
+
+       /* CRTC disabled, so disable  clock. */
+       REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 100000);
+}
+
+static void optc32_disable_phantom_otg(struct timing_generator *optc)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       REG_UPDATE(OTG_CONTROL, OTG_MASTER_EN, 0);
+}
+
+void optc32_set_odm_bypass(struct timing_generator *optc,
+               const struct dc_crtc_timing *dc_crtc_timing)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+       enum h_timing_div_mode h_div = H_TIMING_NO_DIV;
+
+       REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
+                       OPTC_NUM_OF_INPUT_SEGMENT, 0,
+                       OPTC_SEG0_SRC_SEL, optc->inst,
+                       OPTC_SEG1_SRC_SEL, 0xf,
+                       OPTC_SEG2_SRC_SEL, 0xf,
+                       OPTC_SEG3_SRC_SEL, 0xf
+                       );
+
+       h_div = optc1_is_two_pixels_per_containter(dc_crtc_timing);
+       REG_UPDATE(OTG_H_TIMING_CNTL,
+                       OTG_H_TIMING_DIV_MODE, h_div);
+
+       REG_SET(OPTC_MEMORY_CONFIG, 0,
+                       OPTC_MEM_SEL, 0);
+       optc1->opp_count = 1;
+}
+
+static void optc32_setup_manual_trigger(struct timing_generator *optc)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+       struct dc *dc = optc->ctx->dc;
+
+       if (dc->caps.dmub_caps.mclk_sw && !dc->debug.disable_fams)
+               dc_dmub_srv_set_drr_manual_trigger_cmd(dc, optc->inst);
+       else {
+               /*
+                * MIN_MASK_EN is gone and MASK is now always enabled.
+                *
+                * To get it to it work with manual trigger we need to make sure
+                * we program the correct bit.
+                */
+               REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
+                               OTG_V_TOTAL_MIN_SEL, 1,
+                               OTG_V_TOTAL_MAX_SEL, 1,
+                               OTG_FORCE_LOCK_ON_EVENT, 0,
+                               OTG_SET_V_TOTAL_MIN_MASK, (1 << 1)); /* TRIGA */
+
+               // Setup manual flow control for EOF via TRIG_A
+               optc->funcs->setup_manual_trigger(optc);
+       }
+}
+
+static void optc32_set_drr(
+       struct timing_generator *optc,
+       const struct drr_params *params)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       if (params != NULL &&
+               params->vertical_total_max > 0 &&
+               params->vertical_total_min > 0) {
+
+               if (params->vertical_total_mid != 0) {
+
+                       REG_SET(OTG_V_TOTAL_MID, 0,
+                               OTG_V_TOTAL_MID, params->vertical_total_mid - 1);
+
+                       REG_UPDATE_2(OTG_V_TOTAL_CONTROL,
+                                       OTG_VTOTAL_MID_REPLACING_MAX_EN, 1,
+                                       OTG_VTOTAL_MID_FRAME_NUM,
+                                       (uint8_t)params->vertical_total_mid_frame_num);
+
+               }
+
+               optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1);
+       }
+
+       optc32_setup_manual_trigger(optc);
+}
+
+static struct timing_generator_funcs dcn32_tg_funcs = {
+               .validate_timing = optc1_validate_timing,
+               .program_timing = optc1_program_timing,
+               .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
+               .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
+               .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
+               .program_global_sync = optc1_program_global_sync,
+               .enable_crtc = optc32_enable_crtc,
+               .disable_crtc = optc32_disable_crtc,
+               .phantom_crtc_post_enable = optc32_phantom_crtc_post_enable,
+               .disable_phantom_crtc = optc32_disable_phantom_otg,
+               /* used by enable_timing_synchronization. Not need for FPGA */
+               .is_counter_moving = optc1_is_counter_moving,
+               .get_position = optc1_get_position,
+               .get_frame_count = optc1_get_vblank_counter,
+               .get_scanoutpos = optc1_get_crtc_scanoutpos,
+               .get_otg_active_size = optc1_get_otg_active_size,
+               .set_early_control = optc1_set_early_control,
+               /* used by enable_timing_synchronization. Not need for FPGA */
+               .wait_for_state = optc1_wait_for_state,
+               .set_blank_color = optc3_program_blank_color,
+               .did_triggered_reset_occur = optc1_did_triggered_reset_occur,
+               .triplebuffer_lock = optc3_triplebuffer_lock,
+               .triplebuffer_unlock = optc2_triplebuffer_unlock,
+               .enable_reset_trigger = optc1_enable_reset_trigger,
+               .enable_crtc_reset = optc1_enable_crtc_reset,
+               .disable_reset_trigger = optc1_disable_reset_trigger,
+               .lock = optc3_lock,
+               .unlock = optc1_unlock,
+               .lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,
+               .lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
+               .enable_optc_clock = optc1_enable_optc_clock,
+               .set_drr = optc32_set_drr,
+               .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
+               .set_vtotal_min_max = optc3_set_vtotal_min_max,
+               .set_static_screen_control = optc1_set_static_screen_control,
+               .program_stereo = optc1_program_stereo,
+               .is_stereo_left_eye = optc1_is_stereo_left_eye,
+               .tg_init = optc3_tg_init,
+               .is_tg_enabled = optc1_is_tg_enabled,
+               .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
+               .clear_optc_underflow = optc1_clear_optc_underflow,
+               .setup_global_swap_lock = NULL,
+               .get_crc = optc1_get_crc,
+               .configure_crc = optc1_configure_crc,
+               .set_dsc_config = optc3_set_dsc_config,
+               .get_dsc_status = optc2_get_dsc_status,
+               .set_dwb_source = NULL,
+               .set_odm_bypass = optc32_set_odm_bypass,
+               .set_odm_combine = optc32_set_odm_combine,
+               .get_odm_combine_segments = optc32_get_odm_combine_segments,
+               .set_h_timing_div_manual_mode = optc32_set_h_timing_div_manual_mode,
+               .get_optc_source = optc2_get_optc_source,
+               .set_out_mux = optc3_set_out_mux,
+               .set_drr_trigger_window = optc3_set_drr_trigger_window,
+               .set_vtotal_change_limit = optc3_set_vtotal_change_limit,
+               .set_gsl = optc2_set_gsl,
+               .set_gsl_source_select = optc2_set_gsl_source_select,
+               .set_vtg_params = optc1_set_vtg_params,
+               .program_manual_trigger = optc2_program_manual_trigger,
+               .setup_manual_trigger = optc2_setup_manual_trigger,
+               .get_hw_timing = optc1_get_hw_timing,
+};
+
+void dcn32_timing_generator_init(struct optc *optc1)
+{
+       optc1->base.funcs = &dcn32_tg_funcs;
+
+       optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
+       optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
+
+       optc1->min_h_blank = 32;
+       optc1->min_v_blank = 3;
+       optc1->min_v_blank_interlace = 5;
+       optc1->min_h_sync_width = 4;
+       optc1->min_v_sync_width = 1;
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
new file mode 100644 (file)
index 0000000..8ce3b17
--- /dev/null
@@ -0,0 +1,187 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_OPTC_DCN32_H__
+#define __DC_OPTC_DCN32_H__
+
+#include "dcn10/dcn10_optc.h"
+
+#define OPTC_COMMON_MASK_SH_LIST_DCN3_2(mask_sh)\
+       SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
+       SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
+       SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
+       SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
+       SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\
+       SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_START_X, mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_END_X, mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_START_Y, mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_END_Y, mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL2, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_X, mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_Y, mask_sh),\
+       SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\
+       SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
+       SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_START, mask_sh),\
+       SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_END, mask_sh),\
+       SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_START, mask_sh),\
+       SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_END, mask_sh),\
+       SF(OTG0_OTG_H_SYNC_A_CNTL, OTG_H_SYNC_A_POL, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
+       SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_START, mask_sh),\
+       SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_END, mask_sh),\
+       SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_START, mask_sh),\
+       SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_END, mask_sh),\
+       SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_A_POL, mask_sh),\
+       SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, mask_sh),\
+       SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
+       SF(OTG0_OTG_CONTROL, OTG_START_POINT_CNTL, mask_sh),\
+       SF(OTG0_OTG_CONTROL, OTG_DISABLE_POINT_CNTL, mask_sh),\
+       SF(OTG0_OTG_CONTROL, OTG_FIELD_NUMBER_CNTL, mask_sh),\
+       SF(OTG0_OTG_CONTROL, OTG_OUT_MUX, mask_sh),\
+       SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EN, mask_sh),\
+       SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_LINE_NUM, mask_sh),\
+       SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_POLARITY, mask_sh),\
+       SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EYE_FLAG_POLARITY, mask_sh),\
+       SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\
+       SF(OTG0_OTG_STEREO_STATUS, OTG_STEREO_CURRENT_EYE, mask_sh),\
+       SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_EN, mask_sh),\
+       SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\
+       SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MIN_EN, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\
+       SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\
+       SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\
+       SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\
+       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_SELECT, mask_sh),\
+       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_PIPE_SELECT, mask_sh),\
+       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_RISING_EDGE_DETECT_CNTL, mask_sh),\
+       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, mask_sh),\
+       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_POLARITY_SELECT, mask_sh),\
+       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FREQUENCY_SELECT, mask_sh),\
+       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_DELAY, mask_sh),\
+       SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_CLEAR, mask_sh),\
+       SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_EVENT_MASK, mask_sh),\
+       SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_FRAME_COUNT, mask_sh),\
+       SF(OTG0_OTG_STATUS_FRAME_COUNT, OTG_FRAME_COUNT, mask_sh),\
+       SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
+       SF(OTG0_OTG_STATUS, OTG_V_ACTIVE_DISP, mask_sh),\
+       SF(OTG0_OTG_STATUS_POSITION, OTG_HORZ_COUNT, mask_sh),\
+       SF(OTG0_OTG_STATUS_POSITION, OTG_VERT_COUNT, mask_sh),\
+       SF(OTG0_OTG_NOM_VERT_POSITION, OTG_VERT_COUNT_NOM, mask_sh),\
+       SF(OTG0_OTG_M_CONST_DTO0, OTG_M_CONST_DTO_PHASE, mask_sh),\
+       SF(OTG0_OTG_M_CONST_DTO1, OTG_M_CONST_DTO_MODULO, mask_sh),\
+       SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\
+       SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\
+       SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\
+       SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\
+       SF(OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE, mask_sh),\
+       SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_START, mask_sh),\
+       SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_END, mask_sh),\
+       SF(OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_INT_ENABLE, mask_sh),\
+       SF(OTG0_OTG_VERTICAL_INTERRUPT1_POSITION, OTG_VERTICAL_INTERRUPT1_LINE_START, mask_sh),\
+       SF(OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE, mask_sh),\
+       SF(OTG0_OTG_VERTICAL_INTERRUPT2_POSITION, OTG_VERTICAL_INTERRUPT2_LINE_START, mask_sh),\
+       SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\
+       SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\
+       SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\
+       SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\
+       SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\
+       SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
+       SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
+       SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
+       SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, mask_sh),\
+       SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, mask_sh),\
+       SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_AUTO_FORCE_VSYNC_MODE, mask_sh),\
+       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL0_EN, mask_sh),\
+       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL1_EN, mask_sh),\
+       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL2_EN, mask_sh),\
+       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_EN, mask_sh),\
+       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_FORCE_DELAY, mask_sh),\
+       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\
+       SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\
+       SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\
+       SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
+       SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\
+       SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\
+       SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\
+       SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_START, mask_sh),\
+       SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_END, mask_sh),\
+       SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_START, mask_sh),\
+       SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_END, mask_sh),\
+       SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_START, mask_sh),\
+       SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\
+       SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\
+       SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\
+       SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\
+       SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\
+       SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\
+       SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh),\
+       SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\
+       SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\
+       SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \
+       SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\
+       SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\
+       SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, mask_sh), \
+       SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, mask_sh), \
+       SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, mask_sh), \
+       SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_MODE, mask_sh), \
+       SF(OTG0_OTG_GSL_CONTROL, OTG_MASTER_UPDATE_LOCK_GSL_EN, mask_sh), \
+       SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_X, mask_sh), \
+       SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_LINE_NUM, mask_sh),\
+       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG0_SRC_SEL, mask_sh),\
+       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG1_SRC_SEL, mask_sh),\
+       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG2_SRC_SEL, mask_sh),\
+       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG3_SRC_SEL, mask_sh),\
+       SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, mask_sh),\
+       SF(ODM0_OPTC_MEMORY_CONFIG, OPTC_MEM_SEL, mask_sh),\
+       SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, mask_sh),\
+       SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\
+       SF(ODM0_OPTC_BYTES_PER_PIXEL, OPTC_DSC_BYTES_PER_PIXEL, mask_sh),\
+       SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, mask_sh),\
+       SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_SEGMENT_WIDTH, mask_sh),\
+       SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_START_X, mask_sh),\
+       SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_END_X, mask_sh),\
+       SF(OTG0_OTG_DRR_V_TOTAL_CHANGE, OTG_DRR_V_TOTAL_CHANGE_LIMIT, mask_sh),\
+       SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\
+       SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE_MANUAL, mask_sh),\
+       SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh),\
+       SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh)
+
+void dcn32_timing_generator_init(struct optc *optc1);
+void optc32_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode);
+void optc32_get_odm_combine_segments(struct timing_generator *tg, int *odm_combine_segments);
+void optc32_set_odm_bypass(struct timing_generator *optc,
+               const struct dc_crtc_timing *dc_crtc_timing);
+
+#endif /* __DC_OPTC_DCN32_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
new file mode 100644 (file)
index 0000000..a4a39f1
--- /dev/null
@@ -0,0 +1,290 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright 2023 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dcn35_optc.h"
+
+#include "dcn30/dcn30_optc.h"
+#include "dcn31/dcn31_optc.h"
+#include "dcn32/dcn32_optc.h"
+#include "reg_helper.h"
+#include "dc.h"
+#include "dcn_calc_math.h"
+
+#define REG(reg)\
+       optc1->tg_regs->reg
+
+#define CTX \
+       optc1->base.ctx
+
+#undef FN
+#define FN(reg_name, field_name) \
+       optc1->tg_shift->field_name, optc1->tg_mask->field_name
+
+/**
+ * optc35_set_odm_combine() - Enable CRTC - call ASIC Control Object to enable Timing generator.
+ *
+ * @optc: Output Pipe Timing Combine instance reference.
+ * @opp_id: Output Plane Processor instance ID.
+ * @opp_cnt: Output Plane Processor count.
+ * @timing: Timing parameters used to configure DCN blocks.
+ *
+ * Return: void.
+ */
+static void optc35_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
+               struct dc_crtc_timing *timing)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+       uint32_t memory_mask = 0;
+       int h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right;
+       int mpcc_hactive = h_active / opp_cnt;
+       /* Each memory instance is 2048x(314x2) bits to support half line of 4096 */
+       int odm_mem_count = (h_active + 2047) / 2048;
+
+       /*
+        * display <= 4k : 2 memories + 2 pipes
+        * 4k < display <= 8k : 4 memories + 2 pipes
+        * 8k < display <= 12k : 6 memories + 4 pipes
+        */
+       if (opp_cnt == 4) {
+               if (odm_mem_count <= 2)
+                       memory_mask = 0x3;
+               else if (odm_mem_count <= 4)
+                       memory_mask = 0xf;
+               else
+                       memory_mask = 0x3f;
+       } else {
+               if (odm_mem_count <= 2)
+                       memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2);
+               else if (odm_mem_count <= 4)
+                       memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);
+               else
+                       memory_mask = 0x77;
+       }
+
+       REG_SET(OPTC_MEMORY_CONFIG, 0,
+               OPTC_MEM_SEL, memory_mask);
+
+       if (opp_cnt == 2) {
+               REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
+                               OPTC_NUM_OF_INPUT_SEGMENT, 1,
+                               OPTC_SEG0_SRC_SEL, opp_id[0],
+                               OPTC_SEG1_SRC_SEL, opp_id[1]);
+       } else if (opp_cnt == 4) {
+               REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
+                               OPTC_NUM_OF_INPUT_SEGMENT, 3,
+                               OPTC_SEG0_SRC_SEL, opp_id[0],
+                               OPTC_SEG1_SRC_SEL, opp_id[1],
+                               OPTC_SEG2_SRC_SEL, opp_id[2],
+                               OPTC_SEG3_SRC_SEL, opp_id[3]);
+       }
+
+       REG_UPDATE(OPTC_WIDTH_CONTROL,
+                       OPTC_SEGMENT_WIDTH, mpcc_hactive);
+
+       REG_UPDATE(OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, opp_cnt - 1);
+       optc1->opp_count = opp_cnt;
+}
+
+static bool optc35_enable_crtc(struct timing_generator *optc)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       /* opp instance for OTG, 1 to 1 mapping and odm will adjust */
+       REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
+                       OPTC_SEG0_SRC_SEL, optc->inst);
+
+       /* VTG enable first is for HW workaround */
+       REG_UPDATE(CONTROL,
+                       VTG0_ENABLE, 1);
+
+       REG_SEQ_START();
+
+       /* Enable CRTC */
+       REG_UPDATE_2(OTG_CONTROL,
+                       OTG_DISABLE_POINT_CNTL, 2,
+                       OTG_MASTER_EN, 1);
+
+       REG_SEQ_SUBMIT();
+       REG_SEQ_WAIT_DONE();
+
+       return true;
+}
+
+/* disable_crtc */
+static bool optc35_disable_crtc(struct timing_generator *optc)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       /* disable otg request until end of the first line
+        * in the vertical blank region
+        */
+       REG_UPDATE(OTG_CONTROL,
+                       OTG_MASTER_EN, 0);
+
+       REG_UPDATE(CONTROL,
+                       VTG0_ENABLE, 0);
+
+       /* CRTC disabled, so disable  clock. */
+       REG_WAIT(OTG_CLOCK_CONTROL,
+                       OTG_BUSY, 0,
+                       1, 100000);
+       optc1_clear_optc_underflow(optc);
+
+       return true;
+}
+
+static void optc35_phantom_crtc_post_enable(struct timing_generator *optc)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       /* Disable immediately. */
+       REG_UPDATE_2(OTG_CONTROL, OTG_DISABLE_POINT_CNTL, 0, OTG_MASTER_EN, 0);
+
+       /* CRTC disabled, so disable  clock. */
+       REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 100000);
+}
+
+static bool optc35_configure_crc(struct timing_generator *optc,
+                                const struct crc_params *params)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       if (!optc1_is_tg_enabled(optc))
+               return false;
+       REG_WRITE(OTG_CRC_CNTL, 0);
+       if (!params->enable)
+               return true;
+       REG_UPDATE_2(OTG_CRC0_WINDOWA_X_CONTROL,
+                       OTG_CRC0_WINDOWA_X_START, params->windowa_x_start,
+                       OTG_CRC0_WINDOWA_X_END, params->windowa_x_end);
+       REG_UPDATE_2(OTG_CRC0_WINDOWA_Y_CONTROL,
+                       OTG_CRC0_WINDOWA_Y_START, params->windowa_y_start,
+                       OTG_CRC0_WINDOWA_Y_END, params->windowa_y_end);
+       REG_UPDATE_2(OTG_CRC0_WINDOWB_X_CONTROL,
+                       OTG_CRC0_WINDOWB_X_START, params->windowb_x_start,
+                       OTG_CRC0_WINDOWB_X_END, params->windowb_x_end);
+       REG_UPDATE_2(OTG_CRC0_WINDOWB_Y_CONTROL,
+                       OTG_CRC0_WINDOWB_Y_START, params->windowb_y_start,
+                       OTG_CRC0_WINDOWB_Y_END, params->windowb_y_end);
+       if (optc1->base.ctx->dc->debug.otg_crc_db && optc1->tg_mask->OTG_CRC_WINDOW_DB_EN != 0) {
+               REG_UPDATE_4(OTG_CRC_CNTL,
+                               OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0,
+                               OTG_CRC0_SELECT, params->selection,
+                               OTG_CRC_EN, 1,
+                               OTG_CRC_WINDOW_DB_EN, 1);
+       } else
+               REG_UPDATE_3(OTG_CRC_CNTL,
+                               OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0,
+                               OTG_CRC0_SELECT, params->selection,
+                               OTG_CRC_EN, 1);
+       return true;
+}
+
+static struct timing_generator_funcs dcn35_tg_funcs = {
+               .validate_timing = optc1_validate_timing,
+               .program_timing = optc1_program_timing,
+               .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
+               .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
+               .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
+               .program_global_sync = optc1_program_global_sync,
+               .enable_crtc = optc35_enable_crtc,
+               .disable_crtc = optc35_disable_crtc,
+               .immediate_disable_crtc = optc31_immediate_disable_crtc,
+               .phantom_crtc_post_enable = optc35_phantom_crtc_post_enable,
+               /* used by enable_timing_synchronization. Not need for FPGA */
+               .is_counter_moving = optc1_is_counter_moving,
+               .get_position = optc1_get_position,
+               .get_frame_count = optc1_get_vblank_counter,
+               .get_scanoutpos = optc1_get_crtc_scanoutpos,
+               .get_otg_active_size = optc1_get_otg_active_size,
+               .set_early_control = optc1_set_early_control,
+               /* used by enable_timing_synchronization. Not need for FPGA */
+               .wait_for_state = optc1_wait_for_state,
+               .set_blank_color = optc3_program_blank_color,
+               .did_triggered_reset_occur = optc1_did_triggered_reset_occur,
+               .triplebuffer_lock = optc3_triplebuffer_lock,
+               .triplebuffer_unlock = optc2_triplebuffer_unlock,
+               .enable_reset_trigger = optc1_enable_reset_trigger,
+               .enable_crtc_reset = optc1_enable_crtc_reset,
+               .disable_reset_trigger = optc1_disable_reset_trigger,
+               .lock = optc3_lock,
+               .unlock = optc1_unlock,
+               .lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,
+               .lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
+               .enable_optc_clock = optc1_enable_optc_clock,
+               .set_drr = optc31_set_drr,
+               .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
+               .set_vtotal_min_max = optc1_set_vtotal_min_max,
+               .set_static_screen_control = optc1_set_static_screen_control,
+               .program_stereo = optc1_program_stereo,
+               .is_stereo_left_eye = optc1_is_stereo_left_eye,
+               .tg_init = optc3_tg_init,
+               .is_tg_enabled = optc1_is_tg_enabled,
+               .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
+               .clear_optc_underflow = optc1_clear_optc_underflow,
+               .setup_global_swap_lock = NULL,
+               .get_crc = optc1_get_crc,
+               .configure_crc = optc35_configure_crc,
+               .set_dsc_config = optc3_set_dsc_config,
+               .get_dsc_status = optc2_get_dsc_status,
+               .set_dwb_source = NULL,
+               .set_odm_bypass = optc32_set_odm_bypass,
+               .set_odm_combine = optc35_set_odm_combine,
+               .get_optc_source = optc2_get_optc_source,
+               .set_h_timing_div_manual_mode = optc32_set_h_timing_div_manual_mode,
+               .set_out_mux = optc3_set_out_mux,
+               .set_drr_trigger_window = optc3_set_drr_trigger_window,
+               .set_vtotal_change_limit = optc3_set_vtotal_change_limit,
+               .set_gsl = optc2_set_gsl,
+               .set_gsl_source_select = optc2_set_gsl_source_select,
+               .set_vtg_params = optc1_set_vtg_params,
+               .program_manual_trigger = optc2_program_manual_trigger,
+               .setup_manual_trigger = optc2_setup_manual_trigger,
+               .get_hw_timing = optc1_get_hw_timing,
+               .init_odm = optc3_init_odm,
+};
+
+void dcn35_timing_generator_init(struct optc *optc1)
+{
+       optc1->base.funcs = &dcn35_tg_funcs;
+
+       optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
+       optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
+
+       optc1->min_h_blank = 32;
+       optc1->min_v_blank = 3;
+       optc1->min_v_blank_interlace = 5;
+       optc1->min_h_sync_width = 4;
+       optc1->min_v_sync_width = 1;
+
+       dcn35_timing_generator_set_fgcg(
+               optc1, CTX->dc->debug.enable_fine_grain_clock_gating.bits.optc);
+}
+
+void dcn35_timing_generator_set_fgcg(struct optc *optc1, bool enable)
+{
+       REG_UPDATE(OPTC_CLOCK_CONTROL, OPTC_FGCG_REP_DIS, !enable);
+}
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
new file mode 100644 (file)
index 0000000..1f422e4
--- /dev/null
@@ -0,0 +1,74 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright 2023 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_OPTC_DCN35_H__
+#define __DC_OPTC_DCN35_H__
+
+#include "dcn10/dcn10_optc.h"
+#include "dcn32/dcn32_optc.h"
+#define OPTC_COMMON_MASK_SH_LIST_DCN3_5(mask_sh)\
+       OPTC_COMMON_MASK_SH_LIST_DCN3_2(mask_sh),\
+       SF(OTG0_OTG_CRC_CNTL, OTG_CRC_WINDOW_DB_EN, mask_sh),\
+       SF(OTG0_OTG_CRC1_DATA_RG, CRC1_R_CR, mask_sh),\
+       SF(OTG0_OTG_CRC1_DATA_RG, CRC1_G_Y, mask_sh),\
+       SF(OTG0_OTG_CRC1_DATA_B,  CRC1_B_CB, mask_sh),\
+       SF(OTG0_OTG_CRC2_DATA_RG, CRC2_R_CR, mask_sh),\
+       SF(OTG0_OTG_CRC2_DATA_RG, CRC2_G_Y, mask_sh),\
+       SF(OTG0_OTG_CRC2_DATA_B,  CRC2_B_CB, mask_sh),\
+       SF(OTG0_OTG_CRC3_DATA_RG, CRC3_R_CR, mask_sh),\
+       SF(OTG0_OTG_CRC3_DATA_RG, CRC3_G_Y, mask_sh),\
+       SF(OTG0_OTG_CRC3_DATA_B,  CRC3_B_CB, mask_sh),\
+       SF(OTG0_OTG_CRC1_WINDOWA_X_CONTROL, OTG_CRC1_WINDOWA_X_START, mask_sh),\
+       SF(OTG0_OTG_CRC1_WINDOWA_X_CONTROL, OTG_CRC1_WINDOWA_X_END, mask_sh),\
+       SF(OTG0_OTG_CRC1_WINDOWA_Y_CONTROL, OTG_CRC1_WINDOWA_Y_START, mask_sh),\
+       SF(OTG0_OTG_CRC1_WINDOWA_Y_CONTROL, OTG_CRC1_WINDOWA_Y_END, mask_sh),\
+       SF(OTG0_OTG_CRC1_WINDOWB_X_CONTROL, OTG_CRC1_WINDOWB_X_START, mask_sh),\
+       SF(OTG0_OTG_CRC1_WINDOWB_X_CONTROL, OTG_CRC1_WINDOWB_X_END, mask_sh),\
+       SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL, OTG_CRC1_WINDOWB_Y_START, mask_sh),\
+       SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL, OTG_CRC1_WINDOWB_Y_END, mask_sh),\
+       SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK, OTG_CRC0_WINDOWA_X_START_READBACK, mask_sh),\
+       SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK, OTG_CRC0_WINDOWA_X_END_READBACK, mask_sh),\
+       SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK, OTG_CRC0_WINDOWA_Y_START_READBACK, mask_sh),\
+       SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK, OTG_CRC0_WINDOWA_Y_END_READBACK, mask_sh),\
+       SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK, OTG_CRC0_WINDOWB_X_START_READBACK, mask_sh),\
+       SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK, OTG_CRC0_WINDOWB_X_END_READBACK, mask_sh),\
+       SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK, OTG_CRC0_WINDOWB_Y_START_READBACK, mask_sh),\
+       SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK, OTG_CRC0_WINDOWB_Y_END_READBACK, mask_sh),\
+       SF(OTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK, OTG_CRC1_WINDOWA_X_START_READBACK, mask_sh),\
+       SF(OTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK, OTG_CRC1_WINDOWA_X_END_READBACK, mask_sh),\
+       SF(OTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK, OTG_CRC1_WINDOWA_Y_START_READBACK, mask_sh),\
+       SF(OTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK, OTG_CRC1_WINDOWA_Y_END_READBACK, mask_sh),\
+       SF(OTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK, OTG_CRC1_WINDOWB_X_START_READBACK, mask_sh),\
+       SF(OTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK, OTG_CRC1_WINDOWB_X_END_READBACK, mask_sh),\
+       SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK, OTG_CRC1_WINDOWB_Y_START_READBACK, mask_sh),\
+       SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK, OTG_CRC1_WINDOWB_Y_END_READBACK, mask_sh),\
+       SF(OPTC_CLOCK_CONTROL, OPTC_FGCG_REP_DIS, mask_sh)
+
+void dcn35_timing_generator_init(struct optc *optc1);
+
+void dcn35_timing_generator_set_fgcg(struct optc *optc1, bool enable);
+
+#endif /* __DC_OPTC_DCN35_H__ */